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1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s2; -global-isel=1 SI run line skipped since store not yet implemented.3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s4; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s5; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=GCN %s6; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=MEMTIME -check-prefix=GCN %s7; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=MEMTIME -check-prefix=GCN %s8; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=MEMTIME -check-prefix=GCN %s9; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GETREG,GETREG-SDAG -check-prefix=GCN %s10; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GETREG,GETREG-GISEL -check-prefix=GCN %s11; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s12; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s13; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s14; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s15 16declare i64 @llvm.readcyclecounter() #017 18; GCN-LABEL: {{^}}test_readcyclecounter:19; MEMTIME-DAG: s_memtime s{{\[[0-9]+:[0-9]+\]}}20; GCN-DAG: s_load_{{dwordx2|b64}}21; GFX12: s_getreg_b32 [[HI1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES_HI)22; GFX12: s_getreg_b32 [[LO1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES_LO)23; GFX12: s_getreg_b32 [[HI2:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES_HI)24; GFX12: s_cmp_eq_u32 [[HI1]], [[HI2]]25; GFX12: s_cselect_b32 {{s[0-9]+}}, [[LO1]], 026; GFX1250: s_get_shader_cycles_u64 s{{\[[0-9]+:[0-9]+\]}}27; GCN-DAG: kmcnt28; MEMTIME: store_dwordx229; SIVI-NOT: kmcnt30; MEMTIME: s_memtime s{{\[[0-9]+:[0-9]+\]}}31; MEMTIME: store_dwordx232 33; GETREG-GISEL-DAG: s_mov_b32 s[[SZERO:[0-9]+]], 034; GETREG-GISEL-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], s[[SZERO]]35; GETREG-SDAG-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 036; GETREG-DAG: s_getreg_b32 [[CNT1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20)37; GETREG-DAG: v_mov_b32_e32 v[[VCNT1:[0-9]+]], [[CNT1]]38; GETREG: global_store_{{dwordx2|b64}} v{{.+}}, v[[[VCNT1]]:[[ZERO]]]39; GETREG: s_getreg_b32 [[CNT2:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20)40; GETREG: v_mov_b32_e32 v[[VCNT2:[0-9]+]], [[CNT2]]41; GETREG: global_store_{{dwordx2|b64}} v{{.+}}, v[[[VCNT2]]:[[ZERO]]]42 43define amdgpu_kernel void @test_readcyclecounter(ptr addrspace(1) %out) #0 {44 %cycle0 = call i64 @llvm.readcyclecounter()45 store volatile i64 %cycle0, ptr addrspace(1) %out46 47 %cycle1 = call i64 @llvm.readcyclecounter()48 store volatile i64 %cycle1, ptr addrspace(1) %out49 ret void50}51 52; This test used to crash in ScheduleDAG.53;54; GCN-LABEL: {{^}}test_readcyclecounter_smem:55; MEMTIME-DAG: s_memtime56; GFX12: s_getreg_b32 [[HI1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES_HI)57; GFX12: s_getreg_b32 [[LO1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES_LO)58; GFX12: s_getreg_b32 [[HI2:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES_HI)59; GFX1250: s_get_shader_cycles_u64 s{{\[[0-9]+:[0-9]+\]}}60; GCN-DAG: s_load_{{dword|b32|b64}}61; GETREG-DAG: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_SHADER_CYCLES, 0, 20)62; GFX12: s_cmp_eq_u32 [[HI1]], [[HI2]]63; GFX12: s_cselect_b32 {{s[0-9]+}}, [[LO1]], 064define amdgpu_cs i32 @test_readcyclecounter_smem(ptr addrspace(4) inreg %in) #0 {65 %cycle0 = call i64 @llvm.readcyclecounter()66 %in.v = load i64, ptr addrspace(4) %in67 %r.64 = add i64 %cycle0, %in.v68 %r.32 = trunc i64 %r.64 to i3269 ret i32 %r.3270}71 72attributes #0 = { nounwind }73