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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx600 < %s | FileCheck -check-prefixes=GFX67,GFX6 %s3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX67,GFX7 %s4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s6; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9,GFX90A %s7; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10 %s8; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s9 10; We want to undo these canonicalizations to enable mad matching:11; (x * y) + x --> x * (y + 1)12; (x * y) - x --> x * (y - 1)13 14define i32 @v_mul_add_1_i32(i32 %x, i32 %y) {15; GFX67-LABEL: v_mul_add_1_i32:16; GFX67: ; %bb.0:17; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)18; GFX67-NEXT: v_mul_lo_u32 v1, v0, v119; GFX67-NEXT: v_add_i32_e32 v0, vcc, v1, v020; GFX67-NEXT: s_setpc_b64 s[30:31]21;22; GFX8-LABEL: v_mul_add_1_i32:23; GFX8: ; %bb.0:24; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)25; GFX8-NEXT: v_mul_lo_u32 v1, v0, v126; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v027; GFX8-NEXT: s_setpc_b64 s[30:31]28;29; GFX9-LABEL: v_mul_add_1_i32:30; GFX9: ; %bb.0:31; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[0:1]33; GFX9-NEXT: s_setpc_b64 s[30:31]34;35; GFX10-LABEL: v_mul_add_1_i32:36; GFX10: ; %bb.0:37; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)38; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[0:1]39; GFX10-NEXT: s_setpc_b64 s[30:31]40;41; GFX1250-LABEL: v_mul_add_1_i32:42; GFX1250: ; %bb.0:43; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x044; GFX1250-NEXT: s_wait_kmcnt 0x045; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v046; GFX1250-NEXT: s_set_pc_i64 s[30:31]47 %add = add i32 %y, 148 %mul = mul i32 %x, %add49 ret i32 %mul50}51 52define i32 @v_mul_add_1_i32_commute(i32 %x, i32 %y) {53; GFX67-LABEL: v_mul_add_1_i32_commute:54; GFX67: ; %bb.0:55; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GFX67-NEXT: v_mul_lo_u32 v1, v0, v157; GFX67-NEXT: v_add_i32_e32 v0, vcc, v1, v058; GFX67-NEXT: s_setpc_b64 s[30:31]59;60; GFX8-LABEL: v_mul_add_1_i32_commute:61; GFX8: ; %bb.0:62; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)63; GFX8-NEXT: v_mul_lo_u32 v1, v0, v164; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v065; GFX8-NEXT: s_setpc_b64 s[30:31]66;67; GFX9-LABEL: v_mul_add_1_i32_commute:68; GFX9: ; %bb.0:69; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[0:1]71; GFX9-NEXT: s_setpc_b64 s[30:31]72;73; GFX10-LABEL: v_mul_add_1_i32_commute:74; GFX10: ; %bb.0:75; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[0:1]77; GFX10-NEXT: s_setpc_b64 s[30:31]78;79; GFX1250-LABEL: v_mul_add_1_i32_commute:80; GFX1250: ; %bb.0:81; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x082; GFX1250-NEXT: s_wait_kmcnt 0x083; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v084; GFX1250-NEXT: s_set_pc_i64 s[30:31]85 %add = add i32 %y, 186 %mul = mul i32 %add, %x87 ret i32 %mul88}89 90define i32 @v_mul_add_x_i32(i32 %x, i32 %y) {91; GFX67-LABEL: v_mul_add_x_i32:92; GFX67: ; %bb.0:93; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; GFX67-NEXT: v_mul_lo_u32 v1, v0, v195; GFX67-NEXT: v_add_i32_e32 v0, vcc, v0, v196; GFX67-NEXT: s_setpc_b64 s[30:31]97;98; GFX8-LABEL: v_mul_add_x_i32:99; GFX8: ; %bb.0:100; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)101; GFX8-NEXT: v_mul_lo_u32 v1, v0, v1102; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1103; GFX8-NEXT: s_setpc_b64 s[30:31]104;105; GFX9-LABEL: v_mul_add_x_i32:106; GFX9: ; %bb.0:107; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[0:1]109; GFX9-NEXT: s_setpc_b64 s[30:31]110;111; GFX10-LABEL: v_mul_add_x_i32:112; GFX10: ; %bb.0:113; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[0:1]115; GFX10-NEXT: s_setpc_b64 s[30:31]116;117; GFX1250-LABEL: v_mul_add_x_i32:118; GFX1250: ; %bb.0:119; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0120; GFX1250-NEXT: s_wait_kmcnt 0x0121; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v0122; GFX1250-NEXT: s_set_pc_i64 s[30:31]123 %mul = mul i32 %x, %y124 %add = add i32 %x, %mul125 ret i32 %add126}127 128define i32 @v_mul_sub_1_i32(i32 %x, i32 %y) {129; GFX67-LABEL: v_mul_sub_1_i32:130; GFX67: ; %bb.0:131; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)132; GFX67-NEXT: v_add_i32_e32 v1, vcc, -1, v1133; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1134; GFX67-NEXT: s_setpc_b64 s[30:31]135;136; GFX8-LABEL: v_mul_sub_1_i32:137; GFX8: ; %bb.0:138; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; GFX8-NEXT: v_add_u32_e32 v1, vcc, -1, v1140; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1141; GFX8-NEXT: s_setpc_b64 s[30:31]142;143; GFX9-LABEL: v_mul_sub_1_i32:144; GFX9: ; %bb.0:145; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)146; GFX9-NEXT: v_add_u32_e32 v1, -1, v1147; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1148; GFX9-NEXT: s_setpc_b64 s[30:31]149;150; GFX10-LABEL: v_mul_sub_1_i32:151; GFX10: ; %bb.0:152; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)153; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1154; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1155; GFX10-NEXT: s_setpc_b64 s[30:31]156;157; GFX1250-LABEL: v_mul_sub_1_i32:158; GFX1250: ; %bb.0:159; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0160; GFX1250-NEXT: s_wait_kmcnt 0x0161; GFX1250-NEXT: v_add_nc_u32_e32 v1, -1, v1162; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)163; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1164; GFX1250-NEXT: s_set_pc_i64 s[30:31]165 %sub = sub i32 %y, 1166 %mul = mul i32 %x, %sub167 ret i32 %mul168}169 170define i32 @v_mul_sub_1_i32_commute(i32 %x, i32 %y) {171; GFX67-LABEL: v_mul_sub_1_i32_commute:172; GFX67: ; %bb.0:173; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; GFX67-NEXT: v_add_i32_e32 v1, vcc, -1, v1175; GFX67-NEXT: v_mul_lo_u32 v0, v1, v0176; GFX67-NEXT: s_setpc_b64 s[30:31]177;178; GFX8-LABEL: v_mul_sub_1_i32_commute:179; GFX8: ; %bb.0:180; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)181; GFX8-NEXT: v_add_u32_e32 v1, vcc, -1, v1182; GFX8-NEXT: v_mul_lo_u32 v0, v1, v0183; GFX8-NEXT: s_setpc_b64 s[30:31]184;185; GFX9-LABEL: v_mul_sub_1_i32_commute:186; GFX9: ; %bb.0:187; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)188; GFX9-NEXT: v_add_u32_e32 v1, -1, v1189; GFX9-NEXT: v_mul_lo_u32 v0, v1, v0190; GFX9-NEXT: s_setpc_b64 s[30:31]191;192; GFX10-LABEL: v_mul_sub_1_i32_commute:193; GFX10: ; %bb.0:194; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)195; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1196; GFX10-NEXT: v_mul_lo_u32 v0, v1, v0197; GFX10-NEXT: s_setpc_b64 s[30:31]198;199; GFX1250-LABEL: v_mul_sub_1_i32_commute:200; GFX1250: ; %bb.0:201; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0202; GFX1250-NEXT: s_wait_kmcnt 0x0203; GFX1250-NEXT: v_add_nc_u32_e32 v1, -1, v1204; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)205; GFX1250-NEXT: v_mul_lo_u32 v0, v1, v0206; GFX1250-NEXT: s_set_pc_i64 s[30:31]207 %sub = sub i32 %y, 1208 %mul = mul i32 %sub, %x209 ret i32 %mul210}211 212define i32 @v_mul_sub_x_i32(i32 %x, i32 %y) {213; GFX67-LABEL: v_mul_sub_x_i32:214; GFX67: ; %bb.0:215; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)216; GFX67-NEXT: v_mul_lo_u32 v1, v0, v1217; GFX67-NEXT: v_sub_i32_e32 v0, vcc, v1, v0218; GFX67-NEXT: s_setpc_b64 s[30:31]219;220; GFX8-LABEL: v_mul_sub_x_i32:221; GFX8: ; %bb.0:222; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX8-NEXT: v_mul_lo_u32 v1, v0, v1224; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v1, v0225; GFX8-NEXT: s_setpc_b64 s[30:31]226;227; GFX9-LABEL: v_mul_sub_x_i32:228; GFX9: ; %bb.0:229; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1231; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0232; GFX9-NEXT: s_setpc_b64 s[30:31]233;234; GFX10-LABEL: v_mul_sub_x_i32:235; GFX10: ; %bb.0:236; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)237; GFX10-NEXT: v_mul_lo_u32 v1, v0, v1238; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0239; GFX10-NEXT: s_setpc_b64 s[30:31]240;241; GFX1250-LABEL: v_mul_sub_x_i32:242; GFX1250: ; %bb.0:243; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0244; GFX1250-NEXT: s_wait_kmcnt 0x0245; GFX1250-NEXT: v_mul_lo_u32 v1, v0, v1246; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)247; GFX1250-NEXT: v_sub_nc_u32_e32 v0, v1, v0248; GFX1250-NEXT: s_set_pc_i64 s[30:31]249 %mul = mul i32 %x, %y250 %sub = sub i32 %mul, %x251 ret i32 %sub252}253 254define i32 @v_mul_add_2_i32(i32 %x, i32 %y) {255; GFX67-LABEL: v_mul_add_2_i32:256; GFX67: ; %bb.0:257; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)258; GFX67-NEXT: v_add_i32_e32 v1, vcc, 2, v1259; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1260; GFX67-NEXT: s_setpc_b64 s[30:31]261;262; GFX8-LABEL: v_mul_add_2_i32:263; GFX8: ; %bb.0:264; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)265; GFX8-NEXT: v_add_u32_e32 v1, vcc, 2, v1266; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1267; GFX8-NEXT: s_setpc_b64 s[30:31]268;269; GFX9-LABEL: v_mul_add_2_i32:270; GFX9: ; %bb.0:271; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)272; GFX9-NEXT: v_add_u32_e32 v1, 2, v1273; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1274; GFX9-NEXT: s_setpc_b64 s[30:31]275;276; GFX10-LABEL: v_mul_add_2_i32:277; GFX10: ; %bb.0:278; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)279; GFX10-NEXT: v_add_nc_u32_e32 v1, 2, v1280; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1281; GFX10-NEXT: s_setpc_b64 s[30:31]282;283; GFX1250-LABEL: v_mul_add_2_i32:284; GFX1250: ; %bb.0:285; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0286; GFX1250-NEXT: s_wait_kmcnt 0x0287; GFX1250-NEXT: v_add_nc_u32_e32 v1, 2, v1288; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)289; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1290; GFX1250-NEXT: s_set_pc_i64 s[30:31]291 %add = add i32 %y, 2292 %mul = mul i32 %x, %add293 ret i32 %mul294}295 296define i32 @v_mul_sub_2_i32(i32 %x, i32 %y) {297; GFX67-LABEL: v_mul_sub_2_i32:298; GFX67: ; %bb.0:299; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)300; GFX67-NEXT: v_add_i32_e32 v1, vcc, -2, v1301; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1302; GFX67-NEXT: s_setpc_b64 s[30:31]303;304; GFX8-LABEL: v_mul_sub_2_i32:305; GFX8: ; %bb.0:306; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)307; GFX8-NEXT: v_add_u32_e32 v1, vcc, -2, v1308; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1309; GFX8-NEXT: s_setpc_b64 s[30:31]310;311; GFX9-LABEL: v_mul_sub_2_i32:312; GFX9: ; %bb.0:313; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)314; GFX9-NEXT: v_add_u32_e32 v1, -2, v1315; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1316; GFX9-NEXT: s_setpc_b64 s[30:31]317;318; GFX10-LABEL: v_mul_sub_2_i32:319; GFX10: ; %bb.0:320; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)321; GFX10-NEXT: v_add_nc_u32_e32 v1, -2, v1322; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1323; GFX10-NEXT: s_setpc_b64 s[30:31]324;325; GFX1250-LABEL: v_mul_sub_2_i32:326; GFX1250: ; %bb.0:327; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0328; GFX1250-NEXT: s_wait_kmcnt 0x0329; GFX1250-NEXT: v_add_nc_u32_e32 v1, -2, v1330; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)331; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1332; GFX1250-NEXT: s_set_pc_i64 s[30:31]333 %sub = sub i32 %y, 2334 %mul = mul i32 %x, %sub335 ret i32 %mul336}337 338define i32 @v_mul_add_65_i32(i32 %x, i32 %y) {339; GFX67-LABEL: v_mul_add_65_i32:340; GFX67: ; %bb.0:341; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)342; GFX67-NEXT: v_add_i32_e32 v1, vcc, 0x41, v1343; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1344; GFX67-NEXT: s_setpc_b64 s[30:31]345;346; GFX8-LABEL: v_mul_add_65_i32:347; GFX8: ; %bb.0:348; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)349; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x41, v1350; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1351; GFX8-NEXT: s_setpc_b64 s[30:31]352;353; GFX9-LABEL: v_mul_add_65_i32:354; GFX9: ; %bb.0:355; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)356; GFX9-NEXT: v_add_u32_e32 v1, 0x41, v1357; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1358; GFX9-NEXT: s_setpc_b64 s[30:31]359;360; GFX10-LABEL: v_mul_add_65_i32:361; GFX10: ; %bb.0:362; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)363; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x41, v1364; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1365; GFX10-NEXT: s_setpc_b64 s[30:31]366;367; GFX1250-LABEL: v_mul_add_65_i32:368; GFX1250: ; %bb.0:369; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0370; GFX1250-NEXT: s_wait_kmcnt 0x0371; GFX1250-NEXT: v_add_nc_u32_e32 v1, 0x41, v1372; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)373; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1374; GFX1250-NEXT: s_set_pc_i64 s[30:31]375 %add = add i32 %y, 65376 %mul = mul i32 %x, %add377 ret i32 %mul378}379 380define i32 @v_mul_sub_65_i32(i32 %x, i32 %y) {381; GFX67-LABEL: v_mul_sub_65_i32:382; GFX67: ; %bb.0:383; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; GFX67-NEXT: v_add_i32_e32 v1, vcc, 0xffffffbf, v1385; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1386; GFX67-NEXT: s_setpc_b64 s[30:31]387;388; GFX8-LABEL: v_mul_sub_65_i32:389; GFX8: ; %bb.0:390; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)391; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0xffffffbf, v1392; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1393; GFX8-NEXT: s_setpc_b64 s[30:31]394;395; GFX9-LABEL: v_mul_sub_65_i32:396; GFX9: ; %bb.0:397; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)398; GFX9-NEXT: v_add_u32_e32 v1, 0xffffffbf, v1399; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1400; GFX9-NEXT: s_setpc_b64 s[30:31]401;402; GFX10-LABEL: v_mul_sub_65_i32:403; GFX10: ; %bb.0:404; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)405; GFX10-NEXT: v_add_nc_u32_e32 v1, 0xffffffbf, v1406; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1407; GFX10-NEXT: s_setpc_b64 s[30:31]408;409; GFX1250-LABEL: v_mul_sub_65_i32:410; GFX1250: ; %bb.0:411; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0412; GFX1250-NEXT: s_wait_kmcnt 0x0413; GFX1250-NEXT: v_add_nc_u32_e32 v1, 0xffffffbf, v1414; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)415; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1416; GFX1250-NEXT: s_set_pc_i64 s[30:31]417 %sub = sub i32 %y, 65418 %mul = mul i32 %x, %sub419 ret i32 %mul420}421 422define i24 @v_mul_add_1_i24_zext(i24 zeroext %x, i24 zeroext %y) {423; GFX67-LABEL: v_mul_add_1_i24_zext:424; GFX67: ; %bb.0:425; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v1427; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1428; GFX67-NEXT: s_setpc_b64 s[30:31]429;430; GFX8-LABEL: v_mul_add_1_i24_zext:431; GFX8: ; %bb.0:432; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)433; GFX8-NEXT: v_add_u32_e32 v1, vcc, 1, v1434; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v1435; GFX8-NEXT: s_setpc_b64 s[30:31]436;437; GFX9-LABEL: v_mul_add_1_i24_zext:438; GFX9: ; %bb.0:439; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)440; GFX9-NEXT: v_add_u32_e32 v1, 1, v1441; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1442; GFX9-NEXT: s_setpc_b64 s[30:31]443;444; GFX10-LABEL: v_mul_add_1_i24_zext:445; GFX10: ; %bb.0:446; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)447; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v1448; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v1449; GFX10-NEXT: s_setpc_b64 s[30:31]450;451; GFX1250-LABEL: v_mul_add_1_i24_zext:452; GFX1250: ; %bb.0:453; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0454; GFX1250-NEXT: s_wait_kmcnt 0x0455; GFX1250-NEXT: v_add_nc_u32_e32 v1, 1, v1456; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)457; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v1458; GFX1250-NEXT: s_set_pc_i64 s[30:31]459 %add = add i24 %y, 1460 %mul = mul i24 %x, %add461 ret i24 %mul462}463 464define i24 @v_mul_sub_1_i24_zext(i24 zeroext %x, i24 zeroext %y) {465; GFX67-LABEL: v_mul_sub_1_i24_zext:466; GFX67: ; %bb.0:467; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; GFX67-NEXT: v_add_i32_e32 v1, vcc, -1, v1469; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1470; GFX67-NEXT: s_setpc_b64 s[30:31]471;472; GFX8-LABEL: v_mul_sub_1_i24_zext:473; GFX8: ; %bb.0:474; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)475; GFX8-NEXT: v_add_u32_e32 v1, vcc, -1, v1476; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v1477; GFX8-NEXT: s_setpc_b64 s[30:31]478;479; GFX9-LABEL: v_mul_sub_1_i24_zext:480; GFX9: ; %bb.0:481; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)482; GFX9-NEXT: v_add_u32_e32 v1, -1, v1483; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1484; GFX9-NEXT: s_setpc_b64 s[30:31]485;486; GFX10-LABEL: v_mul_sub_1_i24_zext:487; GFX10: ; %bb.0:488; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)489; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1490; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v1491; GFX10-NEXT: s_setpc_b64 s[30:31]492;493; GFX1250-LABEL: v_mul_sub_1_i24_zext:494; GFX1250: ; %bb.0:495; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0496; GFX1250-NEXT: s_wait_kmcnt 0x0497; GFX1250-NEXT: v_add_nc_u32_e32 v1, -1, v1498; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)499; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v1500; GFX1250-NEXT: s_set_pc_i64 s[30:31]501 %sub = sub i24 %y, 1502 %mul = mul i24 %x, %sub503 ret i24 %mul504}505 506define i24 @v_add_mul_i24_zext_1(i24 zeroext %x, i24 zeroext %y) {507; GFX67-LABEL: v_add_mul_i24_zext_1:508; GFX67: ; %bb.0:509; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)510; GFX67-NEXT: v_mad_u32_u24 v0, v0, v1, v0511; GFX67-NEXT: s_setpc_b64 s[30:31]512;513; GFX8-LABEL: v_add_mul_i24_zext_1:514; GFX8: ; %bb.0:515; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)516; GFX8-NEXT: v_mad_u32_u24 v0, v0, v1, v0517; GFX8-NEXT: s_setpc_b64 s[30:31]518;519; GFX9-LABEL: v_add_mul_i24_zext_1:520; GFX9: ; %bb.0:521; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)522; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v0523; GFX9-NEXT: s_setpc_b64 s[30:31]524;525; GFX10-LABEL: v_add_mul_i24_zext_1:526; GFX10: ; %bb.0:527; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v0529; GFX10-NEXT: s_setpc_b64 s[30:31]530;531; GFX1250-LABEL: v_add_mul_i24_zext_1:532; GFX1250: ; %bb.0:533; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0534; GFX1250-NEXT: s_wait_kmcnt 0x0535; GFX1250-NEXT: v_mad_u32_u24 v0, v0, v1, v0536; GFX1250-NEXT: s_set_pc_i64 s[30:31]537 %mul = mul i24 %x, %y538 %add = add i24 %mul, %x539 ret i24 %add540}541 542define i24 @v_mul_add_1_i24_sext(i24 signext %x, i24 signext %y) {543; GFX67-LABEL: v_mul_add_1_i24_sext:544; GFX67: ; %bb.0:545; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)546; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v1547; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1548; GFX67-NEXT: s_setpc_b64 s[30:31]549;550; GFX8-LABEL: v_mul_add_1_i24_sext:551; GFX8: ; %bb.0:552; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)553; GFX8-NEXT: v_add_u32_e32 v1, vcc, 1, v1554; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v1555; GFX8-NEXT: s_setpc_b64 s[30:31]556;557; GFX9-LABEL: v_mul_add_1_i24_sext:558; GFX9: ; %bb.0:559; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)560; GFX9-NEXT: v_add_u32_e32 v1, 1, v1561; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1562; GFX9-NEXT: s_setpc_b64 s[30:31]563;564; GFX10-LABEL: v_mul_add_1_i24_sext:565; GFX10: ; %bb.0:566; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)567; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v1568; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v1569; GFX10-NEXT: s_setpc_b64 s[30:31]570;571; GFX1250-LABEL: v_mul_add_1_i24_sext:572; GFX1250: ; %bb.0:573; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0574; GFX1250-NEXT: s_wait_kmcnt 0x0575; GFX1250-NEXT: v_add_nc_u32_e32 v1, 1, v1576; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)577; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v1578; GFX1250-NEXT: s_set_pc_i64 s[30:31]579 %add = add i24 %y, 1580 %mul = mul i24 %x, %add581 ret i24 %mul582}583 584define i24 @v_add_mul_i24_sext_1(i24 signext %x, i24 signext %y) {585; GFX67-LABEL: v_add_mul_i24_sext_1:586; GFX67: ; %bb.0:587; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)588; GFX67-NEXT: v_mad_u32_u24 v0, v0, v1, v0589; GFX67-NEXT: s_setpc_b64 s[30:31]590;591; GFX8-LABEL: v_add_mul_i24_sext_1:592; GFX8: ; %bb.0:593; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)594; GFX8-NEXT: v_mad_u32_u24 v0, v0, v1, v0595; GFX8-NEXT: s_setpc_b64 s[30:31]596;597; GFX9-LABEL: v_add_mul_i24_sext_1:598; GFX9: ; %bb.0:599; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)600; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v0601; GFX9-NEXT: s_setpc_b64 s[30:31]602;603; GFX10-LABEL: v_add_mul_i24_sext_1:604; GFX10: ; %bb.0:605; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)606; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v0607; GFX10-NEXT: s_setpc_b64 s[30:31]608;609; GFX1250-LABEL: v_add_mul_i24_sext_1:610; GFX1250: ; %bb.0:611; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0612; GFX1250-NEXT: s_wait_kmcnt 0x0613; GFX1250-NEXT: v_mad_u32_u24 v0, v0, v1, v0614; GFX1250-NEXT: s_set_pc_i64 s[30:31]615 %mul = mul i24 %x, %y616 %add = add i24 %mul, %x617 ret i24 %add618}619 620define i24 @v_mul_sub_1_i24_sext(i24 signext %x, i24 signext %y) {621; GFX67-LABEL: v_mul_sub_1_i24_sext:622; GFX67: ; %bb.0:623; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)624; GFX67-NEXT: v_add_i32_e32 v1, vcc, -1, v1625; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1626; GFX67-NEXT: s_setpc_b64 s[30:31]627;628; GFX8-LABEL: v_mul_sub_1_i24_sext:629; GFX8: ; %bb.0:630; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)631; GFX8-NEXT: v_add_u32_e32 v1, vcc, -1, v1632; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v1633; GFX8-NEXT: s_setpc_b64 s[30:31]634;635; GFX9-LABEL: v_mul_sub_1_i24_sext:636; GFX9: ; %bb.0:637; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)638; GFX9-NEXT: v_add_u32_e32 v1, -1, v1639; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v1640; GFX9-NEXT: s_setpc_b64 s[30:31]641;642; GFX10-LABEL: v_mul_sub_1_i24_sext:643; GFX10: ; %bb.0:644; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)645; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1646; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v1647; GFX10-NEXT: s_setpc_b64 s[30:31]648;649; GFX1250-LABEL: v_mul_sub_1_i24_sext:650; GFX1250: ; %bb.0:651; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0652; GFX1250-NEXT: s_wait_kmcnt 0x0653; GFX1250-NEXT: v_add_nc_u32_e32 v1, -1, v1654; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)655; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v1656; GFX1250-NEXT: s_set_pc_i64 s[30:31]657 %sub = sub i24 %y, 1658 %mul = mul i24 %x, %sub659 ret i24 %mul660}661 662define i25 @v_mul_add_1_i25_zext(i25 zeroext %x, i25 zeroext %y) {663; GFX67-LABEL: v_mul_add_1_i25_zext:664; GFX67: ; %bb.0:665; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)666; GFX67-NEXT: v_mul_lo_u32 v1, v0, v1667; GFX67-NEXT: v_add_i32_e32 v0, vcc, v1, v0668; GFX67-NEXT: s_setpc_b64 s[30:31]669;670; GFX8-LABEL: v_mul_add_1_i25_zext:671; GFX8: ; %bb.0:672; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)673; GFX8-NEXT: v_mul_lo_u32 v1, v0, v1674; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0675; GFX8-NEXT: s_setpc_b64 s[30:31]676;677; GFX9-LABEL: v_mul_add_1_i25_zext:678; GFX9: ; %bb.0:679; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)680; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[0:1]681; GFX9-NEXT: s_setpc_b64 s[30:31]682;683; GFX10-LABEL: v_mul_add_1_i25_zext:684; GFX10: ; %bb.0:685; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)686; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[0:1]687; GFX10-NEXT: s_setpc_b64 s[30:31]688;689; GFX1250-LABEL: v_mul_add_1_i25_zext:690; GFX1250: ; %bb.0:691; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0692; GFX1250-NEXT: s_wait_kmcnt 0x0693; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v0694; GFX1250-NEXT: s_set_pc_i64 s[30:31]695 %add = add i25 %y, 1696 %mul = mul i25 %x, %add697 ret i25 %mul698}699 700define i25 @v_mul_sub_1_i25_zext(i25 zeroext %x, i25 zeroext %y) {701; GFX67-LABEL: v_mul_sub_1_i25_zext:702; GFX67: ; %bb.0:703; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)704; GFX67-NEXT: v_add_i32_e32 v1, vcc, 0x1ffffff, v1705; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1706; GFX67-NEXT: s_setpc_b64 s[30:31]707;708; GFX8-LABEL: v_mul_sub_1_i25_zext:709; GFX8: ; %bb.0:710; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)711; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x1ffffff, v1712; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1713; GFX8-NEXT: s_setpc_b64 s[30:31]714;715; GFX9-LABEL: v_mul_sub_1_i25_zext:716; GFX9: ; %bb.0:717; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)718; GFX9-NEXT: v_add_u32_e32 v1, 0x1ffffff, v1719; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1720; GFX9-NEXT: s_setpc_b64 s[30:31]721;722; GFX10-LABEL: v_mul_sub_1_i25_zext:723; GFX10: ; %bb.0:724; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)725; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x1ffffff, v1726; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1727; GFX10-NEXT: s_setpc_b64 s[30:31]728;729; GFX1250-LABEL: v_mul_sub_1_i25_zext:730; GFX1250: ; %bb.0:731; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0732; GFX1250-NEXT: s_wait_kmcnt 0x0733; GFX1250-NEXT: v_add_nc_u32_e32 v1, 0x1ffffff, v1734; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)735; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1736; GFX1250-NEXT: s_set_pc_i64 s[30:31]737 %sub = sub i25 %y, 1738 %mul = mul i25 %x, %sub739 ret i25 %mul740}741 742define i25 @v_mul_add_1_i25_sext(i25 signext %x, i25 signext %y) {743; GFX67-LABEL: v_mul_add_1_i25_sext:744; GFX67: ; %bb.0:745; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)746; GFX67-NEXT: v_mul_lo_u32 v1, v0, v1747; GFX67-NEXT: v_add_i32_e32 v0, vcc, v1, v0748; GFX67-NEXT: s_setpc_b64 s[30:31]749;750; GFX8-LABEL: v_mul_add_1_i25_sext:751; GFX8: ; %bb.0:752; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)753; GFX8-NEXT: v_mul_lo_u32 v1, v0, v1754; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0755; GFX8-NEXT: s_setpc_b64 s[30:31]756;757; GFX9-LABEL: v_mul_add_1_i25_sext:758; GFX9: ; %bb.0:759; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)760; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[0:1]761; GFX9-NEXT: s_setpc_b64 s[30:31]762;763; GFX10-LABEL: v_mul_add_1_i25_sext:764; GFX10: ; %bb.0:765; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)766; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[0:1]767; GFX10-NEXT: s_setpc_b64 s[30:31]768;769; GFX1250-LABEL: v_mul_add_1_i25_sext:770; GFX1250: ; %bb.0:771; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0772; GFX1250-NEXT: s_wait_kmcnt 0x0773; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v0774; GFX1250-NEXT: s_set_pc_i64 s[30:31]775 %add = add i25 %y, 1776 %mul = mul i25 %x, %add777 ret i25 %mul778}779 780define i25 @v_mul_sub_1_i25_sext(i25 signext %x, i25 signext %y) {781; GFX67-LABEL: v_mul_sub_1_i25_sext:782; GFX67: ; %bb.0:783; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)784; GFX67-NEXT: v_add_i32_e32 v1, vcc, 0x1ffffff, v1785; GFX67-NEXT: v_mul_lo_u32 v0, v0, v1786; GFX67-NEXT: s_setpc_b64 s[30:31]787;788; GFX8-LABEL: v_mul_sub_1_i25_sext:789; GFX8: ; %bb.0:790; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)791; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x1ffffff, v1792; GFX8-NEXT: v_mul_lo_u32 v0, v0, v1793; GFX8-NEXT: s_setpc_b64 s[30:31]794;795; GFX9-LABEL: v_mul_sub_1_i25_sext:796; GFX9: ; %bb.0:797; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)798; GFX9-NEXT: v_add_u32_e32 v1, 0x1ffffff, v1799; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1800; GFX9-NEXT: s_setpc_b64 s[30:31]801;802; GFX10-LABEL: v_mul_sub_1_i25_sext:803; GFX10: ; %bb.0:804; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)805; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x1ffffff, v1806; GFX10-NEXT: v_mul_lo_u32 v0, v0, v1807; GFX10-NEXT: s_setpc_b64 s[30:31]808;809; GFX1250-LABEL: v_mul_sub_1_i25_sext:810; GFX1250: ; %bb.0:811; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0812; GFX1250-NEXT: s_wait_kmcnt 0x0813; GFX1250-NEXT: v_add_nc_u32_e32 v1, 0x1ffffff, v1814; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)815; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v1816; GFX1250-NEXT: s_set_pc_i64 s[30:31]817 %sub = sub i25 %y, 1818 %mul = mul i25 %x, %sub819 ret i25 %mul820}821 822define i16 @v_mul_add_1_i16(i16 %x, i16 %y) {823; GFX67-LABEL: v_mul_add_1_i16:824; GFX67: ; %bb.0:825; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)826; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v1827; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v0828; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v1829; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1830; GFX67-NEXT: s_setpc_b64 s[30:31]831;832; GFX8-LABEL: v_mul_add_1_i16:833; GFX8: ; %bb.0:834; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)835; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0836; GFX8-NEXT: s_setpc_b64 s[30:31]837;838; GFX9-LABEL: v_mul_add_1_i16:839; GFX9: ; %bb.0:840; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)841; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v0842; GFX9-NEXT: s_setpc_b64 s[30:31]843;844; GFX10-LABEL: v_mul_add_1_i16:845; GFX10: ; %bb.0:846; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)847; GFX10-NEXT: v_mad_u16 v0, v0, v1, v0848; GFX10-NEXT: s_setpc_b64 s[30:31]849;850; GFX1250-LABEL: v_mul_add_1_i16:851; GFX1250: ; %bb.0:852; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0853; GFX1250-NEXT: s_wait_kmcnt 0x0854; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v0855; GFX1250-NEXT: s_set_pc_i64 s[30:31]856 %add = add i16 %y, 1857 %mul = mul i16 %x, %add858 ret i16 %mul859}860 861define i32 @v_mul_add_1_i16_zext_result(i16 %x, i16 %y) {862; GFX67-LABEL: v_mul_add_1_i16_zext_result:863; GFX67: ; %bb.0:864; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)865; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v1866; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v0867; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v1868; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1869; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v0870; GFX67-NEXT: s_setpc_b64 s[30:31]871;872; GFX8-LABEL: v_mul_add_1_i16_zext_result:873; GFX8: ; %bb.0:874; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)875; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0876; GFX8-NEXT: s_setpc_b64 s[30:31]877;878; GFX9-LABEL: v_mul_add_1_i16_zext_result:879; GFX9: ; %bb.0:880; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)881; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v0882; GFX9-NEXT: s_setpc_b64 s[30:31]883;884; GFX10-LABEL: v_mul_add_1_i16_zext_result:885; GFX10: ; %bb.0:886; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)887; GFX10-NEXT: v_mad_u16 v0, v0, v1, v0888; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0889; GFX10-NEXT: s_setpc_b64 s[30:31]890;891; GFX1250-LABEL: v_mul_add_1_i16_zext_result:892; GFX1250: ; %bb.0:893; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0894; GFX1250-NEXT: s_wait_kmcnt 0x0895; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v0896; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)897; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0898; GFX1250-NEXT: s_set_pc_i64 s[30:31]899 %add = add i16 %y, 1900 %mul = mul i16 %x, %add901 %zext = zext i16 %mul to i32902 ret i32 %zext903}904 905define i16 @v_mul_add_1_i16_commute(i16 %x, i16 %y) {906; GFX67-LABEL: v_mul_add_1_i16_commute:907; GFX67: ; %bb.0:908; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)909; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v1910; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v1911; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v0912; GFX67-NEXT: v_mul_u32_u24_e32 v0, v1, v0913; GFX67-NEXT: s_setpc_b64 s[30:31]914;915; GFX8-LABEL: v_mul_add_1_i16_commute:916; GFX8: ; %bb.0:917; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)918; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0919; GFX8-NEXT: s_setpc_b64 s[30:31]920;921; GFX9-LABEL: v_mul_add_1_i16_commute:922; GFX9: ; %bb.0:923; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)924; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v0925; GFX9-NEXT: s_setpc_b64 s[30:31]926;927; GFX10-LABEL: v_mul_add_1_i16_commute:928; GFX10: ; %bb.0:929; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)930; GFX10-NEXT: v_mad_u16 v0, v0, v1, v0931; GFX10-NEXT: s_setpc_b64 s[30:31]932;933; GFX1250-LABEL: v_mul_add_1_i16_commute:934; GFX1250: ; %bb.0:935; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0936; GFX1250-NEXT: s_wait_kmcnt 0x0937; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v0938; GFX1250-NEXT: s_set_pc_i64 s[30:31]939 %add = add i16 %y, 1940 %mul = mul i16 %add, %x941 ret i16 %mul942}943 944define i16 @v_mul_add_x_i16(i16 %x, i16 %y) {945; GFX67-LABEL: v_mul_add_x_i16:946; GFX67: ; %bb.0:947; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)948; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v0949; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v1950; GFX67-NEXT: v_mad_u32_u24 v0, v2, v1, v0951; GFX67-NEXT: s_setpc_b64 s[30:31]952;953; GFX8-LABEL: v_mul_add_x_i16:954; GFX8: ; %bb.0:955; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)956; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0957; GFX8-NEXT: s_setpc_b64 s[30:31]958;959; GFX9-LABEL: v_mul_add_x_i16:960; GFX9: ; %bb.0:961; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)962; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v0963; GFX9-NEXT: s_setpc_b64 s[30:31]964;965; GFX10-LABEL: v_mul_add_x_i16:966; GFX10: ; %bb.0:967; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)968; GFX10-NEXT: v_mad_u16 v0, v0, v1, v0969; GFX10-NEXT: s_setpc_b64 s[30:31]970;971; GFX1250-LABEL: v_mul_add_x_i16:972; GFX1250: ; %bb.0:973; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0974; GFX1250-NEXT: s_wait_kmcnt 0x0975; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v0976; GFX1250-NEXT: s_set_pc_i64 s[30:31]977 %mul = mul i16 %x, %y978 %add = add i16 %x, %mul979 ret i16 %add980}981 982define i16 @v_mul_sub_1_i16(i16 %x, i16 %y) {983; GFX67-LABEL: v_mul_sub_1_i16:984; GFX67: ; %bb.0:985; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)986; GFX67-NEXT: v_add_i32_e32 v1, vcc, -1, v1987; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v0988; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v1989; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v1990; GFX67-NEXT: s_setpc_b64 s[30:31]991;992; GFX8-LABEL: v_mul_sub_1_i16:993; GFX8: ; %bb.0:994; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)995; GFX8-NEXT: v_add_u16_e32 v1, -1, v1996; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v1997; GFX8-NEXT: s_setpc_b64 s[30:31]998;999; GFX9-LABEL: v_mul_sub_1_i16:1000; GFX9: ; %bb.0:1001; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1002; GFX9-NEXT: v_add_u16_e32 v1, -1, v11003; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v11004; GFX9-NEXT: s_setpc_b64 s[30:31]1005;1006; GFX10-LABEL: v_mul_sub_1_i16:1007; GFX10: ; %bb.0:1008; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1009; GFX10-NEXT: v_add_nc_u16 v1, v1, -11010; GFX10-NEXT: v_mul_lo_u16 v0, v0, v11011; GFX10-NEXT: s_setpc_b64 s[30:31]1012;1013; GFX1250-LABEL: v_mul_sub_1_i16:1014; GFX1250: ; %bb.0:1015; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01016; GFX1250-NEXT: s_wait_kmcnt 0x01017; GFX1250-NEXT: v_add_nc_u16 v1, v1, -11018; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1019; GFX1250-NEXT: v_mul_lo_u16 v0, v0, v11020; GFX1250-NEXT: s_set_pc_i64 s[30:31]1021 %sub = sub i16 %y, 11022 %mul = mul i16 %x, %sub1023 ret i16 %mul1024}1025 1026define i16 @v_mul_sub_1_i16_commute(i16 %x, i16 %y) {1027; GFX67-LABEL: v_mul_sub_1_i16_commute:1028; GFX67: ; %bb.0:1029; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1030; GFX67-NEXT: v_add_i32_e32 v1, vcc, -1, v11031; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v11032; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v01033; GFX67-NEXT: v_mul_u32_u24_e32 v0, v1, v01034; GFX67-NEXT: s_setpc_b64 s[30:31]1035;1036; GFX8-LABEL: v_mul_sub_1_i16_commute:1037; GFX8: ; %bb.0:1038; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1039; GFX8-NEXT: v_add_u16_e32 v1, -1, v11040; GFX8-NEXT: v_mul_lo_u16_e32 v0, v1, v01041; GFX8-NEXT: s_setpc_b64 s[30:31]1042;1043; GFX9-LABEL: v_mul_sub_1_i16_commute:1044; GFX9: ; %bb.0:1045; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1046; GFX9-NEXT: v_add_u16_e32 v1, -1, v11047; GFX9-NEXT: v_mul_lo_u16_e32 v0, v1, v01048; GFX9-NEXT: s_setpc_b64 s[30:31]1049;1050; GFX10-LABEL: v_mul_sub_1_i16_commute:1051; GFX10: ; %bb.0:1052; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1053; GFX10-NEXT: v_add_nc_u16 v1, v1, -11054; GFX10-NEXT: v_mul_lo_u16 v0, v1, v01055; GFX10-NEXT: s_setpc_b64 s[30:31]1056;1057; GFX1250-LABEL: v_mul_sub_1_i16_commute:1058; GFX1250: ; %bb.0:1059; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01060; GFX1250-NEXT: s_wait_kmcnt 0x01061; GFX1250-NEXT: v_add_nc_u16 v1, v1, -11062; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1063; GFX1250-NEXT: v_mul_lo_u16 v0, v1, v01064; GFX1250-NEXT: s_set_pc_i64 s[30:31]1065 %sub = sub i16 %y, 11066 %mul = mul i16 %sub, %x1067 ret i16 %mul1068}1069 1070define i16 @v_mul_sub_x_i16(i16 %x, i16 %y) {1071; GFX67-LABEL: v_mul_sub_x_i16:1072; GFX67: ; %bb.0:1073; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1074; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v01075; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v11076; GFX67-NEXT: v_mul_u32_u24_e32 v1, v2, v11077; GFX67-NEXT: v_sub_i32_e32 v0, vcc, v1, v01078; GFX67-NEXT: s_setpc_b64 s[30:31]1079;1080; GFX8-LABEL: v_mul_sub_x_i16:1081; GFX8: ; %bb.0:1082; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1083; GFX8-NEXT: v_mul_lo_u16_e32 v1, v0, v11084; GFX8-NEXT: v_sub_u16_e32 v0, v1, v01085; GFX8-NEXT: s_setpc_b64 s[30:31]1086;1087; GFX9-LABEL: v_mul_sub_x_i16:1088; GFX9: ; %bb.0:1089; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1090; GFX9-NEXT: v_mul_lo_u16_e32 v1, v0, v11091; GFX9-NEXT: v_sub_u16_e32 v0, v1, v01092; GFX9-NEXT: s_setpc_b64 s[30:31]1093;1094; GFX10-LABEL: v_mul_sub_x_i16:1095; GFX10: ; %bb.0:1096; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1097; GFX10-NEXT: v_mul_lo_u16 v1, v0, v11098; GFX10-NEXT: v_sub_nc_u16 v0, v1, v01099; GFX10-NEXT: s_setpc_b64 s[30:31]1100;1101; GFX1250-LABEL: v_mul_sub_x_i16:1102; GFX1250: ; %bb.0:1103; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01104; GFX1250-NEXT: s_wait_kmcnt 0x01105; GFX1250-NEXT: v_mul_lo_u16 v1, v0, v11106; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1107; GFX1250-NEXT: v_sub_nc_u16 v0, v1, v01108; GFX1250-NEXT: s_set_pc_i64 s[30:31]1109 %mul = mul i16 %x, %y1110 %sub = sub i16 %mul, %x1111 ret i16 %sub1112}1113 1114define i16 @v_mul_add_2_i16(i16 %x, i16 %y) {1115; GFX67-LABEL: v_mul_add_2_i16:1116; GFX67: ; %bb.0:1117; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1118; GFX67-NEXT: v_add_i32_e32 v1, vcc, 2, v11119; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v01120; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v11121; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v11122; GFX67-NEXT: s_setpc_b64 s[30:31]1123;1124; GFX8-LABEL: v_mul_add_2_i16:1125; GFX8: ; %bb.0:1126; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1127; GFX8-NEXT: v_add_u16_e32 v1, 2, v11128; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v11129; GFX8-NEXT: s_setpc_b64 s[30:31]1130;1131; GFX9-LABEL: v_mul_add_2_i16:1132; GFX9: ; %bb.0:1133; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1134; GFX9-NEXT: v_add_u16_e32 v1, 2, v11135; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v11136; GFX9-NEXT: s_setpc_b64 s[30:31]1137;1138; GFX10-LABEL: v_mul_add_2_i16:1139; GFX10: ; %bb.0:1140; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1141; GFX10-NEXT: v_add_nc_u16 v1, v1, 21142; GFX10-NEXT: v_mul_lo_u16 v0, v0, v11143; GFX10-NEXT: s_setpc_b64 s[30:31]1144;1145; GFX1250-LABEL: v_mul_add_2_i16:1146; GFX1250: ; %bb.0:1147; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01148; GFX1250-NEXT: s_wait_kmcnt 0x01149; GFX1250-NEXT: v_add_nc_u16 v1, v1, 21150; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1151; GFX1250-NEXT: v_mul_lo_u16 v0, v0, v11152; GFX1250-NEXT: s_set_pc_i64 s[30:31]1153 %add = add i16 %y, 21154 %mul = mul i16 %x, %add1155 ret i16 %mul1156}1157 1158define i16 @v_mul_sub_2_i16(i16 %x, i16 %y) {1159; GFX67-LABEL: v_mul_sub_2_i16:1160; GFX67: ; %bb.0:1161; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1162; GFX67-NEXT: v_add_i32_e32 v1, vcc, -2, v11163; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v01164; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v11165; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v11166; GFX67-NEXT: s_setpc_b64 s[30:31]1167;1168; GFX8-LABEL: v_mul_sub_2_i16:1169; GFX8: ; %bb.0:1170; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1171; GFX8-NEXT: v_add_u16_e32 v1, -2, v11172; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v11173; GFX8-NEXT: s_setpc_b64 s[30:31]1174;1175; GFX9-LABEL: v_mul_sub_2_i16:1176; GFX9: ; %bb.0:1177; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1178; GFX9-NEXT: v_add_u16_e32 v1, -2, v11179; GFX9-NEXT: v_mul_lo_u16_e32 v0, v0, v11180; GFX9-NEXT: s_setpc_b64 s[30:31]1181;1182; GFX10-LABEL: v_mul_sub_2_i16:1183; GFX10: ; %bb.0:1184; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1185; GFX10-NEXT: v_add_nc_u16 v1, v1, -21186; GFX10-NEXT: v_mul_lo_u16 v0, v0, v11187; GFX10-NEXT: s_setpc_b64 s[30:31]1188;1189; GFX1250-LABEL: v_mul_sub_2_i16:1190; GFX1250: ; %bb.0:1191; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01192; GFX1250-NEXT: s_wait_kmcnt 0x01193; GFX1250-NEXT: v_add_nc_u16 v1, v1, -21194; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1195; GFX1250-NEXT: v_mul_lo_u16 v0, v0, v11196; GFX1250-NEXT: s_set_pc_i64 s[30:31]1197 %sub = sub i16 %y, 21198 %mul = mul i16 %x, %sub1199 ret i16 %mul1200}1201 1202define i64 @v_mul_add_1_i64(i64 %x, i64 %y) {1203; GFX6-LABEL: v_mul_add_1_i64:1204; GFX6: ; %bb.0:1205; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1206; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31207; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21208; GFX6-NEXT: v_mul_lo_u32 v5, v1, v21209; GFX6-NEXT: v_mul_lo_u32 v2, v0, v21210; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v31211; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v51212; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v01213; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc1214; GFX6-NEXT: s_setpc_b64 s[30:31]1215;1216; GFX7-LABEL: v_mul_add_1_i64:1217; GFX7: ; %bb.0:1218; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1219; GFX7-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1220; GFX7-NEXT: v_mul_lo_u32 v1, v1, v21221; GFX7-NEXT: v_mul_lo_u32 v0, v0, v31222; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v51223; GFX7-NEXT: v_add_i32_e32 v1, vcc, v0, v11224; GFX7-NEXT: v_mov_b32_e32 v0, v41225; GFX7-NEXT: s_setpc_b64 s[30:31]1226;1227; GFX8-LABEL: v_mul_add_1_i64:1228; GFX8: ; %bb.0:1229; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1230; GFX8-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1231; GFX8-NEXT: v_mul_lo_u32 v1, v1, v21232; GFX8-NEXT: v_mul_lo_u32 v0, v0, v31233; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v51234; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v11235; GFX8-NEXT: v_mov_b32_e32 v0, v41236; GFX8-NEXT: s_setpc_b64 s[30:31]1237;1238; GFX9-LABEL: v_mul_add_1_i64:1239; GFX9: ; %bb.0:1240; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1241; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1242; GFX9-NEXT: v_mul_lo_u32 v0, v0, v31243; GFX9-NEXT: v_mul_lo_u32 v1, v1, v21244; GFX9-NEXT: v_add3_u32 v1, v1, v5, v01245; GFX9-NEXT: v_mov_b32_e32 v0, v41246; GFX9-NEXT: s_setpc_b64 s[30:31]1247;1248; GFX10-LABEL: v_mul_add_1_i64:1249; GFX10: ; %bb.0:1250; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1251; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, v[0:1]1252; GFX10-NEXT: v_mul_lo_u32 v0, v0, v31253; GFX10-NEXT: v_mul_lo_u32 v1, v1, v21254; GFX10-NEXT: v_add3_u32 v1, v1, v5, v01255; GFX10-NEXT: v_mov_b32_e32 v0, v41256; GFX10-NEXT: s_setpc_b64 s[30:31]1257;1258; GFX1250-LABEL: v_mul_add_1_i64:1259; GFX1250: ; %bb.0:1260; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01261; GFX1250-NEXT: s_wait_kmcnt 0x01262; GFX1250-NEXT: v_mad_nc_u64_u32 v[4:5], v0, v2, v[0:1]1263; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1264; GFX1250-NEXT: v_mad_u32 v1, v1, v2, v51265; GFX1250-NEXT: v_mad_u32 v1, v0, v3, v11266; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3)1267; GFX1250-NEXT: v_mov_b32_e32 v0, v41268; GFX1250-NEXT: s_set_pc_i64 s[30:31]1269 %add = add i64 %y, 11270 %mul = mul i64 %x, %add1271 ret i64 %mul1272}1273 1274define i64 @v_mul_add_1_i64_commute(i64 %x, i64 %y) {1275; GFX6-LABEL: v_mul_add_1_i64_commute:1276; GFX6: ; %bb.0:1277; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1278; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31279; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21280; GFX6-NEXT: v_mul_lo_u32 v5, v1, v21281; GFX6-NEXT: v_mul_lo_u32 v2, v0, v21282; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v31283; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v51284; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v01285; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc1286; GFX6-NEXT: s_setpc_b64 s[30:31]1287;1288; GFX7-LABEL: v_mul_add_1_i64_commute:1289; GFX7: ; %bb.0:1290; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1291; GFX7-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1292; GFX7-NEXT: v_mul_lo_u32 v1, v1, v21293; GFX7-NEXT: v_mul_lo_u32 v0, v0, v31294; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v51295; GFX7-NEXT: v_add_i32_e32 v1, vcc, v0, v11296; GFX7-NEXT: v_mov_b32_e32 v0, v41297; GFX7-NEXT: s_setpc_b64 s[30:31]1298;1299; GFX8-LABEL: v_mul_add_1_i64_commute:1300; GFX8: ; %bb.0:1301; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1302; GFX8-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1303; GFX8-NEXT: v_mul_lo_u32 v1, v1, v21304; GFX8-NEXT: v_mul_lo_u32 v0, v0, v31305; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v51306; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v11307; GFX8-NEXT: v_mov_b32_e32 v0, v41308; GFX8-NEXT: s_setpc_b64 s[30:31]1309;1310; GFX9-LABEL: v_mul_add_1_i64_commute:1311; GFX9: ; %bb.0:1312; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1313; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1314; GFX9-NEXT: v_mul_lo_u32 v0, v0, v31315; GFX9-NEXT: v_mul_lo_u32 v1, v1, v21316; GFX9-NEXT: v_add3_u32 v1, v1, v5, v01317; GFX9-NEXT: v_mov_b32_e32 v0, v41318; GFX9-NEXT: s_setpc_b64 s[30:31]1319;1320; GFX10-LABEL: v_mul_add_1_i64_commute:1321; GFX10: ; %bb.0:1322; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1323; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, v[0:1]1324; GFX10-NEXT: v_mul_lo_u32 v0, v0, v31325; GFX10-NEXT: v_mul_lo_u32 v1, v1, v21326; GFX10-NEXT: v_add3_u32 v1, v1, v5, v01327; GFX10-NEXT: v_mov_b32_e32 v0, v41328; GFX10-NEXT: s_setpc_b64 s[30:31]1329;1330; GFX1250-LABEL: v_mul_add_1_i64_commute:1331; GFX1250: ; %bb.0:1332; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01333; GFX1250-NEXT: s_wait_kmcnt 0x01334; GFX1250-NEXT: v_mad_nc_u64_u32 v[4:5], v0, v2, v[0:1]1335; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1336; GFX1250-NEXT: v_mad_u32 v1, v1, v2, v51337; GFX1250-NEXT: v_mad_u32 v1, v0, v3, v11338; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3)1339; GFX1250-NEXT: v_mov_b32_e32 v0, v41340; GFX1250-NEXT: s_set_pc_i64 s[30:31]1341 %add = add i64 %y, 11342 %mul = mul i64 %add, %x1343 ret i64 %mul1344}1345 1346define i64 @v_mul_add_x_i64(i64 %x, i64 %y) {1347; GFX6-LABEL: v_mul_add_x_i64:1348; GFX6: ; %bb.0:1349; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1350; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31351; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21352; GFX6-NEXT: v_mul_lo_u32 v5, v1, v21353; GFX6-NEXT: v_mul_lo_u32 v2, v0, v21354; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v31355; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v51356; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v21357; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc1358; GFX6-NEXT: s_setpc_b64 s[30:31]1359;1360; GFX7-LABEL: v_mul_add_x_i64:1361; GFX7: ; %bb.0:1362; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1363; GFX7-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1364; GFX7-NEXT: v_mul_lo_u32 v1, v1, v21365; GFX7-NEXT: v_mul_lo_u32 v0, v0, v31366; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v51367; GFX7-NEXT: v_add_i32_e32 v1, vcc, v0, v11368; GFX7-NEXT: v_mov_b32_e32 v0, v41369; GFX7-NEXT: s_setpc_b64 s[30:31]1370;1371; GFX8-LABEL: v_mul_add_x_i64:1372; GFX8: ; %bb.0:1373; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1374; GFX8-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1375; GFX8-NEXT: v_mul_lo_u32 v1, v1, v21376; GFX8-NEXT: v_mul_lo_u32 v0, v0, v31377; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v51378; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v11379; GFX8-NEXT: v_mov_b32_e32 v0, v41380; GFX8-NEXT: s_setpc_b64 s[30:31]1381;1382; GFX9-LABEL: v_mul_add_x_i64:1383; GFX9: ; %bb.0:1384; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1385; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]1386; GFX9-NEXT: v_mul_lo_u32 v0, v0, v31387; GFX9-NEXT: v_mul_lo_u32 v1, v1, v21388; GFX9-NEXT: v_add3_u32 v1, v1, v5, v01389; GFX9-NEXT: v_mov_b32_e32 v0, v41390; GFX9-NEXT: s_setpc_b64 s[30:31]1391;1392; GFX10-LABEL: v_mul_add_x_i64:1393; GFX10: ; %bb.0:1394; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1395; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, v[0:1]1396; GFX10-NEXT: v_mul_lo_u32 v0, v0, v31397; GFX10-NEXT: v_mul_lo_u32 v1, v1, v21398; GFX10-NEXT: v_add3_u32 v1, v1, v5, v01399; GFX10-NEXT: v_mov_b32_e32 v0, v41400; GFX10-NEXT: s_setpc_b64 s[30:31]1401;1402; GFX1250-LABEL: v_mul_add_x_i64:1403; GFX1250: ; %bb.0:1404; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01405; GFX1250-NEXT: s_wait_kmcnt 0x01406; GFX1250-NEXT: v_mad_nc_u64_u32 v[4:5], v0, v2, v[0:1]1407; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1408; GFX1250-NEXT: v_mad_u32 v1, v1, v2, v51409; GFX1250-NEXT: v_mad_u32 v1, v0, v3, v11410; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3)1411; GFX1250-NEXT: v_mov_b32_e32 v0, v41412; GFX1250-NEXT: s_set_pc_i64 s[30:31]1413 %mul = mul i64 %x, %y1414 %add = add i64 %x, %mul1415 ret i64 %add1416}1417 1418define i64 @v_mul_sub_1_i64(i64 %x, i64 %y) {1419; GFX6-LABEL: v_mul_sub_1_i64:1420; GFX6: ; %bb.0:1421; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1422; GFX6-NEXT: v_add_i32_e32 v2, vcc, -1, v21423; GFX6-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc1424; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31425; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21426; GFX6-NEXT: v_mul_lo_u32 v1, v1, v21427; GFX6-NEXT: v_mul_lo_u32 v0, v0, v21428; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v31429; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v11430; GFX6-NEXT: s_setpc_b64 s[30:31]1431;1432; GFX7-LABEL: v_mul_sub_1_i64:1433; GFX7: ; %bb.0:1434; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1435; GFX7-NEXT: v_add_i32_e32 v2, vcc, -1, v21436; GFX7-NEXT: v_mov_b32_e32 v4, v11437; GFX7-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc1438; GFX7-NEXT: v_mul_lo_u32 v3, v0, v11439; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01440; GFX7-NEXT: v_mul_lo_u32 v2, v4, v21441; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v31442; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v21443; GFX7-NEXT: s_setpc_b64 s[30:31]1444;1445; GFX8-LABEL: v_mul_sub_1_i64:1446; GFX8: ; %bb.0:1447; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1448; GFX8-NEXT: v_add_u32_e32 v2, vcc, -1, v21449; GFX8-NEXT: v_mov_b32_e32 v4, v11450; GFX8-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc1451; GFX8-NEXT: v_mul_lo_u32 v3, v0, v11452; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01453; GFX8-NEXT: v_mul_lo_u32 v2, v4, v21454; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v31455; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v21456; GFX8-NEXT: s_setpc_b64 s[30:31]1457;1458; GFX9-LABEL: v_mul_sub_1_i64:1459; GFX9: ; %bb.0:1460; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1461; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, -1, v21462; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc1463; GFX9-NEXT: v_mul_lo_u32 v4, v1, v21464; GFX9-NEXT: v_mul_lo_u32 v3, v0, v31465; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01466; GFX9-NEXT: v_add3_u32 v1, v1, v3, v41467; GFX9-NEXT: s_setpc_b64 s[30:31]1468;1469; GFX10-LABEL: v_mul_sub_1_i64:1470; GFX10: ; %bb.0:1471; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1472; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, -11473; GFX10-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo1474; GFX10-NEXT: v_mul_lo_u32 v4, v1, v21475; GFX10-NEXT: v_mul_lo_u32 v3, v0, v31476; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v2, 01477; GFX10-NEXT: v_add3_u32 v1, v1, v3, v41478; GFX10-NEXT: s_setpc_b64 s[30:31]1479;1480; GFX1250-LABEL: v_mul_sub_1_i64:1481; GFX1250: ; %bb.0:1482; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01483; GFX1250-NEXT: s_wait_kmcnt 0x01484; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], -1, v[2:3]1485; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1486; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[0:1], v[2:3]1487; GFX1250-NEXT: s_set_pc_i64 s[30:31]1488 %sub = sub i64 %y, 11489 %mul = mul i64 %x, %sub1490 ret i64 %mul1491}1492 1493define i64 @v_mul_sub_1_i64_commute(i64 %x, i64 %y) {1494; GFX6-LABEL: v_mul_sub_1_i64_commute:1495; GFX6: ; %bb.0:1496; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1497; GFX6-NEXT: v_add_i32_e32 v2, vcc, -1, v21498; GFX6-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc1499; GFX6-NEXT: v_mul_lo_u32 v1, v2, v11500; GFX6-NEXT: v_mul_hi_u32 v4, v2, v01501; GFX6-NEXT: v_mul_lo_u32 v3, v3, v01502; GFX6-NEXT: v_mul_lo_u32 v0, v2, v01503; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v11504; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v31505; GFX6-NEXT: s_setpc_b64 s[30:31]1506;1507; GFX7-LABEL: v_mul_sub_1_i64_commute:1508; GFX7: ; %bb.0:1509; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1510; GFX7-NEXT: v_mov_b32_e32 v4, v01511; GFX7-NEXT: v_add_i32_e32 v0, vcc, -1, v21512; GFX7-NEXT: v_addc_u32_e32 v2, vcc, -1, v3, vcc1513; GFX7-NEXT: v_mul_lo_u32 v3, v0, v11514; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v4, 01515; GFX7-NEXT: v_mul_lo_u32 v2, v2, v41516; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v31517; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v21518; GFX7-NEXT: s_setpc_b64 s[30:31]1519;1520; GFX8-LABEL: v_mul_sub_1_i64_commute:1521; GFX8: ; %bb.0:1522; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1523; GFX8-NEXT: v_mov_b32_e32 v4, v01524; GFX8-NEXT: v_add_u32_e32 v0, vcc, -1, v21525; GFX8-NEXT: v_addc_u32_e32 v2, vcc, -1, v3, vcc1526; GFX8-NEXT: v_mul_lo_u32 v3, v0, v11527; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v4, 01528; GFX8-NEXT: v_mul_lo_u32 v2, v2, v41529; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v31530; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v21531; GFX8-NEXT: s_setpc_b64 s[30:31]1532;1533; GFX9-LABEL: v_mul_sub_1_i64_commute:1534; GFX9: ; %bb.0:1535; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1536; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, -1, v21537; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc1538; GFX9-NEXT: v_mul_lo_u32 v3, v3, v01539; GFX9-NEXT: v_mul_lo_u32 v4, v2, v11540; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 01541; GFX9-NEXT: v_add3_u32 v1, v1, v4, v31542; GFX9-NEXT: s_setpc_b64 s[30:31]1543;1544; GFX10-LABEL: v_mul_sub_1_i64_commute:1545; GFX10: ; %bb.0:1546; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1547; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, -11548; GFX10-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo1549; GFX10-NEXT: v_mul_lo_u32 v4, v2, v11550; GFX10-NEXT: v_mul_lo_u32 v3, v3, v01551; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v2, v0, 01552; GFX10-NEXT: v_add3_u32 v1, v1, v4, v31553; GFX10-NEXT: s_setpc_b64 s[30:31]1554;1555; GFX1250-LABEL: v_mul_sub_1_i64_commute:1556; GFX1250: ; %bb.0:1557; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01558; GFX1250-NEXT: s_wait_kmcnt 0x01559; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], -1, v[2:3]1560; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1561; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[2:3], v[0:1]1562; GFX1250-NEXT: s_set_pc_i64 s[30:31]1563 %sub = sub i64 %y, 11564 %mul = mul i64 %sub, %x1565 ret i64 %mul1566}1567 1568define i64 @v_mul_sub_x_i64(i64 %x, i64 %y) {1569; GFX6-LABEL: v_mul_sub_x_i64:1570; GFX6: ; %bb.0:1571; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1572; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31573; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21574; GFX6-NEXT: v_mul_lo_u32 v5, v1, v21575; GFX6-NEXT: v_mul_lo_u32 v2, v0, v21576; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v31577; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v51578; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v2, v01579; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc1580; GFX6-NEXT: s_setpc_b64 s[30:31]1581;1582; GFX7-LABEL: v_mul_sub_x_i64:1583; GFX7: ; %bb.0:1584; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1585; GFX7-NEXT: v_mul_lo_u32 v5, v0, v31586; GFX7-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v0, v2, 01587; GFX7-NEXT: v_mul_lo_u32 v2, v1, v21588; GFX7-NEXT: v_add_i32_e32 v4, vcc, v4, v51589; GFX7-NEXT: v_add_i32_e32 v2, vcc, v4, v21590; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v3, v01591; GFX7-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc1592; GFX7-NEXT: s_setpc_b64 s[30:31]1593;1594; GFX8-LABEL: v_mul_sub_x_i64:1595; GFX8: ; %bb.0:1596; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1597; GFX8-NEXT: v_mul_lo_u32 v5, v0, v31598; GFX8-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v0, v2, 01599; GFX8-NEXT: v_mul_lo_u32 v2, v1, v21600; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v51601; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v21602; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v3, v01603; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc1604; GFX8-NEXT: s_setpc_b64 s[30:31]1605;1606; GFX9-LABEL: v_mul_sub_x_i64:1607; GFX9: ; %bb.0:1608; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1609; GFX9-NEXT: v_mul_lo_u32 v4, v1, v21610; GFX9-NEXT: v_mul_lo_u32 v5, v0, v31611; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, v2, 01612; GFX9-NEXT: v_add3_u32 v3, v3, v5, v41613; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v2, v01614; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc1615; GFX9-NEXT: s_setpc_b64 s[30:31]1616;1617; GFX10-LABEL: v_mul_sub_x_i64:1618; GFX10: ; %bb.0:1619; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1620; GFX10-NEXT: v_mul_lo_u32 v4, v1, v21621; GFX10-NEXT: v_mul_lo_u32 v5, v0, v31622; GFX10-NEXT: v_mad_u64_u32 v[2:3], null, v0, v2, 01623; GFX10-NEXT: v_add3_u32 v3, v3, v5, v41624; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v2, v01625; GFX10-NEXT: v_sub_co_ci_u32_e64 v1, null, v3, v1, vcc_lo1626; GFX10-NEXT: s_setpc_b64 s[30:31]1627;1628; GFX1250-LABEL: v_mul_sub_x_i64:1629; GFX1250: ; %bb.0:1630; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01631; GFX1250-NEXT: s_wait_kmcnt 0x01632; GFX1250-NEXT: v_mul_u64_e32 v[2:3], v[0:1], v[2:3]1633; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1634; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[2:3], v[0:1]1635; GFX1250-NEXT: s_set_pc_i64 s[30:31]1636 %mul = mul i64 %x, %y1637 %sub = sub i64 %mul, %x1638 ret i64 %sub1639}1640 1641define i64 @v_mul_add_2_i64(i64 %x, i64 %y) {1642; GFX6-LABEL: v_mul_add_2_i64:1643; GFX6: ; %bb.0:1644; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1645; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v21646; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1647; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31648; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21649; GFX6-NEXT: v_mul_lo_u32 v1, v1, v21650; GFX6-NEXT: v_mul_lo_u32 v0, v0, v21651; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v31652; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v11653; GFX6-NEXT: s_setpc_b64 s[30:31]1654;1655; GFX7-LABEL: v_mul_add_2_i64:1656; GFX7: ; %bb.0:1657; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1658; GFX7-NEXT: v_add_i32_e32 v2, vcc, 2, v21659; GFX7-NEXT: v_mov_b32_e32 v4, v11660; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc1661; GFX7-NEXT: v_mul_lo_u32 v3, v0, v11662; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01663; GFX7-NEXT: v_mul_lo_u32 v2, v4, v21664; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v31665; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v21666; GFX7-NEXT: s_setpc_b64 s[30:31]1667;1668; GFX8-LABEL: v_mul_add_2_i64:1669; GFX8: ; %bb.0:1670; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1671; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v21672; GFX8-NEXT: v_mov_b32_e32 v4, v11673; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc1674; GFX8-NEXT: v_mul_lo_u32 v3, v0, v11675; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01676; GFX8-NEXT: v_mul_lo_u32 v2, v4, v21677; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v31678; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v21679; GFX8-NEXT: s_setpc_b64 s[30:31]1680;1681; GFX9-LABEL: v_mul_add_2_i64:1682; GFX9: ; %bb.0:1683; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1684; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 2, v21685; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc1686; GFX9-NEXT: v_mul_lo_u32 v4, v1, v21687; GFX9-NEXT: v_mul_lo_u32 v3, v0, v31688; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01689; GFX9-NEXT: v_add3_u32 v1, v1, v3, v41690; GFX9-NEXT: s_setpc_b64 s[30:31]1691;1692; GFX10-LABEL: v_mul_add_2_i64:1693; GFX10: ; %bb.0:1694; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1695; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, 21696; GFX10-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo1697; GFX10-NEXT: v_mul_lo_u32 v4, v1, v21698; GFX10-NEXT: v_mul_lo_u32 v3, v0, v31699; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v2, 01700; GFX10-NEXT: v_add3_u32 v1, v1, v3, v41701; GFX10-NEXT: s_setpc_b64 s[30:31]1702;1703; GFX1250-LABEL: v_mul_add_2_i64:1704; GFX1250: ; %bb.0:1705; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01706; GFX1250-NEXT: s_wait_kmcnt 0x01707; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], 2, v[2:3]1708; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1709; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[0:1], v[2:3]1710; GFX1250-NEXT: s_set_pc_i64 s[30:31]1711 %add = add i64 %y, 21712 %mul = mul i64 %x, %add1713 ret i64 %mul1714}1715 1716define i64 @v_mul_sub_2_i64(i64 %x, i64 %y) {1717; GFX6-LABEL: v_mul_sub_2_i64:1718; GFX6: ; %bb.0:1719; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1720; GFX6-NEXT: v_add_i32_e32 v2, vcc, -2, v21721; GFX6-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc1722; GFX6-NEXT: v_mul_lo_u32 v3, v0, v31723; GFX6-NEXT: v_mul_hi_u32 v4, v0, v21724; GFX6-NEXT: v_mul_lo_u32 v1, v1, v21725; GFX6-NEXT: v_mul_lo_u32 v0, v0, v21726; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v31727; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v11728; GFX6-NEXT: s_setpc_b64 s[30:31]1729;1730; GFX7-LABEL: v_mul_sub_2_i64:1731; GFX7: ; %bb.0:1732; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1733; GFX7-NEXT: v_add_i32_e32 v2, vcc, -2, v21734; GFX7-NEXT: v_mov_b32_e32 v4, v11735; GFX7-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc1736; GFX7-NEXT: v_mul_lo_u32 v3, v0, v11737; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01738; GFX7-NEXT: v_mul_lo_u32 v2, v4, v21739; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v31740; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v21741; GFX7-NEXT: s_setpc_b64 s[30:31]1742;1743; GFX8-LABEL: v_mul_sub_2_i64:1744; GFX8: ; %bb.0:1745; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1746; GFX8-NEXT: v_add_u32_e32 v2, vcc, -2, v21747; GFX8-NEXT: v_mov_b32_e32 v4, v11748; GFX8-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc1749; GFX8-NEXT: v_mul_lo_u32 v3, v0, v11750; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01751; GFX8-NEXT: v_mul_lo_u32 v2, v4, v21752; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v31753; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v21754; GFX8-NEXT: s_setpc_b64 s[30:31]1755;1756; GFX9-LABEL: v_mul_sub_2_i64:1757; GFX9: ; %bb.0:1758; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1759; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, -2, v21760; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc1761; GFX9-NEXT: v_mul_lo_u32 v4, v1, v21762; GFX9-NEXT: v_mul_lo_u32 v3, v0, v31763; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, 01764; GFX9-NEXT: v_add3_u32 v1, v1, v3, v41765; GFX9-NEXT: s_setpc_b64 s[30:31]1766;1767; GFX10-LABEL: v_mul_sub_2_i64:1768; GFX10: ; %bb.0:1769; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1770; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v2, -21771; GFX10-NEXT: v_add_co_ci_u32_e64 v3, null, -1, v3, vcc_lo1772; GFX10-NEXT: v_mul_lo_u32 v4, v1, v21773; GFX10-NEXT: v_mul_lo_u32 v3, v0, v31774; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v2, 01775; GFX10-NEXT: v_add3_u32 v1, v1, v3, v41776; GFX10-NEXT: s_setpc_b64 s[30:31]1777;1778; GFX1250-LABEL: v_mul_sub_2_i64:1779; GFX1250: ; %bb.0:1780; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01781; GFX1250-NEXT: s_wait_kmcnt 0x01782; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], -2, v[2:3]1783; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1784; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[0:1], v[2:3]1785; GFX1250-NEXT: s_set_pc_i64 s[30:31]1786 %sub = sub i64 %y, 21787 %mul = mul i64 %x, %sub1788 ret i64 %mul1789}1790 1791define <2 x i32> @v_mul_add_1_i32_multiple(i32 %x, i32 %y, i32 %z) {1792; GFX67-LABEL: v_mul_add_1_i32_multiple:1793; GFX67: ; %bb.0:1794; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1795; GFX67-NEXT: v_mul_lo_u32 v3, v0, v11796; GFX67-NEXT: v_mul_lo_u32 v1, v2, v11797; GFX67-NEXT: v_add_i32_e32 v0, vcc, v3, v01798; GFX67-NEXT: v_add_i32_e32 v1, vcc, v1, v21799; GFX67-NEXT: s_setpc_b64 s[30:31]1800;1801; GFX8-LABEL: v_mul_add_1_i32_multiple:1802; GFX8: ; %bb.0:1803; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1804; GFX8-NEXT: v_mul_lo_u32 v3, v0, v11805; GFX8-NEXT: v_mul_lo_u32 v1, v2, v11806; GFX8-NEXT: v_add_u32_e32 v0, vcc, v3, v01807; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v21808; GFX8-NEXT: s_setpc_b64 s[30:31]1809;1810; GFX900-LABEL: v_mul_add_1_i32_multiple:1811; GFX900: ; %bb.0:1812; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1813; GFX900-NEXT: v_mov_b32_e32 v3, v11814; GFX900-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v3, v[0:1]1815; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, v3, v[2:3]1816; GFX900-NEXT: s_setpc_b64 s[30:31]1817;1818; GFX90A-LABEL: v_mul_add_1_i32_multiple:1819; GFX90A: ; %bb.0:1820; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1821; GFX90A-NEXT: v_mov_b32_e32 v3, v11822; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v3, v[0:1]1823; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v3, v[2:3]1824; GFX90A-NEXT: v_mov_b32_e32 v1, v21825; GFX90A-NEXT: s_setpc_b64 s[30:31]1826;1827; GFX10-LABEL: v_mul_add_1_i32_multiple:1828; GFX10: ; %bb.0:1829; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1830; GFX10-NEXT: v_mov_b32_e32 v3, v11831; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v3, v[0:1]1832; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, v2, v3, v[2:3]1833; GFX10-NEXT: s_setpc_b64 s[30:31]1834;1835; GFX1250-LABEL: v_mul_add_1_i32_multiple:1836; GFX1250: ; %bb.0:1837; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01838; GFX1250-NEXT: s_wait_kmcnt 0x01839; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v01840; GFX1250-NEXT: v_mad_u32 v1, v2, v1, v21841; GFX1250-NEXT: s_set_pc_i64 s[30:31]1842 %add = add i32 %y, 11843 %mul0 = mul i32 %x, %add1844 %mul1 = mul i32 %z, %add1845 %insert.0 = insertelement <2 x i32> poison, i32 %mul0, i32 01846 %insert.1 = insertelement <2 x i32> %insert.0, i32 %mul1, i32 11847 ret <2 x i32> %insert.11848}1849 1850define <2 x i32> @v_mul_add_1_i32_other_use(i32 %x, i32 %y, i32 %z) {1851; GFX67-LABEL: v_mul_add_1_i32_other_use:1852; GFX67: ; %bb.0:1853; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1854; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v11855; GFX67-NEXT: v_mul_lo_u32 v0, v0, v11856; GFX67-NEXT: s_setpc_b64 s[30:31]1857;1858; GFX8-LABEL: v_mul_add_1_i32_other_use:1859; GFX8: ; %bb.0:1860; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1861; GFX8-NEXT: v_add_u32_e32 v1, vcc, 1, v11862; GFX8-NEXT: v_mul_lo_u32 v0, v0, v11863; GFX8-NEXT: s_setpc_b64 s[30:31]1864;1865; GFX9-LABEL: v_mul_add_1_i32_other_use:1866; GFX9: ; %bb.0:1867; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1868; GFX9-NEXT: v_add_u32_e32 v1, 1, v11869; GFX9-NEXT: v_mul_lo_u32 v0, v0, v11870; GFX9-NEXT: s_setpc_b64 s[30:31]1871;1872; GFX10-LABEL: v_mul_add_1_i32_other_use:1873; GFX10: ; %bb.0:1874; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1875; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v11876; GFX10-NEXT: v_mul_lo_u32 v0, v0, v11877; GFX10-NEXT: s_setpc_b64 s[30:31]1878;1879; GFX1250-LABEL: v_mul_add_1_i32_other_use:1880; GFX1250: ; %bb.0:1881; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01882; GFX1250-NEXT: s_wait_kmcnt 0x01883; GFX1250-NEXT: v_add_nc_u32_e32 v1, 1, v11884; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1885; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v11886; GFX1250-NEXT: s_set_pc_i64 s[30:31]1887 %add = add i32 %y, 11888 %mul0 = mul i32 %x, %add1889 %mul1 = mul i32 %z, %add1890 %insert.0 = insertelement <2 x i32> poison, i32 %mul0, i32 01891 %insert.1 = insertelement <2 x i32> %insert.0, i32 %add, i32 11892 ret <2 x i32> %insert.11893}1894 1895define i32 @v_mul_add_1_i32_chain(i32 %arg0, i32 %arg1, i32 %arg2) {1896; GFX67-LABEL: v_mul_add_1_i32_chain:1897; GFX67: ; %bb.0:1898; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1899; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v01900; GFX67-NEXT: v_mul_lo_u32 v1, v2, v11901; GFX67-NEXT: v_add_i32_e32 v2, vcc, v1, v21902; GFX67-NEXT: v_mul_lo_u32 v0, v2, v01903; GFX67-NEXT: v_mul_lo_u32 v1, v0, v11904; GFX67-NEXT: v_add_i32_e32 v0, vcc, v1, v01905; GFX67-NEXT: s_setpc_b64 s[30:31]1906;1907; GFX8-LABEL: v_mul_add_1_i32_chain:1908; GFX8: ; %bb.0:1909; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1910; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v01911; GFX8-NEXT: v_mul_lo_u32 v1, v2, v11912; GFX8-NEXT: v_add_u32_e32 v2, vcc, v1, v21913; GFX8-NEXT: v_mul_lo_u32 v0, v2, v01914; GFX8-NEXT: v_mul_lo_u32 v1, v0, v11915; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v01916; GFX8-NEXT: s_setpc_b64 s[30:31]1917;1918; GFX9-LABEL: v_mul_add_1_i32_chain:1919; GFX9: ; %bb.0:1920; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1921; GFX9-NEXT: v_add_u32_e32 v2, 1, v01922; GFX9-NEXT: v_mul_lo_u32 v1, v2, v11923; GFX9-NEXT: v_add_u32_e32 v2, v1, v21924; GFX9-NEXT: v_mul_lo_u32 v0, v2, v01925; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[0:1]1926; GFX9-NEXT: s_setpc_b64 s[30:31]1927;1928; GFX10-LABEL: v_mul_add_1_i32_chain:1929; GFX10: ; %bb.0:1930; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1931; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v01932; GFX10-NEXT: v_mul_lo_u32 v1, v2, v11933; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v21934; GFX10-NEXT: v_mul_lo_u32 v0, v2, v01935; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[0:1]1936; GFX10-NEXT: s_setpc_b64 s[30:31]1937;1938; GFX1250-LABEL: v_mul_add_1_i32_chain:1939; GFX1250: ; %bb.0:1940; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01941; GFX1250-NEXT: s_wait_kmcnt 0x01942; GFX1250-NEXT: v_add_nc_u32_e32 v2, 1, v01943; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1944; GFX1250-NEXT: v_mul_lo_u32 v1, v2, v11945; GFX1250-NEXT: v_add_nc_u32_e32 v2, v1, v21946; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1947; GFX1250-NEXT: v_mul_lo_u32 v0, v2, v01948; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v01949; GFX1250-NEXT: s_set_pc_i64 s[30:31]1950 %i2 = add i32 %arg0, 11951 %i3 = mul i32 %i2, %arg11952 %i4 = add i32 %i3, %i21953 %i5 = mul i32 %i4, %arg01954 %i6 = add i32 %i3, 11955 %i7 = mul i32 %i5, %i61956 ret i32 %i71957}1958define <2 x i16> @v_mul_add_1_v2i16(<2 x i16> %x, <2 x i16> %y) {1959; GFX67-LABEL: v_mul_add_1_v2i16:1960; GFX67: ; %bb.0:1961; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1962; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v21963; GFX67-NEXT: v_add_i32_e32 v3, vcc, 1, v31964; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v21965; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v31966; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v01967; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v11968; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v21969; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v31970; GFX67-NEXT: s_setpc_b64 s[30:31]1971;1972; GFX8-LABEL: v_mul_add_1_v2i16:1973; GFX8: ; %bb.0:1974; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1975; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v11976; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v01977; GFX8-NEXT: v_mad_u16 v2, v3, v2, v31978; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v21979; GFX8-NEXT: v_mad_u16 v0, v0, v1, v01980; GFX8-NEXT: v_or_b32_e32 v0, v0, v21981; GFX8-NEXT: s_setpc_b64 s[30:31]1982;1983; GFX9-LABEL: v_mul_add_1_v2i16:1984; GFX9: ; %bb.0:1985; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1986; GFX9-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]1987; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v11988; GFX9-NEXT: s_setpc_b64 s[30:31]1989;1990; GFX10-LABEL: v_mul_add_1_v2i16:1991; GFX10: ; %bb.0:1992; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1993; GFX10-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]1994; GFX10-NEXT: v_pk_mul_lo_u16 v0, v0, v11995; GFX10-NEXT: s_setpc_b64 s[30:31]1996;1997; GFX1250-LABEL: v_mul_add_1_v2i16:1998; GFX1250: ; %bb.0:1999; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02000; GFX1250-NEXT: s_wait_kmcnt 0x02001; GFX1250-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]2002; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2003; GFX1250-NEXT: v_pk_mul_lo_u16 v0, v0, v12004; GFX1250-NEXT: s_set_pc_i64 s[30:31]2005 %add = add <2 x i16> %y, <i16 1, i16 1>2006 %mul = mul <2 x i16> %x, %add2007 ret <2 x i16> %mul2008}2009 2010define <2 x i16> @v_mul_add_1_v2i16_commute(<2 x i16> %x, <2 x i16> %y) {2011; GFX67-LABEL: v_mul_add_1_v2i16_commute:2012; GFX67: ; %bb.0:2013; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2014; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v22015; GFX67-NEXT: v_add_i32_e32 v3, vcc, 1, v32016; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22017; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32018; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02019; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12020; GFX67-NEXT: v_mul_u32_u24_e32 v0, v2, v02021; GFX67-NEXT: v_mul_u32_u24_e32 v1, v3, v12022; GFX67-NEXT: s_setpc_b64 s[30:31]2023;2024; GFX8-LABEL: v_mul_add_1_v2i16_commute:2025; GFX8: ; %bb.0:2026; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2027; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v12028; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v02029; GFX8-NEXT: v_mad_u16 v2, v3, v2, v32030; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v22031; GFX8-NEXT: v_mad_u16 v0, v0, v1, v02032; GFX8-NEXT: v_or_b32_e32 v0, v0, v22033; GFX8-NEXT: s_setpc_b64 s[30:31]2034;2035; GFX9-LABEL: v_mul_add_1_v2i16_commute:2036; GFX9: ; %bb.0:2037; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2038; GFX9-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]2039; GFX9-NEXT: v_pk_mul_lo_u16 v0, v1, v02040; GFX9-NEXT: s_setpc_b64 s[30:31]2041;2042; GFX10-LABEL: v_mul_add_1_v2i16_commute:2043; GFX10: ; %bb.0:2044; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2045; GFX10-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]2046; GFX10-NEXT: v_pk_mul_lo_u16 v0, v1, v02047; GFX10-NEXT: s_setpc_b64 s[30:31]2048;2049; GFX1250-LABEL: v_mul_add_1_v2i16_commute:2050; GFX1250: ; %bb.0:2051; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02052; GFX1250-NEXT: s_wait_kmcnt 0x02053; GFX1250-NEXT: v_pk_add_u16 v1, v1, 1 op_sel_hi:[1,0]2054; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2055; GFX1250-NEXT: v_pk_mul_lo_u16 v0, v1, v02056; GFX1250-NEXT: s_set_pc_i64 s[30:31]2057 %add = add <2 x i16> %y, <i16 1, i16 1>2058 %mul = mul <2 x i16> %add, %x2059 ret <2 x i16> %mul2060}2061 2062define <2 x i16> @v_mul_add_x_v2i16(<2 x i16> %x, <2 x i16> %y) {2063; GFX67-LABEL: v_mul_add_x_v2i16:2064; GFX67: ; %bb.0:2065; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2066; GFX67-NEXT: v_and_b32_e32 v4, 0xffff, v02067; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22068; GFX67-NEXT: v_and_b32_e32 v5, 0xffff, v12069; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32070; GFX67-NEXT: v_mad_u32_u24 v1, v5, v3, v12071; GFX67-NEXT: v_mad_u32_u24 v0, v4, v2, v02072; GFX67-NEXT: v_lshlrev_b32_e32 v3, 16, v12073; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02074; GFX67-NEXT: v_or_b32_e32 v0, v0, v32075; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12076; GFX67-NEXT: s_setpc_b64 s[30:31]2077;2078; GFX8-LABEL: v_mul_add_x_v2i16:2079; GFX8: ; %bb.0:2080; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2081; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v12082; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v02083; GFX8-NEXT: v_mad_u16 v2, v3, v2, v32084; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v22085; GFX8-NEXT: v_mad_u16 v0, v0, v1, v02086; GFX8-NEXT: v_or_b32_e32 v0, v0, v22087; GFX8-NEXT: s_setpc_b64 s[30:31]2088;2089; GFX9-LABEL: v_mul_add_x_v2i16:2090; GFX9: ; %bb.0:2091; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2092; GFX9-NEXT: v_pk_mad_u16 v0, v0, v1, v02093; GFX9-NEXT: s_setpc_b64 s[30:31]2094;2095; GFX10-LABEL: v_mul_add_x_v2i16:2096; GFX10: ; %bb.0:2097; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2098; GFX10-NEXT: v_pk_mad_u16 v0, v0, v1, v02099; GFX10-NEXT: s_setpc_b64 s[30:31]2100;2101; GFX1250-LABEL: v_mul_add_x_v2i16:2102; GFX1250: ; %bb.0:2103; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02104; GFX1250-NEXT: s_wait_kmcnt 0x02105; GFX1250-NEXT: v_pk_mad_u16 v0, v0, v1, v02106; GFX1250-NEXT: s_set_pc_i64 s[30:31]2107 %mul = mul <2 x i16> %x, %y2108 %add = add <2 x i16> %x, %mul2109 ret <2 x i16> %add2110}2111 2112define <2 x i16> @v_mul_sub_1_v2i16(<2 x i16> %x, <2 x i16> %y) {2113; GFX67-LABEL: v_mul_sub_1_v2i16:2114; GFX67: ; %bb.0:2115; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2116; GFX67-NEXT: v_add_i32_e32 v2, vcc, -1, v22117; GFX67-NEXT: v_add_i32_e32 v3, vcc, -1, v32118; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22119; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32120; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02121; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12122; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v22123; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v32124; GFX67-NEXT: s_setpc_b64 s[30:31]2125;2126; GFX8-LABEL: v_mul_sub_1_v2i16:2127; GFX8: ; %bb.0:2128; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2129; GFX8-NEXT: v_mov_b32_e32 v3, -12130; GFX8-NEXT: v_add_u16_e32 v2, -1, v12131; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2132; GFX8-NEXT: v_mul_lo_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2133; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v22134; GFX8-NEXT: v_or_b32_e32 v0, v0, v12135; GFX8-NEXT: s_setpc_b64 s[30:31]2136;2137; GFX9-LABEL: v_mul_sub_1_v2i16:2138; GFX9: ; %bb.0:2139; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2140; GFX9-NEXT: v_pk_sub_i16 v1, v1, 1 op_sel_hi:[1,0]2141; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v12142; GFX9-NEXT: s_setpc_b64 s[30:31]2143;2144; GFX10-LABEL: v_mul_sub_1_v2i16:2145; GFX10: ; %bb.0:2146; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2147; GFX10-NEXT: v_pk_sub_i16 v1, v1, 1 op_sel_hi:[1,0]2148; GFX10-NEXT: v_pk_mul_lo_u16 v0, v0, v12149; GFX10-NEXT: s_setpc_b64 s[30:31]2150;2151; GFX1250-LABEL: v_mul_sub_1_v2i16:2152; GFX1250: ; %bb.0:2153; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02154; GFX1250-NEXT: s_wait_kmcnt 0x02155; GFX1250-NEXT: v_pk_sub_i16 v1, v1, 1 op_sel_hi:[1,0]2156; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2157; GFX1250-NEXT: v_pk_mul_lo_u16 v0, v0, v12158; GFX1250-NEXT: s_set_pc_i64 s[30:31]2159 %sub = sub <2 x i16> %y, <i16 1, i16 1>2160 %mul = mul <2 x i16> %x, %sub2161 ret <2 x i16> %mul2162}2163 2164define <2 x i16> @v_mul_sub_1_v2i16_commute(<2 x i16> %x, <2 x i16> %y) {2165; GFX67-LABEL: v_mul_sub_1_v2i16_commute:2166; GFX67: ; %bb.0:2167; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2168; GFX67-NEXT: v_add_i32_e32 v2, vcc, -1, v22169; GFX67-NEXT: v_add_i32_e32 v3, vcc, -1, v32170; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22171; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32172; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02173; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12174; GFX67-NEXT: v_mul_u32_u24_e32 v0, v2, v02175; GFX67-NEXT: v_mul_u32_u24_e32 v1, v3, v12176; GFX67-NEXT: s_setpc_b64 s[30:31]2177;2178; GFX8-LABEL: v_mul_sub_1_v2i16_commute:2179; GFX8: ; %bb.0:2180; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2181; GFX8-NEXT: v_mov_b32_e32 v3, -12182; GFX8-NEXT: v_add_u16_e32 v2, -1, v12183; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2184; GFX8-NEXT: v_mul_lo_u16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12185; GFX8-NEXT: v_mul_lo_u16_e32 v0, v2, v02186; GFX8-NEXT: v_or_b32_e32 v0, v0, v12187; GFX8-NEXT: s_setpc_b64 s[30:31]2188;2189; GFX9-LABEL: v_mul_sub_1_v2i16_commute:2190; GFX9: ; %bb.0:2191; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2192; GFX9-NEXT: v_pk_sub_i16 v1, v1, 1 op_sel_hi:[1,0]2193; GFX9-NEXT: v_pk_mul_lo_u16 v0, v1, v02194; GFX9-NEXT: s_setpc_b64 s[30:31]2195;2196; GFX10-LABEL: v_mul_sub_1_v2i16_commute:2197; GFX10: ; %bb.0:2198; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2199; GFX10-NEXT: v_pk_sub_i16 v1, v1, 1 op_sel_hi:[1,0]2200; GFX10-NEXT: v_pk_mul_lo_u16 v0, v1, v02201; GFX10-NEXT: s_setpc_b64 s[30:31]2202;2203; GFX1250-LABEL: v_mul_sub_1_v2i16_commute:2204; GFX1250: ; %bb.0:2205; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02206; GFX1250-NEXT: s_wait_kmcnt 0x02207; GFX1250-NEXT: v_pk_sub_i16 v1, v1, 1 op_sel_hi:[1,0]2208; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2209; GFX1250-NEXT: v_pk_mul_lo_u16 v0, v1, v02210; GFX1250-NEXT: s_set_pc_i64 s[30:31]2211 %sub = sub <2 x i16> %y, <i16 1, i16 1>2212 %mul = mul <2 x i16> %sub, %x2213 ret <2 x i16> %mul2214}2215 2216define <2 x i16> @v_mul_sub_x_v2i16(<2 x i16> %x, <2 x i16> %y) {2217; GFX67-LABEL: v_mul_sub_x_v2i16:2218; GFX67: ; %bb.0:2219; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2220; GFX67-NEXT: v_and_b32_e32 v4, 0xffff, v02221; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22222; GFX67-NEXT: v_mul_u32_u24_e32 v2, v4, v22223; GFX67-NEXT: v_and_b32_e32 v4, 0xffff, v12224; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32225; GFX67-NEXT: v_mul_u32_u24_e32 v3, v4, v32226; GFX67-NEXT: v_sub_i32_e32 v1, vcc, v3, v12227; GFX67-NEXT: v_sub_i32_e32 v0, vcc, v2, v02228; GFX67-NEXT: v_lshlrev_b32_e32 v3, 16, v12229; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02230; GFX67-NEXT: v_or_b32_e32 v0, v0, v32231; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12232; GFX67-NEXT: s_setpc_b64 s[30:31]2233;2234; GFX8-LABEL: v_mul_sub_x_v2i16:2235; GFX8: ; %bb.0:2236; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2237; GFX8-NEXT: v_mul_lo_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12238; GFX8-NEXT: v_mul_lo_u16_e32 v1, v0, v12239; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12240; GFX8-NEXT: v_sub_u16_e32 v0, v1, v02241; GFX8-NEXT: v_or_b32_e32 v0, v0, v22242; GFX8-NEXT: s_setpc_b64 s[30:31]2243;2244; GFX9-LABEL: v_mul_sub_x_v2i16:2245; GFX9: ; %bb.0:2246; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2247; GFX9-NEXT: v_pk_mul_lo_u16 v1, v0, v12248; GFX9-NEXT: v_pk_sub_i16 v0, v1, v02249; GFX9-NEXT: s_setpc_b64 s[30:31]2250;2251; GFX10-LABEL: v_mul_sub_x_v2i16:2252; GFX10: ; %bb.0:2253; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2254; GFX10-NEXT: v_pk_mul_lo_u16 v1, v0, v12255; GFX10-NEXT: v_pk_sub_i16 v0, v1, v02256; GFX10-NEXT: s_setpc_b64 s[30:31]2257;2258; GFX1250-LABEL: v_mul_sub_x_v2i16:2259; GFX1250: ; %bb.0:2260; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02261; GFX1250-NEXT: s_wait_kmcnt 0x02262; GFX1250-NEXT: v_pk_mul_lo_u16 v1, v0, v12263; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2264; GFX1250-NEXT: v_pk_sub_i16 v0, v1, v02265; GFX1250-NEXT: s_set_pc_i64 s[30:31]2266 %mul = mul <2 x i16> %x, %y2267 %sub = sub <2 x i16> %mul, %x2268 ret <2 x i16> %sub2269}2270 2271define <2 x i16> @v_mul_add_2_v2i16(<2 x i16> %x, <2 x i16> %y) {2272; GFX67-LABEL: v_mul_add_2_v2i16:2273; GFX67: ; %bb.0:2274; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2275; GFX67-NEXT: v_add_i32_e32 v2, vcc, 2, v22276; GFX67-NEXT: v_add_i32_e32 v3, vcc, 2, v32277; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22278; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32279; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02280; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12281; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v22282; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v32283; GFX67-NEXT: s_setpc_b64 s[30:31]2284;2285; GFX8-LABEL: v_mul_add_2_v2i16:2286; GFX8: ; %bb.0:2287; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2288; GFX8-NEXT: v_mov_b32_e32 v3, 22289; GFX8-NEXT: v_add_u16_e32 v2, 2, v12290; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2291; GFX8-NEXT: v_mul_lo_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2292; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v22293; GFX8-NEXT: v_or_b32_e32 v0, v0, v12294; GFX8-NEXT: s_setpc_b64 s[30:31]2295;2296; GFX9-LABEL: v_mul_add_2_v2i16:2297; GFX9: ; %bb.0:2298; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2299; GFX9-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]2300; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v12301; GFX9-NEXT: s_setpc_b64 s[30:31]2302;2303; GFX10-LABEL: v_mul_add_2_v2i16:2304; GFX10: ; %bb.0:2305; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2306; GFX10-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]2307; GFX10-NEXT: v_pk_mul_lo_u16 v0, v0, v12308; GFX10-NEXT: s_setpc_b64 s[30:31]2309;2310; GFX1250-LABEL: v_mul_add_2_v2i16:2311; GFX1250: ; %bb.0:2312; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02313; GFX1250-NEXT: s_wait_kmcnt 0x02314; GFX1250-NEXT: v_pk_add_u16 v1, v1, 2 op_sel_hi:[1,0]2315; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2316; GFX1250-NEXT: v_pk_mul_lo_u16 v0, v0, v12317; GFX1250-NEXT: s_set_pc_i64 s[30:31]2318 %add = add <2 x i16> %y, <i16 2, i16 2>2319 %mul = mul <2 x i16> %x, %add2320 ret <2 x i16> %mul2321}2322 2323define <2 x i16> @v_mul_sub_2_v2i16(<2 x i16> %x, <2 x i16> %y) {2324; GFX67-LABEL: v_mul_sub_2_v2i16:2325; GFX67: ; %bb.0:2326; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2327; GFX67-NEXT: v_add_i32_e32 v2, vcc, -2, v22328; GFX67-NEXT: v_add_i32_e32 v3, vcc, -2, v32329; GFX67-NEXT: v_and_b32_e32 v2, 0xffff, v22330; GFX67-NEXT: v_and_b32_e32 v3, 0xffff, v32331; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v02332; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v12333; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v22334; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v32335; GFX67-NEXT: s_setpc_b64 s[30:31]2336;2337; GFX8-LABEL: v_mul_sub_2_v2i16:2338; GFX8: ; %bb.0:2339; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2340; GFX8-NEXT: v_mov_b32_e32 v3, -22341; GFX8-NEXT: v_add_u16_e32 v2, -2, v12342; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2343; GFX8-NEXT: v_mul_lo_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2344; GFX8-NEXT: v_mul_lo_u16_e32 v0, v0, v22345; GFX8-NEXT: v_or_b32_e32 v0, v0, v12346; GFX8-NEXT: s_setpc_b64 s[30:31]2347;2348; GFX9-LABEL: v_mul_sub_2_v2i16:2349; GFX9: ; %bb.0:2350; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2351; GFX9-NEXT: v_pk_sub_i16 v1, v1, 2 op_sel_hi:[1,0]2352; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v12353; GFX9-NEXT: s_setpc_b64 s[30:31]2354;2355; GFX10-LABEL: v_mul_sub_2_v2i16:2356; GFX10: ; %bb.0:2357; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2358; GFX10-NEXT: v_pk_sub_i16 v1, v1, 2 op_sel_hi:[1,0]2359; GFX10-NEXT: v_pk_mul_lo_u16 v0, v0, v12360; GFX10-NEXT: s_setpc_b64 s[30:31]2361;2362; GFX1250-LABEL: v_mul_sub_2_v2i16:2363; GFX1250: ; %bb.0:2364; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02365; GFX1250-NEXT: s_wait_kmcnt 0x02366; GFX1250-NEXT: v_pk_sub_i16 v1, v1, 2 op_sel_hi:[1,0]2367; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2368; GFX1250-NEXT: v_pk_mul_lo_u16 v0, v0, v12369; GFX1250-NEXT: s_set_pc_i64 s[30:31]2370 %sub = sub <2 x i16> %y, <i16 2, i16 2>2371 %mul = mul <2 x i16> %x, %sub2372 ret <2 x i16> %mul2373}2374 2375define <2 x i32> @v_mul_add_1_v2i32(<2 x i32> %x, <2 x i32> %y) {2376; GFX67-LABEL: v_mul_add_1_v2i32:2377; GFX67: ; %bb.0:2378; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2379; GFX67-NEXT: v_mul_lo_u32 v2, v0, v22380; GFX67-NEXT: v_mul_lo_u32 v3, v1, v32381; GFX67-NEXT: v_add_i32_e32 v0, vcc, v2, v02382; GFX67-NEXT: v_add_i32_e32 v1, vcc, v3, v12383; GFX67-NEXT: s_setpc_b64 s[30:31]2384;2385; GFX8-LABEL: v_mul_add_1_v2i32:2386; GFX8: ; %bb.0:2387; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2388; GFX8-NEXT: v_mul_lo_u32 v2, v0, v22389; GFX8-NEXT: v_mul_lo_u32 v3, v1, v32390; GFX8-NEXT: v_add_u32_e32 v0, vcc, v2, v02391; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v12392; GFX8-NEXT: s_setpc_b64 s[30:31]2393;2394; GFX900-LABEL: v_mul_add_1_v2i32:2395; GFX900: ; %bb.0:2396; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2397; GFX900-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]2398; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v1, v3, v[1:2]2399; GFX900-NEXT: v_mov_b32_e32 v0, v42400; GFX900-NEXT: s_setpc_b64 s[30:31]2401;2402; GFX90A-LABEL: v_mul_add_1_v2i32:2403; GFX90A: ; %bb.0:2404; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2405; GFX90A-NEXT: v_mov_b32_e32 v4, v12406; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[0:1]2407; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v3, v[4:5]2408; GFX90A-NEXT: v_mov_b32_e32 v1, v22409; GFX90A-NEXT: s_setpc_b64 s[30:31]2410;2411; GFX10-LABEL: v_mul_add_1_v2i32:2412; GFX10: ; %bb.0:2413; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2414; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, v[0:1]2415; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, v1, v3, v[1:2]2416; GFX10-NEXT: v_mov_b32_e32 v0, v42417; GFX10-NEXT: s_setpc_b64 s[30:31]2418;2419; GFX1250-LABEL: v_mul_add_1_v2i32:2420; GFX1250: ; %bb.0:2421; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02422; GFX1250-NEXT: s_wait_kmcnt 0x02423; GFX1250-NEXT: v_mad_u32 v0, v0, v2, v02424; GFX1250-NEXT: v_mad_u32 v1, v1, v3, v12425; GFX1250-NEXT: s_set_pc_i64 s[30:31]2426 %add = add <2 x i32> %y, <i32 1, i32 1>2427 %mul = mul <2 x i32> %x, %add2428 ret <2 x i32> %mul2429}2430 2431define <2 x i32> @v_mul_add_1_v2i32_commute(<2 x i32> %x, <2 x i32> %y) {2432; GFX67-LABEL: v_mul_add_1_v2i32_commute:2433; GFX67: ; %bb.0:2434; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2435; GFX67-NEXT: v_mul_lo_u32 v2, v0, v22436; GFX67-NEXT: v_mul_lo_u32 v3, v1, v32437; GFX67-NEXT: v_add_i32_e32 v0, vcc, v2, v02438; GFX67-NEXT: v_add_i32_e32 v1, vcc, v3, v12439; GFX67-NEXT: s_setpc_b64 s[30:31]2440;2441; GFX8-LABEL: v_mul_add_1_v2i32_commute:2442; GFX8: ; %bb.0:2443; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2444; GFX8-NEXT: v_mul_lo_u32 v2, v0, v22445; GFX8-NEXT: v_mul_lo_u32 v3, v1, v32446; GFX8-NEXT: v_add_u32_e32 v0, vcc, v2, v02447; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v12448; GFX8-NEXT: s_setpc_b64 s[30:31]2449;2450; GFX900-LABEL: v_mul_add_1_v2i32_commute:2451; GFX900: ; %bb.0:2452; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2453; GFX900-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]2454; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v1, v3, v[1:2]2455; GFX900-NEXT: v_mov_b32_e32 v0, v42456; GFX900-NEXT: s_setpc_b64 s[30:31]2457;2458; GFX90A-LABEL: v_mul_add_1_v2i32_commute:2459; GFX90A: ; %bb.0:2460; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2461; GFX90A-NEXT: v_mov_b32_e32 v4, v12462; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[0:1]2463; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v3, v[4:5]2464; GFX90A-NEXT: v_mov_b32_e32 v1, v22465; GFX90A-NEXT: s_setpc_b64 s[30:31]2466;2467; GFX10-LABEL: v_mul_add_1_v2i32_commute:2468; GFX10: ; %bb.0:2469; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2470; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, v[0:1]2471; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, v1, v3, v[1:2]2472; GFX10-NEXT: v_mov_b32_e32 v0, v42473; GFX10-NEXT: s_setpc_b64 s[30:31]2474;2475; GFX1250-LABEL: v_mul_add_1_v2i32_commute:2476; GFX1250: ; %bb.0:2477; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02478; GFX1250-NEXT: s_wait_kmcnt 0x02479; GFX1250-NEXT: v_mad_u32 v0, v0, v2, v02480; GFX1250-NEXT: v_mad_u32 v1, v1, v3, v12481; GFX1250-NEXT: s_set_pc_i64 s[30:31]2482 %add = add <2 x i32> %y, <i32 1, i32 1>2483 %mul = mul <2 x i32> %add, %x2484 ret <2 x i32> %mul2485}2486 2487define <2 x i32> @v_mul_add_x_v2i32(<2 x i32> %x, <2 x i32> %y) {2488; GFX67-LABEL: v_mul_add_x_v2i32:2489; GFX67: ; %bb.0:2490; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2491; GFX67-NEXT: v_mul_lo_u32 v2, v0, v22492; GFX67-NEXT: v_mul_lo_u32 v3, v1, v32493; GFX67-NEXT: v_add_i32_e32 v0, vcc, v0, v22494; GFX67-NEXT: v_add_i32_e32 v1, vcc, v1, v32495; GFX67-NEXT: s_setpc_b64 s[30:31]2496;2497; GFX8-LABEL: v_mul_add_x_v2i32:2498; GFX8: ; %bb.0:2499; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2500; GFX8-NEXT: v_mul_lo_u32 v2, v0, v22501; GFX8-NEXT: v_mul_lo_u32 v3, v1, v32502; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v22503; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v32504; GFX8-NEXT: s_setpc_b64 s[30:31]2505;2506; GFX900-LABEL: v_mul_add_x_v2i32:2507; GFX900: ; %bb.0:2508; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2509; GFX900-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v0, v2, v[0:1]2510; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v1, v3, v[1:2]2511; GFX900-NEXT: v_mov_b32_e32 v0, v42512; GFX900-NEXT: s_setpc_b64 s[30:31]2513;2514; GFX90A-LABEL: v_mul_add_x_v2i32:2515; GFX90A: ; %bb.0:2516; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2517; GFX90A-NEXT: v_mov_b32_e32 v4, v12518; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[0:1]2519; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, v3, v[4:5]2520; GFX90A-NEXT: v_mov_b32_e32 v1, v22521; GFX90A-NEXT: s_setpc_b64 s[30:31]2522;2523; GFX10-LABEL: v_mul_add_x_v2i32:2524; GFX10: ; %bb.0:2525; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2526; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v0, v2, v[0:1]2527; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, v1, v3, v[1:2]2528; GFX10-NEXT: v_mov_b32_e32 v0, v42529; GFX10-NEXT: s_setpc_b64 s[30:31]2530;2531; GFX1250-LABEL: v_mul_add_x_v2i32:2532; GFX1250: ; %bb.0:2533; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02534; GFX1250-NEXT: s_wait_kmcnt 0x02535; GFX1250-NEXT: v_mad_u32 v0, v0, v2, v02536; GFX1250-NEXT: v_mad_u32 v1, v1, v3, v12537; GFX1250-NEXT: s_set_pc_i64 s[30:31]2538 %mul = mul <2 x i32> %x, %y2539 %add = add <2 x i32> %x, %mul2540 ret <2 x i32> %add2541}2542 2543define <2 x i32> @v_mul_sub_1_v2i32(<2 x i32> %x, <2 x i32> %y) {2544; GFX67-LABEL: v_mul_sub_1_v2i32:2545; GFX67: ; %bb.0:2546; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2547; GFX67-NEXT: v_add_i32_e32 v3, vcc, -1, v32548; GFX67-NEXT: v_add_i32_e32 v2, vcc, -1, v22549; GFX67-NEXT: v_mul_lo_u32 v0, v0, v22550; GFX67-NEXT: v_mul_lo_u32 v1, v1, v32551; GFX67-NEXT: s_setpc_b64 s[30:31]2552;2553; GFX8-LABEL: v_mul_sub_1_v2i32:2554; GFX8: ; %bb.0:2555; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2556; GFX8-NEXT: v_add_u32_e32 v3, vcc, -1, v32557; GFX8-NEXT: v_add_u32_e32 v2, vcc, -1, v22558; GFX8-NEXT: v_mul_lo_u32 v0, v0, v22559; GFX8-NEXT: v_mul_lo_u32 v1, v1, v32560; GFX8-NEXT: s_setpc_b64 s[30:31]2561;2562; GFX9-LABEL: v_mul_sub_1_v2i32:2563; GFX9: ; %bb.0:2564; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2565; GFX9-NEXT: v_add_u32_e32 v3, -1, v32566; GFX9-NEXT: v_add_u32_e32 v2, -1, v22567; GFX9-NEXT: v_mul_lo_u32 v0, v0, v22568; GFX9-NEXT: v_mul_lo_u32 v1, v1, v32569; GFX9-NEXT: s_setpc_b64 s[30:31]2570;2571; GFX10-LABEL: v_mul_sub_1_v2i32:2572; GFX10: ; %bb.0:2573; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2574; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v22575; GFX10-NEXT: v_add_nc_u32_e32 v3, -1, v32576; GFX10-NEXT: v_mul_lo_u32 v0, v0, v22577; GFX10-NEXT: v_mul_lo_u32 v1, v1, v32578; GFX10-NEXT: s_setpc_b64 s[30:31]2579;2580; GFX1250-LABEL: v_mul_sub_1_v2i32:2581; GFX1250: ; %bb.0:2582; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02583; GFX1250-NEXT: s_wait_kmcnt 0x02584; GFX1250-NEXT: v_dual_add_nc_u32 v2, -1, v2 :: v_dual_add_nc_u32 v3, -1, v32585; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2586; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v22587; GFX1250-NEXT: v_mul_lo_u32 v1, v1, v32588; GFX1250-NEXT: s_set_pc_i64 s[30:31]2589 %sub = sub <2 x i32> %y, <i32 1, i32 1>2590 %mul = mul <2 x i32> %x, %sub2591 ret <2 x i32> %mul2592}2593 2594define <2 x i32> @v_mul_sub_1_v2i32_commute(<2 x i32> %x, <2 x i32> %y) {2595; GFX67-LABEL: v_mul_sub_1_v2i32_commute:2596; GFX67: ; %bb.0:2597; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2598; GFX67-NEXT: v_add_i32_e32 v3, vcc, -1, v32599; GFX67-NEXT: v_add_i32_e32 v2, vcc, -1, v22600; GFX67-NEXT: v_mul_lo_u32 v0, v2, v02601; GFX67-NEXT: v_mul_lo_u32 v1, v3, v12602; GFX67-NEXT: s_setpc_b64 s[30:31]2603;2604; GFX8-LABEL: v_mul_sub_1_v2i32_commute:2605; GFX8: ; %bb.0:2606; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2607; GFX8-NEXT: v_add_u32_e32 v3, vcc, -1, v32608; GFX8-NEXT: v_add_u32_e32 v2, vcc, -1, v22609; GFX8-NEXT: v_mul_lo_u32 v0, v2, v02610; GFX8-NEXT: v_mul_lo_u32 v1, v3, v12611; GFX8-NEXT: s_setpc_b64 s[30:31]2612;2613; GFX9-LABEL: v_mul_sub_1_v2i32_commute:2614; GFX9: ; %bb.0:2615; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2616; GFX9-NEXT: v_add_u32_e32 v3, -1, v32617; GFX9-NEXT: v_add_u32_e32 v2, -1, v22618; GFX9-NEXT: v_mul_lo_u32 v0, v2, v02619; GFX9-NEXT: v_mul_lo_u32 v1, v3, v12620; GFX9-NEXT: s_setpc_b64 s[30:31]2621;2622; GFX10-LABEL: v_mul_sub_1_v2i32_commute:2623; GFX10: ; %bb.0:2624; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2625; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v22626; GFX10-NEXT: v_add_nc_u32_e32 v3, -1, v32627; GFX10-NEXT: v_mul_lo_u32 v0, v2, v02628; GFX10-NEXT: v_mul_lo_u32 v1, v3, v12629; GFX10-NEXT: s_setpc_b64 s[30:31]2630;2631; GFX1250-LABEL: v_mul_sub_1_v2i32_commute:2632; GFX1250: ; %bb.0:2633; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02634; GFX1250-NEXT: s_wait_kmcnt 0x02635; GFX1250-NEXT: v_dual_add_nc_u32 v2, -1, v2 :: v_dual_add_nc_u32 v3, -1, v32636; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2637; GFX1250-NEXT: v_mul_lo_u32 v0, v2, v02638; GFX1250-NEXT: v_mul_lo_u32 v1, v3, v12639; GFX1250-NEXT: s_set_pc_i64 s[30:31]2640 %sub = sub <2 x i32> %y, <i32 1, i32 1>2641 %mul = mul <2 x i32> %sub, %x2642 ret <2 x i32> %mul2643}2644 2645define <2 x i32> @v_mul_sub_x_v2i32(<2 x i32> %x, <2 x i32> %y) {2646; GFX67-LABEL: v_mul_sub_x_v2i32:2647; GFX67: ; %bb.0:2648; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2649; GFX67-NEXT: v_mul_lo_u32 v2, v0, v22650; GFX67-NEXT: v_mul_lo_u32 v3, v1, v32651; GFX67-NEXT: v_sub_i32_e32 v0, vcc, v2, v02652; GFX67-NEXT: v_sub_i32_e32 v1, vcc, v3, v12653; GFX67-NEXT: s_setpc_b64 s[30:31]2654;2655; GFX8-LABEL: v_mul_sub_x_v2i32:2656; GFX8: ; %bb.0:2657; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2658; GFX8-NEXT: v_mul_lo_u32 v2, v0, v22659; GFX8-NEXT: v_mul_lo_u32 v3, v1, v32660; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v2, v02661; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v12662; GFX8-NEXT: s_setpc_b64 s[30:31]2663;2664; GFX900-LABEL: v_mul_sub_x_v2i32:2665; GFX900: ; %bb.0:2666; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2667; GFX900-NEXT: v_mul_lo_u32 v2, v0, v22668; GFX900-NEXT: v_mul_lo_u32 v3, v1, v32669; GFX900-NEXT: v_sub_u32_e32 v0, v2, v02670; GFX900-NEXT: v_sub_u32_e32 v1, v3, v12671; GFX900-NEXT: s_setpc_b64 s[30:31]2672;2673; GFX90A-LABEL: v_mul_sub_x_v2i32:2674; GFX90A: ; %bb.0:2675; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2676; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v32677; GFX90A-NEXT: v_mul_lo_u32 v2, v0, v22678; GFX90A-NEXT: v_sub_u32_e32 v0, v2, v02679; GFX90A-NEXT: v_sub_u32_e32 v1, v3, v12680; GFX90A-NEXT: s_setpc_b64 s[30:31]2681;2682; GFX10-LABEL: v_mul_sub_x_v2i32:2683; GFX10: ; %bb.0:2684; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2685; GFX10-NEXT: v_mul_lo_u32 v2, v0, v22686; GFX10-NEXT: v_mul_lo_u32 v3, v1, v32687; GFX10-NEXT: v_sub_nc_u32_e32 v0, v2, v02688; GFX10-NEXT: v_sub_nc_u32_e32 v1, v3, v12689; GFX10-NEXT: s_setpc_b64 s[30:31]2690;2691; GFX1250-LABEL: v_mul_sub_x_v2i32:2692; GFX1250: ; %bb.0:2693; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02694; GFX1250-NEXT: s_wait_kmcnt 0x02695; GFX1250-NEXT: v_mul_lo_u32 v2, v0, v22696; GFX1250-NEXT: v_mul_lo_u32 v3, v1, v32697; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2698; GFX1250-NEXT: v_dual_sub_nc_u32 v0, v2, v0 :: v_dual_sub_nc_u32 v1, v3, v12699; GFX1250-NEXT: s_set_pc_i64 s[30:31]2700 %mul = mul <2 x i32> %x, %y2701 %sub = sub <2 x i32> %mul, %x2702 ret <2 x i32> %sub2703}2704 2705define <2 x i32> @v_mul_add_2_v2i32(<2 x i32> %x, <2 x i32> %y) {2706; GFX67-LABEL: v_mul_add_2_v2i32:2707; GFX67: ; %bb.0:2708; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2709; GFX67-NEXT: v_add_i32_e32 v3, vcc, 2, v32710; GFX67-NEXT: v_add_i32_e32 v2, vcc, 2, v22711; GFX67-NEXT: v_mul_lo_u32 v0, v0, v22712; GFX67-NEXT: v_mul_lo_u32 v1, v1, v32713; GFX67-NEXT: s_setpc_b64 s[30:31]2714;2715; GFX8-LABEL: v_mul_add_2_v2i32:2716; GFX8: ; %bb.0:2717; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2718; GFX8-NEXT: v_add_u32_e32 v3, vcc, 2, v32719; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v22720; GFX8-NEXT: v_mul_lo_u32 v0, v0, v22721; GFX8-NEXT: v_mul_lo_u32 v1, v1, v32722; GFX8-NEXT: s_setpc_b64 s[30:31]2723;2724; GFX9-LABEL: v_mul_add_2_v2i32:2725; GFX9: ; %bb.0:2726; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2727; GFX9-NEXT: v_add_u32_e32 v3, 2, v32728; GFX9-NEXT: v_add_u32_e32 v2, 2, v22729; GFX9-NEXT: v_mul_lo_u32 v0, v0, v22730; GFX9-NEXT: v_mul_lo_u32 v1, v1, v32731; GFX9-NEXT: s_setpc_b64 s[30:31]2732;2733; GFX10-LABEL: v_mul_add_2_v2i32:2734; GFX10: ; %bb.0:2735; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2736; GFX10-NEXT: v_add_nc_u32_e32 v2, 2, v22737; GFX10-NEXT: v_add_nc_u32_e32 v3, 2, v32738; GFX10-NEXT: v_mul_lo_u32 v0, v0, v22739; GFX10-NEXT: v_mul_lo_u32 v1, v1, v32740; GFX10-NEXT: s_setpc_b64 s[30:31]2741;2742; GFX1250-LABEL: v_mul_add_2_v2i32:2743; GFX1250: ; %bb.0:2744; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02745; GFX1250-NEXT: s_wait_kmcnt 0x02746; GFX1250-NEXT: v_dual_add_nc_u32 v2, 2, v2 :: v_dual_add_nc_u32 v3, 2, v32747; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2748; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v22749; GFX1250-NEXT: v_mul_lo_u32 v1, v1, v32750; GFX1250-NEXT: s_set_pc_i64 s[30:31]2751 %add = add <2 x i32> %y, <i32 2, i32 2>2752 %mul = mul <2 x i32> %x, %add2753 ret <2 x i32> %mul2754}2755 2756define <2 x i32> @v_mul_sub_2_v2i32(<2 x i32> %x, <2 x i32> %y) {2757; GFX67-LABEL: v_mul_sub_2_v2i32:2758; GFX67: ; %bb.0:2759; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2760; GFX67-NEXT: v_add_i32_e32 v3, vcc, -2, v32761; GFX67-NEXT: v_add_i32_e32 v2, vcc, -2, v22762; GFX67-NEXT: v_mul_lo_u32 v0, v0, v22763; GFX67-NEXT: v_mul_lo_u32 v1, v1, v32764; GFX67-NEXT: s_setpc_b64 s[30:31]2765;2766; GFX8-LABEL: v_mul_sub_2_v2i32:2767; GFX8: ; %bb.0:2768; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2769; GFX8-NEXT: v_add_u32_e32 v3, vcc, -2, v32770; GFX8-NEXT: v_add_u32_e32 v2, vcc, -2, v22771; GFX8-NEXT: v_mul_lo_u32 v0, v0, v22772; GFX8-NEXT: v_mul_lo_u32 v1, v1, v32773; GFX8-NEXT: s_setpc_b64 s[30:31]2774;2775; GFX9-LABEL: v_mul_sub_2_v2i32:2776; GFX9: ; %bb.0:2777; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2778; GFX9-NEXT: v_add_u32_e32 v3, -2, v32779; GFX9-NEXT: v_add_u32_e32 v2, -2, v22780; GFX9-NEXT: v_mul_lo_u32 v0, v0, v22781; GFX9-NEXT: v_mul_lo_u32 v1, v1, v32782; GFX9-NEXT: s_setpc_b64 s[30:31]2783;2784; GFX10-LABEL: v_mul_sub_2_v2i32:2785; GFX10: ; %bb.0:2786; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2787; GFX10-NEXT: v_add_nc_u32_e32 v2, -2, v22788; GFX10-NEXT: v_add_nc_u32_e32 v3, -2, v32789; GFX10-NEXT: v_mul_lo_u32 v0, v0, v22790; GFX10-NEXT: v_mul_lo_u32 v1, v1, v32791; GFX10-NEXT: s_setpc_b64 s[30:31]2792;2793; GFX1250-LABEL: v_mul_sub_2_v2i32:2794; GFX1250: ; %bb.0:2795; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02796; GFX1250-NEXT: s_wait_kmcnt 0x02797; GFX1250-NEXT: v_dual_add_nc_u32 v2, -2, v2 :: v_dual_add_nc_u32 v3, -2, v32798; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2799; GFX1250-NEXT: v_mul_lo_u32 v0, v0, v22800; GFX1250-NEXT: v_mul_lo_u32 v1, v1, v32801; GFX1250-NEXT: s_set_pc_i64 s[30:31]2802 %sub = sub <2 x i32> %y, <i32 2, i32 2>2803 %mul = mul <2 x i32> %x, %sub2804 ret <2 x i32> %mul2805}2806 2807define <2 x i24> @v_mul_add_1_v2i24(<2 x i24> %x, <2 x i24> %y) {2808; GFX67-LABEL: v_mul_add_1_v2i24:2809; GFX67: ; %bb.0:2810; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2811; GFX67-NEXT: v_add_i32_e32 v3, vcc, 1, v32812; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v22813; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v22814; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v32815; GFX67-NEXT: s_setpc_b64 s[30:31]2816;2817; GFX8-LABEL: v_mul_add_1_v2i24:2818; GFX8: ; %bb.0:2819; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2820; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v32821; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v22822; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v22823; GFX8-NEXT: v_mul_u32_u24_e32 v1, v1, v32824; GFX8-NEXT: s_setpc_b64 s[30:31]2825;2826; GFX9-LABEL: v_mul_add_1_v2i24:2827; GFX9: ; %bb.0:2828; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2829; GFX9-NEXT: v_add_u32_e32 v3, 1, v32830; GFX9-NEXT: v_add_u32_e32 v2, 1, v22831; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v22832; GFX9-NEXT: v_mul_u32_u24_e32 v1, v1, v32833; GFX9-NEXT: s_setpc_b64 s[30:31]2834;2835; GFX10-LABEL: v_mul_add_1_v2i24:2836; GFX10: ; %bb.0:2837; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2838; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v22839; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v32840; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v22841; GFX10-NEXT: v_mul_u32_u24_e32 v1, v1, v32842; GFX10-NEXT: s_setpc_b64 s[30:31]2843;2844; GFX1250-LABEL: v_mul_add_1_v2i24:2845; GFX1250: ; %bb.0:2846; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02847; GFX1250-NEXT: s_wait_kmcnt 0x02848; GFX1250-NEXT: v_dual_add_nc_u32 v2, 1, v2 :: v_dual_add_nc_u32 v3, 1, v32849; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2850; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v22851; GFX1250-NEXT: v_mul_u32_u24_e32 v1, v1, v32852; GFX1250-NEXT: s_set_pc_i64 s[30:31]2853 %add = add <2 x i24> %y, <i24 1, i24 1>2854 %mul = mul <2 x i24> %x, %add2855 ret <2 x i24> %mul2856}2857 2858define <2 x i24> @v_mul_add_1_v2i24_commute(<2 x i24> %x, <2 x i24> %y) {2859; GFX67-LABEL: v_mul_add_1_v2i24_commute:2860; GFX67: ; %bb.0:2861; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2862; GFX67-NEXT: v_add_i32_e32 v3, vcc, 1, v32863; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v22864; GFX67-NEXT: v_mul_u32_u24_e32 v0, v2, v02865; GFX67-NEXT: v_mul_u32_u24_e32 v1, v3, v12866; GFX67-NEXT: s_setpc_b64 s[30:31]2867;2868; GFX8-LABEL: v_mul_add_1_v2i24_commute:2869; GFX8: ; %bb.0:2870; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2871; GFX8-NEXT: v_add_u32_e32 v3, vcc, 1, v32872; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v22873; GFX8-NEXT: v_mul_u32_u24_e32 v0, v2, v02874; GFX8-NEXT: v_mul_u32_u24_e32 v1, v3, v12875; GFX8-NEXT: s_setpc_b64 s[30:31]2876;2877; GFX9-LABEL: v_mul_add_1_v2i24_commute:2878; GFX9: ; %bb.0:2879; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2880; GFX9-NEXT: v_add_u32_e32 v3, 1, v32881; GFX9-NEXT: v_add_u32_e32 v2, 1, v22882; GFX9-NEXT: v_mul_u32_u24_e32 v0, v2, v02883; GFX9-NEXT: v_mul_u32_u24_e32 v1, v3, v12884; GFX9-NEXT: s_setpc_b64 s[30:31]2885;2886; GFX10-LABEL: v_mul_add_1_v2i24_commute:2887; GFX10: ; %bb.0:2888; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2889; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v22890; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v32891; GFX10-NEXT: v_mul_u32_u24_e32 v0, v2, v02892; GFX10-NEXT: v_mul_u32_u24_e32 v1, v3, v12893; GFX10-NEXT: s_setpc_b64 s[30:31]2894;2895; GFX1250-LABEL: v_mul_add_1_v2i24_commute:2896; GFX1250: ; %bb.0:2897; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02898; GFX1250-NEXT: s_wait_kmcnt 0x02899; GFX1250-NEXT: v_dual_add_nc_u32 v2, 1, v2 :: v_dual_add_nc_u32 v3, 1, v32900; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2901; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v2, v02902; GFX1250-NEXT: v_mul_u32_u24_e32 v1, v3, v12903; GFX1250-NEXT: s_set_pc_i64 s[30:31]2904 %add = add <2 x i24> %y, <i24 1, i24 1>2905 %mul = mul <2 x i24> %add, %x2906 ret <2 x i24> %mul2907}2908 2909define <2 x i24> @v_mul_add_x_v2i24(<2 x i24> %x, <2 x i24> %y) {2910; GFX67-LABEL: v_mul_add_x_v2i24:2911; GFX67: ; %bb.0:2912; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2913; GFX67-NEXT: v_mad_u32_u24 v0, v0, v2, v02914; GFX67-NEXT: v_mad_u32_u24 v1, v1, v3, v12915; GFX67-NEXT: s_setpc_b64 s[30:31]2916;2917; GFX8-LABEL: v_mul_add_x_v2i24:2918; GFX8: ; %bb.0:2919; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2920; GFX8-NEXT: v_mad_u32_u24 v0, v0, v2, v02921; GFX8-NEXT: v_mad_u32_u24 v1, v1, v3, v12922; GFX8-NEXT: s_setpc_b64 s[30:31]2923;2924; GFX9-LABEL: v_mul_add_x_v2i24:2925; GFX9: ; %bb.0:2926; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2927; GFX9-NEXT: v_mad_u32_u24 v0, v0, v2, v02928; GFX9-NEXT: v_mad_u32_u24 v1, v1, v3, v12929; GFX9-NEXT: s_setpc_b64 s[30:31]2930;2931; GFX10-LABEL: v_mul_add_x_v2i24:2932; GFX10: ; %bb.0:2933; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2934; GFX10-NEXT: v_mad_u32_u24 v0, v0, v2, v02935; GFX10-NEXT: v_mad_u32_u24 v1, v1, v3, v12936; GFX10-NEXT: s_setpc_b64 s[30:31]2937;2938; GFX1250-LABEL: v_mul_add_x_v2i24:2939; GFX1250: ; %bb.0:2940; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02941; GFX1250-NEXT: s_wait_kmcnt 0x02942; GFX1250-NEXT: v_mad_u32_u24 v0, v0, v2, v02943; GFX1250-NEXT: v_mad_u32_u24 v1, v1, v3, v12944; GFX1250-NEXT: s_set_pc_i64 s[30:31]2945 %mul = mul <2 x i24> %x, %y2946 %add = add <2 x i24> %x, %mul2947 ret <2 x i24> %add2948}2949 2950define <2 x i24> @v_mul_sub_1_v2i24(<2 x i24> %x, <2 x i24> %y) {2951; GFX67-LABEL: v_mul_sub_1_v2i24:2952; GFX67: ; %bb.0:2953; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2954; GFX67-NEXT: v_add_i32_e32 v3, vcc, -1, v32955; GFX67-NEXT: v_add_i32_e32 v2, vcc, -1, v22956; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v22957; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v32958; GFX67-NEXT: s_setpc_b64 s[30:31]2959;2960; GFX8-LABEL: v_mul_sub_1_v2i24:2961; GFX8: ; %bb.0:2962; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2963; GFX8-NEXT: v_add_u32_e32 v3, vcc, -1, v32964; GFX8-NEXT: v_add_u32_e32 v2, vcc, -1, v22965; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v22966; GFX8-NEXT: v_mul_u32_u24_e32 v1, v1, v32967; GFX8-NEXT: s_setpc_b64 s[30:31]2968;2969; GFX9-LABEL: v_mul_sub_1_v2i24:2970; GFX9: ; %bb.0:2971; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2972; GFX9-NEXT: v_add_u32_e32 v3, -1, v32973; GFX9-NEXT: v_add_u32_e32 v2, -1, v22974; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v22975; GFX9-NEXT: v_mul_u32_u24_e32 v1, v1, v32976; GFX9-NEXT: s_setpc_b64 s[30:31]2977;2978; GFX10-LABEL: v_mul_sub_1_v2i24:2979; GFX10: ; %bb.0:2980; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2981; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v22982; GFX10-NEXT: v_add_nc_u32_e32 v3, -1, v32983; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v22984; GFX10-NEXT: v_mul_u32_u24_e32 v1, v1, v32985; GFX10-NEXT: s_setpc_b64 s[30:31]2986;2987; GFX1250-LABEL: v_mul_sub_1_v2i24:2988; GFX1250: ; %bb.0:2989; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02990; GFX1250-NEXT: s_wait_kmcnt 0x02991; GFX1250-NEXT: v_dual_add_nc_u32 v2, -1, v2 :: v_dual_add_nc_u32 v3, -1, v32992; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2993; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v22994; GFX1250-NEXT: v_mul_u32_u24_e32 v1, v1, v32995; GFX1250-NEXT: s_set_pc_i64 s[30:31]2996 %sub = sub <2 x i24> %y, <i24 1, i24 1>2997 %mul = mul <2 x i24> %x, %sub2998 ret <2 x i24> %mul2999}3000 3001define <2 x i24> @v_mul_sub_1_v2i24_commute(<2 x i24> %x, <2 x i24> %y) {3002; GFX67-LABEL: v_mul_sub_1_v2i24_commute:3003; GFX67: ; %bb.0:3004; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3005; GFX67-NEXT: v_add_i32_e32 v3, vcc, -1, v33006; GFX67-NEXT: v_add_i32_e32 v2, vcc, -1, v23007; GFX67-NEXT: v_mul_u32_u24_e32 v0, v2, v03008; GFX67-NEXT: v_mul_u32_u24_e32 v1, v3, v13009; GFX67-NEXT: s_setpc_b64 s[30:31]3010;3011; GFX8-LABEL: v_mul_sub_1_v2i24_commute:3012; GFX8: ; %bb.0:3013; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3014; GFX8-NEXT: v_add_u32_e32 v3, vcc, -1, v33015; GFX8-NEXT: v_add_u32_e32 v2, vcc, -1, v23016; GFX8-NEXT: v_mul_u32_u24_e32 v0, v2, v03017; GFX8-NEXT: v_mul_u32_u24_e32 v1, v3, v13018; GFX8-NEXT: s_setpc_b64 s[30:31]3019;3020; GFX9-LABEL: v_mul_sub_1_v2i24_commute:3021; GFX9: ; %bb.0:3022; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3023; GFX9-NEXT: v_add_u32_e32 v3, -1, v33024; GFX9-NEXT: v_add_u32_e32 v2, -1, v23025; GFX9-NEXT: v_mul_u32_u24_e32 v0, v2, v03026; GFX9-NEXT: v_mul_u32_u24_e32 v1, v3, v13027; GFX9-NEXT: s_setpc_b64 s[30:31]3028;3029; GFX10-LABEL: v_mul_sub_1_v2i24_commute:3030; GFX10: ; %bb.0:3031; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3032; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v23033; GFX10-NEXT: v_add_nc_u32_e32 v3, -1, v33034; GFX10-NEXT: v_mul_u32_u24_e32 v0, v2, v03035; GFX10-NEXT: v_mul_u32_u24_e32 v1, v3, v13036; GFX10-NEXT: s_setpc_b64 s[30:31]3037;3038; GFX1250-LABEL: v_mul_sub_1_v2i24_commute:3039; GFX1250: ; %bb.0:3040; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03041; GFX1250-NEXT: s_wait_kmcnt 0x03042; GFX1250-NEXT: v_dual_add_nc_u32 v2, -1, v2 :: v_dual_add_nc_u32 v3, -1, v33043; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)3044; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v2, v03045; GFX1250-NEXT: v_mul_u32_u24_e32 v1, v3, v13046; GFX1250-NEXT: s_set_pc_i64 s[30:31]3047 %sub = sub <2 x i24> %y, <i24 1, i24 1>3048 %mul = mul <2 x i24> %sub, %x3049 ret <2 x i24> %mul3050}3051 3052define <2 x i24> @v_mul_sub_x_v2i24(<2 x i24> %x, <2 x i24> %y) {3053; GFX67-LABEL: v_mul_sub_x_v2i24:3054; GFX67: ; %bb.0:3055; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3056; GFX67-NEXT: v_mul_u32_u24_e32 v2, v0, v23057; GFX67-NEXT: v_mul_u32_u24_e32 v3, v1, v33058; GFX67-NEXT: v_sub_i32_e32 v0, vcc, v2, v03059; GFX67-NEXT: v_sub_i32_e32 v1, vcc, v3, v13060; GFX67-NEXT: s_setpc_b64 s[30:31]3061;3062; GFX8-LABEL: v_mul_sub_x_v2i24:3063; GFX8: ; %bb.0:3064; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3065; GFX8-NEXT: v_mul_u32_u24_e32 v2, v0, v23066; GFX8-NEXT: v_mul_u32_u24_e32 v3, v1, v33067; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v2, v03068; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v3, v13069; GFX8-NEXT: s_setpc_b64 s[30:31]3070;3071; GFX9-LABEL: v_mul_sub_x_v2i24:3072; GFX9: ; %bb.0:3073; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3074; GFX9-NEXT: v_mul_u32_u24_e32 v2, v0, v23075; GFX9-NEXT: v_mul_u32_u24_e32 v3, v1, v33076; GFX9-NEXT: v_sub_u32_e32 v0, v2, v03077; GFX9-NEXT: v_sub_u32_e32 v1, v3, v13078; GFX9-NEXT: s_setpc_b64 s[30:31]3079;3080; GFX10-LABEL: v_mul_sub_x_v2i24:3081; GFX10: ; %bb.0:3082; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3083; GFX10-NEXT: v_mul_u32_u24_e32 v2, v0, v23084; GFX10-NEXT: v_mul_u32_u24_e32 v3, v1, v33085; GFX10-NEXT: v_sub_nc_u32_e32 v0, v2, v03086; GFX10-NEXT: v_sub_nc_u32_e32 v1, v3, v13087; GFX10-NEXT: s_setpc_b64 s[30:31]3088;3089; GFX1250-LABEL: v_mul_sub_x_v2i24:3090; GFX1250: ; %bb.0:3091; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03092; GFX1250-NEXT: s_wait_kmcnt 0x03093; GFX1250-NEXT: v_mul_u32_u24_e32 v2, v0, v23094; GFX1250-NEXT: v_mul_u32_u24_e32 v3, v1, v33095; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)3096; GFX1250-NEXT: v_dual_sub_nc_u32 v0, v2, v0 :: v_dual_sub_nc_u32 v1, v3, v13097; GFX1250-NEXT: s_set_pc_i64 s[30:31]3098 %mul = mul <2 x i24> %x, %y3099 %sub = sub <2 x i24> %mul, %x3100 ret <2 x i24> %sub3101}3102 3103define <2 x i24> @v_mul_add_2_v2i24(<2 x i24> %x, <2 x i24> %y) {3104; GFX67-LABEL: v_mul_add_2_v2i24:3105; GFX67: ; %bb.0:3106; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3107; GFX67-NEXT: v_add_i32_e32 v3, vcc, 2, v33108; GFX67-NEXT: v_add_i32_e32 v2, vcc, 2, v23109; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v23110; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v33111; GFX67-NEXT: s_setpc_b64 s[30:31]3112;3113; GFX8-LABEL: v_mul_add_2_v2i24:3114; GFX8: ; %bb.0:3115; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3116; GFX8-NEXT: v_add_u32_e32 v3, vcc, 2, v33117; GFX8-NEXT: v_add_u32_e32 v2, vcc, 2, v23118; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v23119; GFX8-NEXT: v_mul_u32_u24_e32 v1, v1, v33120; GFX8-NEXT: s_setpc_b64 s[30:31]3121;3122; GFX9-LABEL: v_mul_add_2_v2i24:3123; GFX9: ; %bb.0:3124; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3125; GFX9-NEXT: v_add_u32_e32 v3, 2, v33126; GFX9-NEXT: v_add_u32_e32 v2, 2, v23127; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v23128; GFX9-NEXT: v_mul_u32_u24_e32 v1, v1, v33129; GFX9-NEXT: s_setpc_b64 s[30:31]3130;3131; GFX10-LABEL: v_mul_add_2_v2i24:3132; GFX10: ; %bb.0:3133; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3134; GFX10-NEXT: v_add_nc_u32_e32 v2, 2, v23135; GFX10-NEXT: v_add_nc_u32_e32 v3, 2, v33136; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v23137; GFX10-NEXT: v_mul_u32_u24_e32 v1, v1, v33138; GFX10-NEXT: s_setpc_b64 s[30:31]3139;3140; GFX1250-LABEL: v_mul_add_2_v2i24:3141; GFX1250: ; %bb.0:3142; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03143; GFX1250-NEXT: s_wait_kmcnt 0x03144; GFX1250-NEXT: v_dual_add_nc_u32 v2, 2, v2 :: v_dual_add_nc_u32 v3, 2, v33145; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)3146; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v23147; GFX1250-NEXT: v_mul_u32_u24_e32 v1, v1, v33148; GFX1250-NEXT: s_set_pc_i64 s[30:31]3149 %add = add <2 x i24> %y, <i24 2, i24 2>3150 %mul = mul <2 x i24> %x, %add3151 ret <2 x i24> %mul3152}3153 3154define <2 x i24> @v_mul_sub_2_v2i24(<2 x i24> %x, <2 x i24> %y) {3155; GFX67-LABEL: v_mul_sub_2_v2i24:3156; GFX67: ; %bb.0:3157; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3158; GFX67-NEXT: v_add_i32_e32 v3, vcc, -2, v33159; GFX67-NEXT: v_add_i32_e32 v2, vcc, -2, v23160; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v23161; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v33162; GFX67-NEXT: s_setpc_b64 s[30:31]3163;3164; GFX8-LABEL: v_mul_sub_2_v2i24:3165; GFX8: ; %bb.0:3166; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3167; GFX8-NEXT: v_add_u32_e32 v3, vcc, -2, v33168; GFX8-NEXT: v_add_u32_e32 v2, vcc, -2, v23169; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v23170; GFX8-NEXT: v_mul_u32_u24_e32 v1, v1, v33171; GFX8-NEXT: s_setpc_b64 s[30:31]3172;3173; GFX9-LABEL: v_mul_sub_2_v2i24:3174; GFX9: ; %bb.0:3175; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3176; GFX9-NEXT: v_add_u32_e32 v3, -2, v33177; GFX9-NEXT: v_add_u32_e32 v2, -2, v23178; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v23179; GFX9-NEXT: v_mul_u32_u24_e32 v1, v1, v33180; GFX9-NEXT: s_setpc_b64 s[30:31]3181;3182; GFX10-LABEL: v_mul_sub_2_v2i24:3183; GFX10: ; %bb.0:3184; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3185; GFX10-NEXT: v_add_nc_u32_e32 v2, -2, v23186; GFX10-NEXT: v_add_nc_u32_e32 v3, -2, v33187; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v23188; GFX10-NEXT: v_mul_u32_u24_e32 v1, v1, v33189; GFX10-NEXT: s_setpc_b64 s[30:31]3190;3191; GFX1250-LABEL: v_mul_sub_2_v2i24:3192; GFX1250: ; %bb.0:3193; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03194; GFX1250-NEXT: s_wait_kmcnt 0x03195; GFX1250-NEXT: v_dual_add_nc_u32 v2, -2, v2 :: v_dual_add_nc_u32 v3, -2, v33196; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)3197; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v23198; GFX1250-NEXT: v_mul_u32_u24_e32 v1, v1, v33199; GFX1250-NEXT: s_set_pc_i64 s[30:31]3200 %sub = sub <2 x i24> %y, <i24 2, i24 2>3201 %mul = mul <2 x i24> %x, %sub3202 ret <2 x i24> %mul3203}3204 3205define i32 @v_mul_9_add_52_i32(i32 %arg) {3206; GFX67-LABEL: v_mul_9_add_52_i32:3207; GFX67: ; %bb.0:3208; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3209; GFX67-NEXT: v_mul_lo_u32 v0, v0, 93210; GFX67-NEXT: v_add_i32_e32 v0, vcc, 52, v03211; GFX67-NEXT: s_setpc_b64 s[30:31]3212;3213; GFX8-LABEL: v_mul_9_add_52_i32:3214; GFX8: ; %bb.0:3215; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3216; GFX8-NEXT: v_mul_lo_u32 v0, v0, 93217; GFX8-NEXT: v_add_u32_e32 v0, vcc, 52, v03218; GFX8-NEXT: s_setpc_b64 s[30:31]3219;3220; GFX9-LABEL: v_mul_9_add_52_i32:3221; GFX9: ; %bb.0:3222; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3223; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 9, 523224; GFX9-NEXT: s_setpc_b64 s[30:31]3225;3226; GFX10-LABEL: v_mul_9_add_52_i32:3227; GFX10: ; %bb.0:3228; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3229; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 9, 523230; GFX10-NEXT: s_setpc_b64 s[30:31]3231;3232; GFX1250-LABEL: v_mul_9_add_52_i32:3233; GFX1250: ; %bb.0:3234; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03235; GFX1250-NEXT: s_wait_kmcnt 0x03236; GFX1250-NEXT: v_mad_u32 v0, v0, 9, 523237; GFX1250-NEXT: s_set_pc_i64 s[30:31]3238 %mul = mul i32 %arg, 93239 %add = add i32 %mul, 523240 ret i32 %add3241}3242 3243define i16 @v_mul_9_add_52_i16(i16 %arg) {3244; GFX67-LABEL: v_mul_9_add_52_i16:3245; GFX67: ; %bb.0:3246; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3247; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03248; GFX67-NEXT: v_mad_u32_u24 v0, v0, 9, 523249; GFX67-NEXT: s_setpc_b64 s[30:31]3250;3251; GFX8-LABEL: v_mul_9_add_52_i16:3252; GFX8: ; %bb.0:3253; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3254; GFX8-NEXT: v_mad_u16 v0, v0, 9, 523255; GFX8-NEXT: s_setpc_b64 s[30:31]3256;3257; GFX9-LABEL: v_mul_9_add_52_i16:3258; GFX9: ; %bb.0:3259; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3260; GFX9-NEXT: v_mad_legacy_u16 v0, v0, 9, 523261; GFX9-NEXT: s_setpc_b64 s[30:31]3262;3263; GFX10-LABEL: v_mul_9_add_52_i16:3264; GFX10: ; %bb.0:3265; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3266; GFX10-NEXT: v_mad_u16 v0, v0, 9, 523267; GFX10-NEXT: s_setpc_b64 s[30:31]3268;3269; GFX1250-LABEL: v_mul_9_add_52_i16:3270; GFX1250: ; %bb.0:3271; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03272; GFX1250-NEXT: s_wait_kmcnt 0x03273; GFX1250-NEXT: v_mad_u16 v0, v0, 9, 523274; GFX1250-NEXT: s_set_pc_i64 s[30:31]3275 %mul = mul i16 %arg, 93276 %add = add i16 %mul, 523277 ret i16 %add3278}3279 3280define <2 x i16> @v_mul_9_add_52_v2i16(<2 x i16> %arg) {3281; GFX67-LABEL: v_mul_9_add_52_v2i16:3282; GFX67: ; %bb.0:3283; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3284; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03285; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v13286; GFX67-NEXT: v_mad_u32_u24 v1, v1, 9, 523287; GFX67-NEXT: v_mad_u32_u24 v0, v0, 9, 523288; GFX67-NEXT: v_lshlrev_b32_e32 v2, 16, v13289; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03290; GFX67-NEXT: v_or_b32_e32 v0, v0, v23291; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v13292; GFX67-NEXT: s_setpc_b64 s[30:31]3293;3294; GFX8-LABEL: v_mul_9_add_52_v2i16:3295; GFX8: ; %bb.0:3296; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3297; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v03298; GFX8-NEXT: v_mad_u16 v1, v1, 9, 523299; GFX8-NEXT: v_mad_u16 v0, v0, 9, 523300; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v13301; GFX8-NEXT: v_or_b32_e32 v0, v0, v13302; GFX8-NEXT: s_setpc_b64 s[30:31]3303;3304; GFX9-LABEL: v_mul_9_add_52_v2i16:3305; GFX9: ; %bb.0:3306; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3307; GFX9-NEXT: v_pk_mad_u16 v0, v0, 9, 52 op_sel_hi:[1,0,0]3308; GFX9-NEXT: s_setpc_b64 s[30:31]3309;3310; GFX10-LABEL: v_mul_9_add_52_v2i16:3311; GFX10: ; %bb.0:3312; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3313; GFX10-NEXT: v_pk_mad_u16 v0, v0, 9, 52 op_sel_hi:[1,0,0]3314; GFX10-NEXT: s_setpc_b64 s[30:31]3315;3316; GFX1250-LABEL: v_mul_9_add_52_v2i16:3317; GFX1250: ; %bb.0:3318; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03319; GFX1250-NEXT: s_wait_kmcnt 0x03320; GFX1250-NEXT: v_pk_mad_u16 v0, v0, 9, 52 op_sel_hi:[1,0,0]3321; GFX1250-NEXT: s_set_pc_i64 s[30:31]3322 %mul = mul <2 x i16> %arg, <i16 9, i16 9>3323 %add = add <2 x i16> %mul, <i16 52, i16 52>3324 ret <2 x i16> %add3325}3326 3327define i64 @v_mul_9_add_52_i64(i64 %arg) {3328; GFX6-LABEL: v_mul_9_add_52_i64:3329; GFX6: ; %bb.0:3330; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3331; GFX6-NEXT: v_mul_lo_u32 v1, v1, 93332; GFX6-NEXT: v_mul_hi_u32 v2, v0, 93333; GFX6-NEXT: v_mul_lo_u32 v0, v0, 93334; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v13335; GFX6-NEXT: v_add_i32_e32 v0, vcc, 52, v03336; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3337; GFX6-NEXT: s_setpc_b64 s[30:31]3338;3339; GFX7-LABEL: v_mul_9_add_52_i64:3340; GFX7: ; %bb.0:3341; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3342; GFX7-NEXT: v_mul_lo_u32 v2, v1, 93343; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 9, 523344; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v13345; GFX7-NEXT: s_setpc_b64 s[30:31]3346;3347; GFX8-LABEL: v_mul_9_add_52_i64:3348; GFX8: ; %bb.0:3349; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3350; GFX8-NEXT: v_mul_lo_u32 v2, v1, 93351; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 9, 523352; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v13353; GFX8-NEXT: s_setpc_b64 s[30:31]3354;3355; GFX900-LABEL: v_mul_9_add_52_i64:3356; GFX900: ; %bb.0:3357; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3358; GFX900-NEXT: v_mov_b32_e32 v2, v13359; GFX900-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 9, 523360; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, 9, v[1:2]3361; GFX900-NEXT: s_setpc_b64 s[30:31]3362;3363; GFX90A-LABEL: v_mul_9_add_52_i64:3364; GFX90A: ; %bb.0:3365; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3366; GFX90A-NEXT: v_mov_b32_e32 v2, v13367; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 9, 523368; GFX90A-NEXT: v_mov_b32_e32 v4, v13369; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 9, v[4:5]3370; GFX90A-NEXT: v_mov_b32_e32 v1, v23371; GFX90A-NEXT: s_setpc_b64 s[30:31]3372;3373; GFX10-LABEL: v_mul_9_add_52_i64:3374; GFX10: ; %bb.0:3375; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3376; GFX10-NEXT: v_mov_b32_e32 v2, v13377; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 9, 523378; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, v2, 9, v[1:2]3379; GFX10-NEXT: s_setpc_b64 s[30:31]3380;3381; GFX1250-LABEL: v_mul_9_add_52_i64:3382; GFX1250: ; %bb.0:3383; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03384; GFX1250-NEXT: s_wait_kmcnt 0x03385; GFX1250-NEXT: v_mov_b32_e32 v2, v13386; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, 9, 523387; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)3388; GFX1250-NEXT: v_mad_u32 v1, v2, 9, v13389; GFX1250-NEXT: s_set_pc_i64 s[30:31]3390 %mul = mul i64 %arg, 93391 %add = add i64 %mul, 523392 ret i64 %add3393}3394 3395define i32 @v_mul_5_add_1_i32(i32 %arg) {3396; GFX67-LABEL: v_mul_5_add_1_i32:3397; GFX67: ; %bb.0:3398; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3399; GFX67-NEXT: v_mul_lo_u32 v0, v0, 53400; GFX67-NEXT: v_add_i32_e32 v0, vcc, 1, v03401; GFX67-NEXT: s_setpc_b64 s[30:31]3402;3403; GFX8-LABEL: v_mul_5_add_1_i32:3404; GFX8: ; %bb.0:3405; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3406; GFX8-NEXT: v_mul_lo_u32 v0, v0, 53407; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v03408; GFX8-NEXT: s_setpc_b64 s[30:31]3409;3410; GFX9-LABEL: v_mul_5_add_1_i32:3411; GFX9: ; %bb.0:3412; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3413; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 5, 13414; GFX9-NEXT: s_setpc_b64 s[30:31]3415;3416; GFX10-LABEL: v_mul_5_add_1_i32:3417; GFX10: ; %bb.0:3418; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3419; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 5, 13420; GFX10-NEXT: s_setpc_b64 s[30:31]3421;3422; GFX1250-LABEL: v_mul_5_add_1_i32:3423; GFX1250: ; %bb.0:3424; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03425; GFX1250-NEXT: s_wait_kmcnt 0x03426; GFX1250-NEXT: v_mad_u32 v0, v0, 5, 13427; GFX1250-NEXT: s_set_pc_i64 s[30:31]3428 %mul = mul i32 %arg, 53429 %add = add i32 %mul, 13430 ret i32 %add3431}3432 3433define i32 @v_mul_284_add_82_i32(i32 %arg) {3434; GFX67-LABEL: v_mul_284_add_82_i32:3435; GFX67: ; %bb.0:3436; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3437; GFX67-NEXT: s_movk_i32 s4, 0x11c3438; GFX67-NEXT: v_mul_lo_u32 v0, v0, s43439; GFX67-NEXT: v_add_i32_e32 v0, vcc, 0x52, v03440; GFX67-NEXT: s_setpc_b64 s[30:31]3441;3442; GFX8-LABEL: v_mul_284_add_82_i32:3443; GFX8: ; %bb.0:3444; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3445; GFX8-NEXT: s_movk_i32 s4, 0x11c3446; GFX8-NEXT: v_mul_lo_u32 v0, v0, s43447; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0x52, v03448; GFX8-NEXT: s_setpc_b64 s[30:31]3449;3450; GFX9-LABEL: v_mul_284_add_82_i32:3451; GFX9: ; %bb.0:3452; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3453; GFX9-NEXT: s_movk_i32 s4, 0x11c3454; GFX9-NEXT: v_mul_lo_u32 v0, v0, s43455; GFX9-NEXT: v_add_u32_e32 v0, 0x52, v03456; GFX9-NEXT: s_setpc_b64 s[30:31]3457;3458; GFX10-LABEL: v_mul_284_add_82_i32:3459; GFX10: ; %bb.0:3460; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3461; GFX10-NEXT: s_movk_i32 s4, 0x11c3462; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s4, 0x523463; GFX10-NEXT: s_setpc_b64 s[30:31]3464;3465; GFX1250-LABEL: v_mul_284_add_82_i32:3466; GFX1250: ; %bb.0:3467; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03468; GFX1250-NEXT: s_wait_kmcnt 0x03469; GFX1250-NEXT: s_movk_i32 s0, 0x11c3470; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3471; GFX1250-NEXT: v_mad_u32 v0, v0, s0, 0x523472; GFX1250-NEXT: s_set_pc_i64 s[30:31]3473 %mul = mul i32 %arg, 2843474 %add = add i32 %mul, 823475 ret i32 %add3476}3477 3478define i16 @v_mul_5_add_1_i16(i16 %arg) {3479; GFX67-LABEL: v_mul_5_add_1_i16:3480; GFX67: ; %bb.0:3481; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3482; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03483; GFX67-NEXT: v_mad_u32_u24 v0, v0, 5, 13484; GFX67-NEXT: s_setpc_b64 s[30:31]3485;3486; GFX8-LABEL: v_mul_5_add_1_i16:3487; GFX8: ; %bb.0:3488; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3489; GFX8-NEXT: v_mad_u16 v0, v0, 5, 13490; GFX8-NEXT: s_setpc_b64 s[30:31]3491;3492; GFX9-LABEL: v_mul_5_add_1_i16:3493; GFX9: ; %bb.0:3494; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3495; GFX9-NEXT: v_mad_legacy_u16 v0, v0, 5, 13496; GFX9-NEXT: s_setpc_b64 s[30:31]3497;3498; GFX10-LABEL: v_mul_5_add_1_i16:3499; GFX10: ; %bb.0:3500; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3501; GFX10-NEXT: v_mad_u16 v0, v0, 5, 13502; GFX10-NEXT: s_setpc_b64 s[30:31]3503;3504; GFX1250-LABEL: v_mul_5_add_1_i16:3505; GFX1250: ; %bb.0:3506; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03507; GFX1250-NEXT: s_wait_kmcnt 0x03508; GFX1250-NEXT: v_mad_u16 v0, v0, 5, 13509; GFX1250-NEXT: s_set_pc_i64 s[30:31]3510 %mul = mul i16 %arg, 53511 %add = add i16 %mul, 13512 ret i16 %add3513}3514 3515define i16 @v_mul_284_add_82_i16(i16 %arg) {3516; GFX67-LABEL: v_mul_284_add_82_i16:3517; GFX67: ; %bb.0:3518; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3519; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03520; GFX67-NEXT: s_movk_i32 s4, 0x11c3521; GFX67-NEXT: v_mov_b32_e32 v1, 0x523522; GFX67-NEXT: v_mad_u32_u24 v0, v0, s4, v13523; GFX67-NEXT: s_setpc_b64 s[30:31]3524;3525; GFX8-LABEL: v_mul_284_add_82_i16:3526; GFX8: ; %bb.0:3527; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3528; GFX8-NEXT: s_movk_i32 s4, 0x11c3529; GFX8-NEXT: v_mov_b32_e32 v1, 0x523530; GFX8-NEXT: v_mad_u16 v0, v0, s4, v13531; GFX8-NEXT: s_setpc_b64 s[30:31]3532;3533; GFX9-LABEL: v_mul_284_add_82_i16:3534; GFX9: ; %bb.0:3535; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3536; GFX9-NEXT: s_movk_i32 s4, 0x11c3537; GFX9-NEXT: v_mov_b32_e32 v1, 0x523538; GFX9-NEXT: v_mad_legacy_u16 v0, v0, s4, v13539; GFX9-NEXT: s_setpc_b64 s[30:31]3540;3541; GFX10-LABEL: v_mul_284_add_82_i16:3542; GFX10: ; %bb.0:3543; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3544; GFX10-NEXT: s_movk_i32 s4, 0x11c3545; GFX10-NEXT: v_mad_u16 v0, v0, s4, 0x523546; GFX10-NEXT: s_setpc_b64 s[30:31]3547;3548; GFX1250-LABEL: v_mul_284_add_82_i16:3549; GFX1250: ; %bb.0:3550; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03551; GFX1250-NEXT: s_wait_kmcnt 0x03552; GFX1250-NEXT: s_movk_i32 s0, 0x11c3553; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3554; GFX1250-NEXT: v_mad_u16 v0, v0, s0, 0x523555; GFX1250-NEXT: s_set_pc_i64 s[30:31]3556 %mul = mul i16 %arg, 2843557 %add = add i16 %mul, 823558 ret i16 %add3559}3560 3561define <2 x i16> @v_mul_5_add_1_v2i16(<2 x i16> %arg) {3562; GFX67-LABEL: v_mul_5_add_1_v2i16:3563; GFX67: ; %bb.0:3564; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3565; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03566; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v13567; GFX67-NEXT: v_mad_u32_u24 v1, v1, 5, 13568; GFX67-NEXT: v_mad_u32_u24 v0, v0, 5, 13569; GFX67-NEXT: v_lshlrev_b32_e32 v2, 16, v13570; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03571; GFX67-NEXT: v_or_b32_e32 v0, v0, v23572; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v13573; GFX67-NEXT: s_setpc_b64 s[30:31]3574;3575; GFX8-LABEL: v_mul_5_add_1_v2i16:3576; GFX8: ; %bb.0:3577; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3578; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v03579; GFX8-NEXT: v_mad_u16 v1, v1, 5, 13580; GFX8-NEXT: v_mad_u16 v0, v0, 5, 13581; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v13582; GFX8-NEXT: v_or_b32_e32 v0, v0, v13583; GFX8-NEXT: s_setpc_b64 s[30:31]3584;3585; GFX9-LABEL: v_mul_5_add_1_v2i16:3586; GFX9: ; %bb.0:3587; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3588; GFX9-NEXT: v_pk_mad_u16 v0, v0, 5, 1 op_sel_hi:[1,0,0]3589; GFX9-NEXT: s_setpc_b64 s[30:31]3590;3591; GFX10-LABEL: v_mul_5_add_1_v2i16:3592; GFX10: ; %bb.0:3593; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3594; GFX10-NEXT: v_pk_mad_u16 v0, v0, 5, 1 op_sel_hi:[1,0,0]3595; GFX10-NEXT: s_setpc_b64 s[30:31]3596;3597; GFX1250-LABEL: v_mul_5_add_1_v2i16:3598; GFX1250: ; %bb.0:3599; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03600; GFX1250-NEXT: s_wait_kmcnt 0x03601; GFX1250-NEXT: v_pk_mad_u16 v0, v0, 5, 1 op_sel_hi:[1,0,0]3602; GFX1250-NEXT: s_set_pc_i64 s[30:31]3603 %mul = mul <2 x i16> %arg, <i16 5, i16 5>3604 %add = add <2 x i16> %mul, <i16 1, i16 1>3605 ret <2 x i16> %add3606}3607 3608define <2 x i16> @v_mul_284_add_82_v2i16(<2 x i16> %arg) {3609; GFX67-LABEL: v_mul_284_add_82_v2i16:3610; GFX67: ; %bb.0:3611; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3612; GFX67-NEXT: v_and_b32_e32 v0, 0xffff, v03613; GFX67-NEXT: v_and_b32_e32 v1, 0xffff, v13614; GFX67-NEXT: s_movk_i32 s4, 0x11c3615; GFX67-NEXT: v_mov_b32_e32 v2, 0x523616; GFX67-NEXT: v_mad_u32_u24 v1, v1, s4, v23617; GFX67-NEXT: v_mad_u32_u24 v0, v0, s4, v23618; GFX67-NEXT: v_lshlrev_b32_e32 v3, 16, v13619; GFX67-NEXT: v_and_b32_e32 v0, 0xfffe, v03620; GFX67-NEXT: v_or_b32_e32 v0, v0, v33621; GFX67-NEXT: v_and_b32_e32 v1, 0xfffe, v13622; GFX67-NEXT: s_setpc_b64 s[30:31]3623;3624; GFX8-LABEL: v_mul_284_add_82_v2i16:3625; GFX8: ; %bb.0:3626; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3627; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v03628; GFX8-NEXT: s_movk_i32 s4, 0x11c3629; GFX8-NEXT: v_mov_b32_e32 v2, 0x523630; GFX8-NEXT: v_mad_u16 v1, v1, s4, v23631; GFX8-NEXT: v_mad_u16 v0, v0, s4, v23632; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v13633; GFX8-NEXT: v_or_b32_e32 v0, v0, v13634; GFX8-NEXT: s_setpc_b64 s[30:31]3635;3636; GFX9-LABEL: v_mul_284_add_82_v2i16:3637; GFX9: ; %bb.0:3638; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3639; GFX9-NEXT: s_movk_i32 s4, 0x11c3640; GFX9-NEXT: v_mov_b32_e32 v1, 0x523641; GFX9-NEXT: v_pk_mad_u16 v0, v0, s4, v1 op_sel_hi:[1,0,0]3642; GFX9-NEXT: s_setpc_b64 s[30:31]3643;3644; GFX10-LABEL: v_mul_284_add_82_v2i16:3645; GFX10: ; %bb.0:3646; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3647; GFX10-NEXT: s_movk_i32 s4, 0x11c3648; GFX10-NEXT: v_pk_mad_u16 v0, v0, s4, 0x52 op_sel_hi:[1,0,0]3649; GFX10-NEXT: s_setpc_b64 s[30:31]3650;3651; GFX1250-LABEL: v_mul_284_add_82_v2i16:3652; GFX1250: ; %bb.0:3653; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03654; GFX1250-NEXT: s_wait_kmcnt 0x03655; GFX1250-NEXT: s_movk_i32 s0, 0x11c3656; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3657; GFX1250-NEXT: v_pk_mad_u16 v0, v0, s0, 0x52 op_sel_hi:[1,0,0]3658; GFX1250-NEXT: s_set_pc_i64 s[30:31]3659 %mul = mul <2 x i16> %arg, <i16 284, i16 284>3660 %add = add <2 x i16> %mul, <i16 82, i16 82>3661 ret <2 x i16> %add3662}3663 3664define i64 @v_mul_5_add_1_i64(i64 %arg) {3665; GFX6-LABEL: v_mul_5_add_1_i64:3666; GFX6: ; %bb.0:3667; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3668; GFX6-NEXT: v_mul_lo_u32 v1, v1, 53669; GFX6-NEXT: v_mul_hi_u32 v2, v0, 53670; GFX6-NEXT: v_mul_lo_u32 v0, v0, 53671; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v13672; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v03673; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3674; GFX6-NEXT: s_setpc_b64 s[30:31]3675;3676; GFX7-LABEL: v_mul_5_add_1_i64:3677; GFX7: ; %bb.0:3678; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3679; GFX7-NEXT: v_mul_lo_u32 v2, v1, 53680; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 5, 13681; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v13682; GFX7-NEXT: s_setpc_b64 s[30:31]3683;3684; GFX8-LABEL: v_mul_5_add_1_i64:3685; GFX8: ; %bb.0:3686; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3687; GFX8-NEXT: v_mul_lo_u32 v2, v1, 53688; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 5, 13689; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v13690; GFX8-NEXT: s_setpc_b64 s[30:31]3691;3692; GFX900-LABEL: v_mul_5_add_1_i64:3693; GFX900: ; %bb.0:3694; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3695; GFX900-NEXT: v_mov_b32_e32 v2, v13696; GFX900-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 5, 13697; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, 5, v[1:2]3698; GFX900-NEXT: s_setpc_b64 s[30:31]3699;3700; GFX90A-LABEL: v_mul_5_add_1_i64:3701; GFX90A: ; %bb.0:3702; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3703; GFX90A-NEXT: v_mov_b32_e32 v2, v13704; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, 5, 13705; GFX90A-NEXT: v_mov_b32_e32 v4, v13706; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 5, v[4:5]3707; GFX90A-NEXT: v_mov_b32_e32 v1, v23708; GFX90A-NEXT: s_setpc_b64 s[30:31]3709;3710; GFX10-LABEL: v_mul_5_add_1_i64:3711; GFX10: ; %bb.0:3712; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3713; GFX10-NEXT: v_mov_b32_e32 v2, v13714; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 5, 13715; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, v2, 5, v[1:2]3716; GFX10-NEXT: s_setpc_b64 s[30:31]3717;3718; GFX1250-LABEL: v_mul_5_add_1_i64:3719; GFX1250: ; %bb.0:3720; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03721; GFX1250-NEXT: s_wait_kmcnt 0x03722; GFX1250-NEXT: v_mov_b32_e32 v2, v13723; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, 5, 13724; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)3725; GFX1250-NEXT: v_mad_u32 v1, v2, 5, v13726; GFX1250-NEXT: s_set_pc_i64 s[30:31]3727 %mul = mul i64 %arg, 53728 %add = add i64 %mul, 13729 ret i64 %add3730}3731 3732define i64 @v_mul_284_add_82_i64(i64 %arg) {3733; GFX6-LABEL: v_mul_284_add_82_i64:3734; GFX6: ; %bb.0:3735; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3736; GFX6-NEXT: s_movk_i32 s4, 0x11c3737; GFX6-NEXT: v_mul_lo_u32 v1, v1, s43738; GFX6-NEXT: v_mul_hi_u32 v2, v0, s43739; GFX6-NEXT: v_mul_lo_u32 v0, v0, s43740; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v13741; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0x52, v03742; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3743; GFX6-NEXT: s_setpc_b64 s[30:31]3744;3745; GFX7-LABEL: v_mul_284_add_82_i64:3746; GFX7: ; %bb.0:3747; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3748; GFX7-NEXT: s_movk_i32 s4, 0x11c3749; GFX7-NEXT: v_mul_lo_u32 v3, v1, s43750; GFX7-NEXT: v_mov_b32_e32 v1, 0x523751; GFX7-NEXT: v_mov_b32_e32 v2, 03752; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s4, v[1:2]3753; GFX7-NEXT: v_add_i32_e32 v1, vcc, v3, v13754; GFX7-NEXT: s_setpc_b64 s[30:31]3755;3756; GFX8-LABEL: v_mul_284_add_82_i64:3757; GFX8: ; %bb.0:3758; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3759; GFX8-NEXT: s_movk_i32 s4, 0x11c3760; GFX8-NEXT: v_mul_lo_u32 v3, v1, s43761; GFX8-NEXT: v_mov_b32_e32 v1, 0x523762; GFX8-NEXT: v_mov_b32_e32 v2, 03763; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s4, v[1:2]3764; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v13765; GFX8-NEXT: s_setpc_b64 s[30:31]3766;3767; GFX900-LABEL: v_mul_284_add_82_i64:3768; GFX900: ; %bb.0:3769; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3770; GFX900-NEXT: v_mov_b32_e32 v3, 0x523771; GFX900-NEXT: s_movk_i32 s6, 0x11c3772; GFX900-NEXT: v_mov_b32_e32 v4, 03773; GFX900-NEXT: v_mov_b32_e32 v2, v13774; GFX900-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[3:4]3775; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, s6, v[1:2]3776; GFX900-NEXT: s_setpc_b64 s[30:31]3777;3778; GFX90A-LABEL: v_mul_284_add_82_i64:3779; GFX90A: ; %bb.0:3780; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3781; GFX90A-NEXT: v_mov_b32_e32 v4, 0x523782; GFX90A-NEXT: s_movk_i32 s6, 0x11c3783; GFX90A-NEXT: v_mov_b32_e32 v5, 03784; GFX90A-NEXT: v_mov_b32_e32 v2, v13785; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[4:5]3786; GFX90A-NEXT: v_mov_b32_e32 v4, v13787; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, s6, v[4:5]3788; GFX90A-NEXT: v_mov_b32_e32 v1, v23789; GFX90A-NEXT: s_setpc_b64 s[30:31]3790;3791; GFX10-LABEL: v_mul_284_add_82_i64:3792; GFX10: ; %bb.0:3793; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3794; GFX10-NEXT: s_movk_i32 s4, 0x11c3795; GFX10-NEXT: v_mov_b32_e32 v2, v13796; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s4, 0x523797; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, 0x11c, v2, v[1:2]3798; GFX10-NEXT: s_setpc_b64 s[30:31]3799;3800; GFX1250-LABEL: v_mul_284_add_82_i64:3801; GFX1250: ; %bb.0:3802; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03803; GFX1250-NEXT: s_wait_kmcnt 0x03804; GFX1250-NEXT: s_movk_i32 s0, 0x11c3805; GFX1250-NEXT: v_mov_b32_e32 v2, v13806; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, s0, 0x523807; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)3808; GFX1250-NEXT: v_mad_u32 v1, 0x11c, v2, v13809; GFX1250-NEXT: s_set_pc_i64 s[30:31]3810 %mul = mul i64 %arg, 2843811 %add = add i64 %mul, 823812 ret i64 %add3813}3814 3815define i64 @v_mul_934584645_add_8234599_i64(i64 %arg) {3816; GFX6-LABEL: v_mul_934584645_add_8234599_i64:3817; GFX6: ; %bb.0:3818; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3819; GFX6-NEXT: s_mov_b32 s4, 0x37b4a1453820; GFX6-NEXT: v_mul_lo_u32 v1, v1, s43821; GFX6-NEXT: v_mul_hi_u32 v2, v0, s43822; GFX6-NEXT: v_mul_lo_u32 v0, v0, s43823; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v13824; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0x7da667, v03825; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc3826; GFX6-NEXT: s_setpc_b64 s[30:31]3827;3828; GFX7-LABEL: v_mul_934584645_add_8234599_i64:3829; GFX7: ; %bb.0:3830; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3831; GFX7-NEXT: s_mov_b32 s4, 0x37b4a1453832; GFX7-NEXT: v_mul_lo_u32 v3, v1, s43833; GFX7-NEXT: v_mov_b32_e32 v1, 0x7da6673834; GFX7-NEXT: v_mov_b32_e32 v2, 03835; GFX7-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s4, v[1:2]3836; GFX7-NEXT: v_add_i32_e32 v1, vcc, v3, v13837; GFX7-NEXT: s_setpc_b64 s[30:31]3838;3839; GFX8-LABEL: v_mul_934584645_add_8234599_i64:3840; GFX8: ; %bb.0:3841; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3842; GFX8-NEXT: s_mov_b32 s4, 0x37b4a1453843; GFX8-NEXT: v_mul_lo_u32 v3, v1, s43844; GFX8-NEXT: v_mov_b32_e32 v1, 0x7da6673845; GFX8-NEXT: v_mov_b32_e32 v2, 03846; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s4, v[1:2]3847; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v13848; GFX8-NEXT: s_setpc_b64 s[30:31]3849;3850; GFX900-LABEL: v_mul_934584645_add_8234599_i64:3851; GFX900: ; %bb.0:3852; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3853; GFX900-NEXT: v_mov_b32_e32 v3, 0x7da6673854; GFX900-NEXT: s_mov_b32 s6, 0x37b4a1453855; GFX900-NEXT: v_mov_b32_e32 v4, 03856; GFX900-NEXT: v_mov_b32_e32 v2, v13857; GFX900-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[3:4]3858; GFX900-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v2, s6, v[1:2]3859; GFX900-NEXT: s_setpc_b64 s[30:31]3860;3861; GFX90A-LABEL: v_mul_934584645_add_8234599_i64:3862; GFX90A: ; %bb.0:3863; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3864; GFX90A-NEXT: v_mov_b32_e32 v4, 0x7da6673865; GFX90A-NEXT: s_mov_b32 s6, 0x37b4a1453866; GFX90A-NEXT: v_mov_b32_e32 v5, 03867; GFX90A-NEXT: v_mov_b32_e32 v2, v13868; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[4:5]3869; GFX90A-NEXT: v_mov_b32_e32 v4, v13870; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, s6, v[4:5]3871; GFX90A-NEXT: v_mov_b32_e32 v1, v23872; GFX90A-NEXT: s_setpc_b64 s[30:31]3873;3874; GFX10-LABEL: v_mul_934584645_add_8234599_i64:3875; GFX10: ; %bb.0:3876; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3877; GFX10-NEXT: s_mov_b32 s4, 0x37b4a1453878; GFX10-NEXT: v_mov_b32_e32 v2, v13879; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s4, 0x7da6673880; GFX10-NEXT: v_mad_u64_u32 v[1:2], null, 0x37b4a145, v2, v[1:2]3881; GFX10-NEXT: s_setpc_b64 s[30:31]3882;3883; GFX1250-LABEL: v_mul_934584645_add_8234599_i64:3884; GFX1250: ; %bb.0:3885; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x03886; GFX1250-NEXT: s_wait_kmcnt 0x03887; GFX1250-NEXT: s_mov_b32 s0, 0x37b4a1453888; GFX1250-NEXT: v_mov_b32_e32 v2, v13889; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, s0, 0x7da6673890; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)3891; GFX1250-NEXT: v_mad_u32 v1, 0x37b4a145, v2, v13892; GFX1250-NEXT: s_set_pc_i64 s[30:31]3893 %mul = mul i64 %arg, 9345846453894 %add = add i64 %mul, 82345993895 ret i64 %add3896}3897 3898define amdgpu_kernel void @compute_mad(ptr addrspace(4) %i18, ptr addrspace(4) %i21, ptr addrspace(1) nocapture noundef writeonly align 4 %arg, i32 noundef %arg1) #1 {3899; GFX67-LABEL: compute_mad:3900; GFX67: ; %bb.0: ; %bb3901; GFX67-NEXT: s_load_dword s0, s[4:5], 0x63902; GFX67-NEXT: s_mov_b32 s3, 0xf0003903; GFX67-NEXT: s_waitcnt lgkmcnt(0)3904; GFX67-NEXT: s_add_i32 s0, s0, 13905; GFX67-NEXT: v_mul_lo_u32 v1, s0, v03906; GFX67-NEXT: v_add_i32_e32 v2, vcc, s0, v13907; GFX67-NEXT: v_mul_lo_u32 v2, v2, v03908; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v13909; GFX67-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x03910; GFX67-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x43911; GFX67-NEXT: v_mul_lo_u32 v3, v2, v13912; GFX67-NEXT: s_waitcnt lgkmcnt(0)3913; GFX67-NEXT: s_load_dword s2, s[14:15], 0x13914; GFX67-NEXT: s_load_dwordx2 s[4:5], s[12:13], 0x03915; GFX67-NEXT: v_add_i32_e32 v1, vcc, v3, v13916; GFX67-NEXT: v_mul_lo_u32 v1, v1, v23917; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v33918; GFX67-NEXT: s_waitcnt lgkmcnt(0)3919; GFX67-NEXT: s_and_b32 s2, s2, 0xffff3920; GFX67-NEXT: v_mul_lo_u32 v3, v1, v23921; GFX67-NEXT: s_mul_i32 s8, s8, s23922; GFX67-NEXT: v_add_i32_e32 v0, vcc, s8, v03923; GFX67-NEXT: v_add_i32_e32 v2, vcc, v3, v23924; GFX67-NEXT: v_mul_lo_u32 v1, v2, v13925; GFX67-NEXT: v_mov_b32_e32 v2, s53926; GFX67-NEXT: s_mov_b32 s2, 03927; GFX67-NEXT: v_mul_lo_u32 v3, v1, v33928; GFX67-NEXT: v_add_i32_e32 v3, vcc, v3, v13929; GFX67-NEXT: v_mul_lo_u32 v4, v3, v13930; GFX67-NEXT: v_add_i32_e32 v0, vcc, s4, v03931; GFX67-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc3932; GFX67-NEXT: v_lshl_b64 v[0:1], v[0:1], 23933; GFX67-NEXT: v_add_i32_e32 v2, vcc, v4, v33934; GFX67-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr643935; GFX67-NEXT: s_endpgm3936;3937; GFX8-LABEL: compute_mad:3938; GFX8: ; %bb.0: ; %bb3939; GFX8-NEXT: s_load_dword s0, s[4:5], 0x183940; GFX8-NEXT: s_waitcnt lgkmcnt(0)3941; GFX8-NEXT: s_add_i32 s0, s0, 13942; GFX8-NEXT: v_mul_lo_u32 v1, s0, v03943; GFX8-NEXT: v_add_u32_e32 v2, vcc, s0, v13944; GFX8-NEXT: v_mul_lo_u32 v2, v2, v03945; GFX8-NEXT: v_add_u32_e32 v1, vcc, 1, v13946; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x03947; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x103948; GFX8-NEXT: v_mul_lo_u32 v3, v2, v13949; GFX8-NEXT: s_waitcnt lgkmcnt(0)3950; GFX8-NEXT: s_load_dword s2, s[2:3], 0x43951; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v13952; GFX8-NEXT: v_mul_lo_u32 v1, v1, v23953; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v33954; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x03955; GFX8-NEXT: v_mul_lo_u32 v3, v1, v23956; GFX8-NEXT: s_waitcnt lgkmcnt(0)3957; GFX8-NEXT: s_and_b32 s2, s2, 0xffff3958; GFX8-NEXT: s_mul_i32 s8, s8, s23959; GFX8-NEXT: v_add_u32_e32 v0, vcc, s8, v03960; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v23961; GFX8-NEXT: v_mul_lo_u32 v1, v2, v13962; GFX8-NEXT: v_mov_b32_e32 v2, s13963; GFX8-NEXT: v_mov_b32_e32 v4, s53964; GFX8-NEXT: v_mul_lo_u32 v3, v1, v33965; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v13966; GFX8-NEXT: v_mul_lo_u32 v5, v3, v13967; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v03968; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc3969; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]3970; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v33971; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v03972; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc3973; GFX8-NEXT: flat_store_dword v[0:1], v23974; GFX8-NEXT: s_endpgm3975;3976; GFX900-LABEL: compute_mad:3977; GFX900: ; %bb.0: ; %bb3978; GFX900-NEXT: s_load_dword s0, s[4:5], 0x183979; GFX900-NEXT: s_waitcnt lgkmcnt(0)3980; GFX900-NEXT: s_add_i32 s0, s0, 13981; GFX900-NEXT: v_mul_lo_u32 v1, s0, v03982; GFX900-NEXT: v_add_u32_e32 v2, s0, v13983; GFX900-NEXT: v_mul_lo_u32 v2, v2, v03984; GFX900-NEXT: v_add_u32_e32 v1, 1, v13985; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x03986; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x103987; GFX900-NEXT: s_waitcnt lgkmcnt(0)3988; GFX900-NEXT: s_load_dword s9, s[2:3], 0x43989; GFX900-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x03990; GFX900-NEXT: v_mul_lo_u32 v3, v2, v13991; GFX900-NEXT: v_mov_b32_e32 v5, s73992; GFX900-NEXT: s_waitcnt lgkmcnt(0)3993; GFX900-NEXT: s_and_b32 s0, s9, 0xffff3994; GFX900-NEXT: v_add_u32_e32 v1, v3, v13995; GFX900-NEXT: v_mul_lo_u32 v1, v1, v23996; GFX900-NEXT: v_add_u32_e32 v2, 1, v33997; GFX900-NEXT: s_mul_i32 s8, s8, s03998; GFX900-NEXT: v_add_u32_e32 v0, s8, v03999; GFX900-NEXT: v_mul_lo_u32 v3, v1, v24000; GFX900-NEXT: v_mov_b32_e32 v4, s54001; GFX900-NEXT: v_add_u32_e32 v2, v3, v24002; GFX900-NEXT: v_mul_lo_u32 v1, v2, v14003; GFX900-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, v3, v[1:2]4004; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, s4, v04005; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc4006; GFX900-NEXT: v_lshlrev_b64 v[3:4], 2, v[3:4]4007; GFX900-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v1, v[2:3]4008; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s6, v34009; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc4010; GFX900-NEXT: global_store_dword v[1:2], v0, off4011; GFX900-NEXT: s_endpgm4012;4013; GFX90A-LABEL: compute_mad:4014; GFX90A: ; %bb.0: ; %bb4015; GFX90A-NEXT: s_load_dword s9, s[4:5], 0x184016; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x04017; GFX90A-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x104018; GFX90A-NEXT: v_and_b32_e32 v4, 0x3ff, v04019; GFX90A-NEXT: s_waitcnt lgkmcnt(0)4020; GFX90A-NEXT: s_add_i32 s9, s9, 14021; GFX90A-NEXT: v_mul_lo_u32 v0, s9, v44022; GFX90A-NEXT: v_add_u32_e32 v1, s9, v04023; GFX90A-NEXT: v_mul_lo_u32 v1, v1, v44024; GFX90A-NEXT: v_add_u32_e32 v0, 1, v04025; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v04026; GFX90A-NEXT: v_add_u32_e32 v0, v2, v04027; GFX90A-NEXT: v_mul_lo_u32 v0, v0, v14028; GFX90A-NEXT: v_add_u32_e32 v1, 1, v24029; GFX90A-NEXT: v_mul_lo_u32 v2, v0, v14030; GFX90A-NEXT: s_load_dword s4, s[2:3], 0x44031; GFX90A-NEXT: v_add_u32_e32 v1, v2, v14032; GFX90A-NEXT: v_mul_lo_u32 v0, v1, v04033; GFX90A-NEXT: v_mad_u64_u32 v[2:3], s[2:3], v0, v2, v[0:1]4034; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x04035; GFX90A-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v2, v0, v[2:3]4036; GFX90A-NEXT: s_waitcnt lgkmcnt(0)4037; GFX90A-NEXT: s_and_b32 s2, s4, 0xffff4038; GFX90A-NEXT: s_mul_i32 s8, s8, s24039; GFX90A-NEXT: v_add_u32_e32 v1, s8, v44040; GFX90A-NEXT: v_mov_b32_e32 v3, s14041; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s0, v14042; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc4043; GFX90A-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]4044; GFX90A-NEXT: v_mov_b32_e32 v1, s74045; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, s6, v24046; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc4047; GFX90A-NEXT: global_store_dword v[2:3], v0, off4048; GFX90A-NEXT: s_endpgm4049;4050; GFX10-LABEL: compute_mad:4051; GFX10: ; %bb.0: ; %bb4052; GFX10-NEXT: s_load_dword s0, s[4:5], 0x184053; GFX10-NEXT: s_waitcnt lgkmcnt(0)4054; GFX10-NEXT: s_add_i32 s0, s0, 14055; GFX10-NEXT: v_mul_lo_u32 v1, s0, v04056; GFX10-NEXT: v_add_nc_u32_e32 v2, s0, v14057; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x04058; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v14059; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x104060; GFX10-NEXT: v_mul_lo_u32 v2, v2, v04061; GFX10-NEXT: v_mul_lo_u32 v3, v2, v14062; GFX10-NEXT: s_waitcnt lgkmcnt(0)4063; GFX10-NEXT: s_load_dword s2, s[2:3], 0x44064; GFX10-NEXT: v_add_nc_u32_e32 v1, v3, v14065; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x04066; GFX10-NEXT: v_mul_lo_u32 v2, v1, v24067; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v34068; GFX10-NEXT: v_mul_lo_u32 v4, v2, v14069; GFX10-NEXT: s_waitcnt lgkmcnt(0)4070; GFX10-NEXT: s_and_b32 s2, s2, 0xffff4071; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v14072; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s8, s2, v[0:1]4073; GFX10-NEXT: v_mul_lo_u32 v1, v3, v24074; GFX10-NEXT: v_add_co_u32 v2, s0, s0, v04075; GFX10-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s04076; GFX10-NEXT: v_mad_u64_u32 v[4:5], null, v1, v4, v[1:2]4077; GFX10-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]4078; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v4, v1, v[4:5]4079; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, s4, v24080; GFX10-NEXT: v_add_co_ci_u32_e64 v2, null, s5, v3, vcc_lo4081; GFX10-NEXT: global_store_dword v[1:2], v0, off4082; GFX10-NEXT: s_endpgm4083;4084; GFX1250-LABEL: compute_mad:4085; GFX1250: ; %bb.0: ; %bb4086; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14087; GFX1250-NEXT: s_load_b96 s[8:10], s[4:5], 0x104088; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v04089; GFX1250-NEXT: s_wait_kmcnt 0x04090; GFX1250-NEXT: s_add_co_i32 s0, s10, 14091; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)4092; GFX1250-NEXT: v_mul_lo_u32 v1, s0, v04093; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)4094; GFX1250-NEXT: v_dual_add_nc_u32 v2, s0, v1 :: v_dual_add_nc_u32 v1, 1, v14095; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x04096; GFX1250-NEXT: s_wait_xcnt 0x04097; GFX1250-NEXT: s_and_b32 s4, ttmp6, 154098; GFX1250-NEXT: s_getreg_b32 s5, hwreg(HW_REG_IB_STS2, 6, 4)4099; GFX1250-NEXT: v_mul_lo_u32 v2, v2, v04100; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)4101; GFX1250-NEXT: v_mul_lo_u32 v3, v2, v14102; GFX1250-NEXT: s_wait_kmcnt 0x04103; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x44104; GFX1250-NEXT: s_wait_xcnt 0x04105; GFX1250-NEXT: s_bfe_u32 s3, ttmp6, 0x4000c4106; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x04107; GFX1250-NEXT: s_add_co_i32 s3, s3, 14108; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)4109; GFX1250-NEXT: s_mul_i32 s3, ttmp9, s34110; GFX1250-NEXT: v_add_nc_u32_e32 v1, v3, v14111; GFX1250-NEXT: s_add_co_i32 s4, s4, s34112; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)4113; GFX1250-NEXT: v_mul_lo_u32 v1, v1, v24114; GFX1250-NEXT: v_add_nc_u32_e32 v2, 1, v34115; GFX1250-NEXT: s_wait_kmcnt 0x04116; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff4117; GFX1250-NEXT: s_cmp_eq_u32 s5, 04118; GFX1250-NEXT: v_mul_lo_u32 v3, v1, v24119; GFX1250-NEXT: s_cselect_b32 s3, ttmp9, s44120; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)4121; GFX1250-NEXT: v_mad_u32 v0, s3, s2, v04122; GFX1250-NEXT: v_add_nc_u32_e32 v2, v3, v24123; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4124; GFX1250-NEXT: v_mul_lo_u32 v2, v2, v14125; GFX1250-NEXT: v_mov_b32_e32 v1, 04126; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]4127; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4128; GFX1250-NEXT: v_mad_u32 v3, v2, v3, v24129; GFX1250-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 2, s[8:9]4130; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)4131; GFX1250-NEXT: v_mad_u32 v2, v3, v2, v34132; GFX1250-NEXT: global_store_b32 v[0:1], v2, off4133; GFX1250-NEXT: s_endpgm4134bb:4135 %i = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !04136 %i2 = add i32 %arg1, 14137 %i3 = mul i32 %i2, %i4138 %i4 = add i32 %i3, %i24139 %i5 = mul i32 %i4, %i4140 %i6 = add i32 %i3, 14141 %i7 = mul i32 %i5, %i64142 %i8 = add i32 %i7, %i64143 %i9 = mul i32 %i8, %i54144 %i10 = add i32 %i7, 14145 %i11 = mul i32 %i9, %i104146 %i12 = add i32 %i11, %i104147 %i13 = mul i32 %i12, %i94148 %i14 = add i32 %i11, 14149 %i15 = add i32 %i13, 14150 %i16 = mul i32 %i13, %i144151 %i17 = mul i32 %i16, %i154152 %i19 = load i64, ptr addrspace(4) %i18, align 84153 %i20 = tail call i32 @llvm.amdgcn.workgroup.id.x()4154 %i22 = getelementptr i8, ptr addrspace(4) %i21, i64 44155 %i23 = load i16, ptr addrspace(4) %i22, align 44156 %i24 = zext i16 %i23 to i324157 %i25 = mul i32 %i20, %i244158 %i26 = add i32 %i25, %i4159 %i27 = zext i32 %i26 to i644160 %i28 = add i64 %i19, %i274161 %i29 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %i284162 store i32 %i17, ptr addrspace(1) %i29, align 44163 ret void4164}4165 4166define amdgpu_ps i32 @s_mul_add_1_i32(i32 inreg %x, i32 inreg %y) {4167; GFX67-LABEL: s_mul_add_1_i32:4168; GFX67: ; %bb.0:4169; GFX67-NEXT: s_add_i32 s1, s1, 14170; GFX67-NEXT: s_mul_i32 s0, s0, s14171; GFX67-NEXT: ; return to shader part epilog4172;4173; GFX8-LABEL: s_mul_add_1_i32:4174; GFX8: ; %bb.0:4175; GFX8-NEXT: s_add_i32 s1, s1, 14176; GFX8-NEXT: s_mul_i32 s0, s0, s14177; GFX8-NEXT: ; return to shader part epilog4178;4179; GFX9-LABEL: s_mul_add_1_i32:4180; GFX9: ; %bb.0:4181; GFX9-NEXT: s_add_i32 s1, s1, 14182; GFX9-NEXT: s_mul_i32 s0, s0, s14183; GFX9-NEXT: ; return to shader part epilog4184;4185; GFX10-LABEL: s_mul_add_1_i32:4186; GFX10: ; %bb.0:4187; GFX10-NEXT: s_add_i32 s1, s1, 14188; GFX10-NEXT: s_mul_i32 s0, s0, s14189; GFX10-NEXT: ; return to shader part epilog4190;4191; GFX1250-LABEL: s_mul_add_1_i32:4192; GFX1250: ; %bb.0:4193; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14194; GFX1250-NEXT: s_add_co_i32 s1, s1, 14195; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4196; GFX1250-NEXT: s_mul_i32 s0, s0, s14197; GFX1250-NEXT: ; return to shader part epilog4198 %add = add i32 %y, 14199 %mul = mul i32 %x, %add4200 ret i32 %mul4201}4202 4203define amdgpu_ps i32 @s_mul_add_1_i32_commute(i32 inreg %x, i32 inreg %y) {4204; GFX67-LABEL: s_mul_add_1_i32_commute:4205; GFX67: ; %bb.0:4206; GFX67-NEXT: s_add_i32 s1, s1, 14207; GFX67-NEXT: s_mul_i32 s0, s1, s04208; GFX67-NEXT: ; return to shader part epilog4209;4210; GFX8-LABEL: s_mul_add_1_i32_commute:4211; GFX8: ; %bb.0:4212; GFX8-NEXT: s_add_i32 s1, s1, 14213; GFX8-NEXT: s_mul_i32 s0, s1, s04214; GFX8-NEXT: ; return to shader part epilog4215;4216; GFX9-LABEL: s_mul_add_1_i32_commute:4217; GFX9: ; %bb.0:4218; GFX9-NEXT: s_add_i32 s1, s1, 14219; GFX9-NEXT: s_mul_i32 s0, s1, s04220; GFX9-NEXT: ; return to shader part epilog4221;4222; GFX10-LABEL: s_mul_add_1_i32_commute:4223; GFX10: ; %bb.0:4224; GFX10-NEXT: s_add_i32 s1, s1, 14225; GFX10-NEXT: s_mul_i32 s0, s1, s04226; GFX10-NEXT: ; return to shader part epilog4227;4228; GFX1250-LABEL: s_mul_add_1_i32_commute:4229; GFX1250: ; %bb.0:4230; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14231; GFX1250-NEXT: s_add_co_i32 s1, s1, 14232; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4233; GFX1250-NEXT: s_mul_i32 s0, s1, s04234; GFX1250-NEXT: ; return to shader part epilog4235 %add = add i32 %y, 14236 %mul = mul i32 %add, %x4237 ret i32 %mul4238}4239 4240define i8 @v_mul_add_1_i8(i8 %x, i8 %y) {4241; GFX67-LABEL: v_mul_add_1_i8:4242; GFX67: ; %bb.0:4243; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4244; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v14245; GFX67-NEXT: v_and_b32_e32 v0, 0xff, v04246; GFX67-NEXT: v_and_b32_e32 v1, 0xff, v14247; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v14248; GFX67-NEXT: s_setpc_b64 s[30:31]4249;4250; GFX8-LABEL: v_mul_add_1_i8:4251; GFX8: ; %bb.0:4252; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4253; GFX8-NEXT: v_mad_u16 v0, v0, v1, v04254; GFX8-NEXT: s_setpc_b64 s[30:31]4255;4256; GFX9-LABEL: v_mul_add_1_i8:4257; GFX9: ; %bb.0:4258; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4259; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v04260; GFX9-NEXT: s_setpc_b64 s[30:31]4261;4262; GFX10-LABEL: v_mul_add_1_i8:4263; GFX10: ; %bb.0:4264; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4265; GFX10-NEXT: v_mad_u16 v0, v0, v1, v04266; GFX10-NEXT: s_setpc_b64 s[30:31]4267;4268; GFX1250-LABEL: v_mul_add_1_i8:4269; GFX1250: ; %bb.0:4270; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04271; GFX1250-NEXT: s_wait_kmcnt 0x04272; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v04273; GFX1250-NEXT: s_set_pc_i64 s[30:31]4274 %add = add i8 %y, 14275 %mul = mul i8 %x, %add4276 ret i8 %mul4277}4278 4279define i8 @v_mul_add_1_i8_commute(i8 %x, i8 %y) {4280; GFX67-LABEL: v_mul_add_1_i8_commute:4281; GFX67: ; %bb.0:4282; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4283; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v14284; GFX67-NEXT: v_and_b32_e32 v1, 0xff, v14285; GFX67-NEXT: v_and_b32_e32 v0, 0xff, v04286; GFX67-NEXT: v_mul_u32_u24_e32 v0, v1, v04287; GFX67-NEXT: s_setpc_b64 s[30:31]4288;4289; GFX8-LABEL: v_mul_add_1_i8_commute:4290; GFX8: ; %bb.0:4291; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4292; GFX8-NEXT: v_mad_u16 v0, v0, v1, v04293; GFX8-NEXT: s_setpc_b64 s[30:31]4294;4295; GFX9-LABEL: v_mul_add_1_i8_commute:4296; GFX9: ; %bb.0:4297; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4298; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v04299; GFX9-NEXT: s_setpc_b64 s[30:31]4300;4301; GFX10-LABEL: v_mul_add_1_i8_commute:4302; GFX10: ; %bb.0:4303; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4304; GFX10-NEXT: v_mad_u16 v0, v0, v1, v04305; GFX10-NEXT: s_setpc_b64 s[30:31]4306;4307; GFX1250-LABEL: v_mul_add_1_i8_commute:4308; GFX1250: ; %bb.0:4309; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04310; GFX1250-NEXT: s_wait_kmcnt 0x04311; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v04312; GFX1250-NEXT: s_set_pc_i64 s[30:31]4313 %add = add i8 %y, 14314 %mul = mul i8 %add, %x4315 ret i8 %mul4316}4317 4318define i8 @v_mul_add_1_i8_zext(i8 zeroext %x, i8 zeroext %y) {4319; GFX67-LABEL: v_mul_add_1_i8_zext:4320; GFX67: ; %bb.0:4321; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4322; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v14323; GFX67-NEXT: v_and_b32_e32 v1, 0xff, v14324; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v14325; GFX67-NEXT: s_setpc_b64 s[30:31]4326;4327; GFX8-LABEL: v_mul_add_1_i8_zext:4328; GFX8: ; %bb.0:4329; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4330; GFX8-NEXT: v_mad_u16 v0, v0, v1, v04331; GFX8-NEXT: s_setpc_b64 s[30:31]4332;4333; GFX9-LABEL: v_mul_add_1_i8_zext:4334; GFX9: ; %bb.0:4335; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4336; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v04337; GFX9-NEXT: s_setpc_b64 s[30:31]4338;4339; GFX10-LABEL: v_mul_add_1_i8_zext:4340; GFX10: ; %bb.0:4341; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4342; GFX10-NEXT: v_mad_u16 v0, v0, v1, v04343; GFX10-NEXT: s_setpc_b64 s[30:31]4344;4345; GFX1250-LABEL: v_mul_add_1_i8_zext:4346; GFX1250: ; %bb.0:4347; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04348; GFX1250-NEXT: s_wait_kmcnt 0x04349; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v04350; GFX1250-NEXT: s_set_pc_i64 s[30:31]4351 %add = add i8 %y, 14352 %mul = mul i8 %x, %add4353 ret i8 %mul4354}4355 4356define i8 @v_mul_add_1_i8_zext_commute(i8 zeroext %x, i8 zeroext %y) {4357; GFX67-LABEL: v_mul_add_1_i8_zext_commute:4358; GFX67: ; %bb.0:4359; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4360; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v14361; GFX67-NEXT: v_and_b32_e32 v1, 0xff, v14362; GFX67-NEXT: v_mul_u32_u24_e32 v0, v1, v04363; GFX67-NEXT: s_setpc_b64 s[30:31]4364;4365; GFX8-LABEL: v_mul_add_1_i8_zext_commute:4366; GFX8: ; %bb.0:4367; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4368; GFX8-NEXT: v_mad_u16 v0, v0, v1, v04369; GFX8-NEXT: s_setpc_b64 s[30:31]4370;4371; GFX9-LABEL: v_mul_add_1_i8_zext_commute:4372; GFX9: ; %bb.0:4373; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4374; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v1, v04375; GFX9-NEXT: s_setpc_b64 s[30:31]4376;4377; GFX10-LABEL: v_mul_add_1_i8_zext_commute:4378; GFX10: ; %bb.0:4379; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4380; GFX10-NEXT: v_mad_u16 v0, v0, v1, v04381; GFX10-NEXT: s_setpc_b64 s[30:31]4382;4383; GFX1250-LABEL: v_mul_add_1_i8_zext_commute:4384; GFX1250: ; %bb.0:4385; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04386; GFX1250-NEXT: s_wait_kmcnt 0x04387; GFX1250-NEXT: v_mad_u16 v0, v0, v1, v04388; GFX1250-NEXT: s_set_pc_i64 s[30:31]4389 %add = add i8 %y, 14390 %mul = mul i8 %add, %x4391 ret i8 %mul4392}4393 4394define <2 x i8> @v_mul_add_1_v2i8(<2 x i8> %x, <2 x i8> %y) {4395; GFX67-LABEL: v_mul_add_1_v2i8:4396; GFX67: ; %bb.0:4397; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4398; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v24399; GFX67-NEXT: v_lshlrev_b32_e32 v3, 8, v34400; GFX67-NEXT: v_and_b32_e32 v2, 0xff, v24401; GFX67-NEXT: v_or_b32_e32 v2, v3, v24402; GFX67-NEXT: v_add_i32_e32 v2, vcc, 0x100, v24403; GFX67-NEXT: v_bfe_u32 v3, v2, 8, 84404; GFX67-NEXT: v_and_b32_e32 v0, 0xff, v04405; GFX67-NEXT: v_and_b32_e32 v2, 0xff, v24406; GFX67-NEXT: v_and_b32_e32 v1, 0xff, v14407; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v24408; GFX67-NEXT: v_mul_u32_u24_e32 v1, v1, v34409; GFX67-NEXT: s_setpc_b64 s[30:31]4410;4411; GFX8-LABEL: v_mul_add_1_v2i8:4412; GFX8: ; %bb.0:4413; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4414; GFX8-NEXT: v_mad_u16 v1, v1, v3, v14415; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v14416; GFX8-NEXT: v_mad_u16 v0, v0, v2, v04417; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4418; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v14419; GFX8-NEXT: s_setpc_b64 s[30:31]4420;4421; GFX9-LABEL: v_mul_add_1_v2i8:4422; GFX9: ; %bb.0:4423; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4424; GFX9-NEXT: v_mad_legacy_u16 v1, v1, v3, v14425; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v14426; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v2, v04427; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4428; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v14429; GFX9-NEXT: s_setpc_b64 s[30:31]4430;4431; GFX10-LABEL: v_mul_add_1_v2i8:4432; GFX10: ; %bb.0:4433; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4434; GFX10-NEXT: v_mad_u16 v1, v1, v3, v14435; GFX10-NEXT: v_mad_u16 v0, v0, v2, v04436; GFX10-NEXT: v_lshlrev_b16 v2, 8, v14437; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v14438; GFX10-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4439; GFX10-NEXT: s_setpc_b64 s[30:31]4440;4441; GFX1250-LABEL: v_mul_add_1_v2i8:4442; GFX1250: ; %bb.0:4443; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04444; GFX1250-NEXT: s_wait_kmcnt 0x04445; GFX1250-NEXT: v_mad_u16 v1, v1, v3, v14446; GFX1250-NEXT: v_mad_u16 v0, v0, v2, v04447; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)4448; GFX1250-NEXT: v_lshlrev_b16 v2, 8, v14449; GFX1250-NEXT: v_and_b32_e32 v1, 0xff, v14450; GFX1250-NEXT: v_bitop3_b16 v0, v0, v2, 0xff bitop3:0xec4451; GFX1250-NEXT: s_set_pc_i64 s[30:31]4452 %add = add <2 x i8> %y, <i8 1, i8 1>4453 %mul = mul <2 x i8> %x, %add4454 ret <2 x i8> %mul4455}4456 4457define <2 x i8> @v_mul_add_1_v2i8_commute(<2 x i8> %x, <2 x i8> %y) {4458; GFX67-LABEL: v_mul_add_1_v2i8_commute:4459; GFX67: ; %bb.0:4460; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4461; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v24462; GFX67-NEXT: v_lshlrev_b32_e32 v3, 8, v34463; GFX67-NEXT: v_and_b32_e32 v2, 0xff, v24464; GFX67-NEXT: v_or_b32_e32 v2, v3, v24465; GFX67-NEXT: v_add_i32_e32 v2, vcc, 0x100, v24466; GFX67-NEXT: v_bfe_u32 v3, v2, 8, 84467; GFX67-NEXT: v_and_b32_e32 v2, 0xff, v24468; GFX67-NEXT: v_and_b32_e32 v0, 0xff, v04469; GFX67-NEXT: v_and_b32_e32 v1, 0xff, v14470; GFX67-NEXT: v_mul_u32_u24_e32 v0, v2, v04471; GFX67-NEXT: v_mul_u32_u24_e32 v1, v3, v14472; GFX67-NEXT: s_setpc_b64 s[30:31]4473;4474; GFX8-LABEL: v_mul_add_1_v2i8_commute:4475; GFX8: ; %bb.0:4476; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4477; GFX8-NEXT: v_mad_u16 v1, v1, v3, v14478; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v14479; GFX8-NEXT: v_mad_u16 v0, v0, v2, v04480; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4481; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v14482; GFX8-NEXT: s_setpc_b64 s[30:31]4483;4484; GFX9-LABEL: v_mul_add_1_v2i8_commute:4485; GFX9: ; %bb.0:4486; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4487; GFX9-NEXT: v_mad_legacy_u16 v1, v1, v3, v14488; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v14489; GFX9-NEXT: v_mad_legacy_u16 v0, v0, v2, v04490; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4491; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v14492; GFX9-NEXT: s_setpc_b64 s[30:31]4493;4494; GFX10-LABEL: v_mul_add_1_v2i8_commute:4495; GFX10: ; %bb.0:4496; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4497; GFX10-NEXT: v_mad_u16 v1, v1, v3, v14498; GFX10-NEXT: v_mad_u16 v0, v0, v2, v04499; GFX10-NEXT: v_lshlrev_b16 v2, 8, v14500; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v14501; GFX10-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4502; GFX10-NEXT: s_setpc_b64 s[30:31]4503;4504; GFX1250-LABEL: v_mul_add_1_v2i8_commute:4505; GFX1250: ; %bb.0:4506; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04507; GFX1250-NEXT: s_wait_kmcnt 0x04508; GFX1250-NEXT: v_mad_u16 v1, v1, v3, v14509; GFX1250-NEXT: v_mad_u16 v0, v0, v2, v04510; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)4511; GFX1250-NEXT: v_lshlrev_b16 v2, 8, v14512; GFX1250-NEXT: v_and_b32_e32 v1, 0xff, v14513; GFX1250-NEXT: v_bitop3_b16 v0, v0, v2, 0xff bitop3:0xec4514; GFX1250-NEXT: s_set_pc_i64 s[30:31]4515 %add = add <2 x i8> %y, <i8 1, i8 1>4516 %mul = mul <2 x i8> %add, %x4517 ret <2 x i8> %mul4518}4519 4520; test mul_u24 intrinsic with (i32, i32) -> i644521define i64 @mul_u24_with_uneven_operands(i32 %z) {4522; GFX67-LABEL: mul_u24_with_uneven_operands:4523; GFX67: ; %bb.0: ; %entry4524; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4525; GFX67-NEXT: v_and_b32_e32 v0, 1, v04526; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v04527; GFX67-NEXT: v_mul_u32_u24_e32 v0, v1, v04528; GFX67-NEXT: v_mov_b32_e32 v1, 04529; GFX67-NEXT: s_setpc_b64 s[30:31]4530;4531; GFX8-LABEL: mul_u24_with_uneven_operands:4532; GFX8: ; %bb.0: ; %entry4533; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4534; GFX8-NEXT: v_and_b32_e32 v0, 1, v04535; GFX8-NEXT: v_add_u32_e32 v1, vcc, 1, v04536; GFX8-NEXT: v_mul_u32_u24_e32 v0, v1, v04537; GFX8-NEXT: v_mov_b32_e32 v1, 04538; GFX8-NEXT: s_setpc_b64 s[30:31]4539;4540; GFX9-LABEL: mul_u24_with_uneven_operands:4541; GFX9: ; %bb.0: ; %entry4542; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4543; GFX9-NEXT: v_and_b32_e32 v0, 1, v04544; GFX9-NEXT: v_add_u32_e32 v1, 1, v04545; GFX9-NEXT: v_mul_u32_u24_e32 v0, v1, v04546; GFX9-NEXT: v_mov_b32_e32 v1, 04547; GFX9-NEXT: s_setpc_b64 s[30:31]4548;4549; GFX10-LABEL: mul_u24_with_uneven_operands:4550; GFX10: ; %bb.0: ; %entry4551; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4552; GFX10-NEXT: v_and_b32_e32 v0, 1, v04553; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v04554; GFX10-NEXT: v_mul_u32_u24_e32 v0, v1, v04555; GFX10-NEXT: v_mov_b32_e32 v1, 04556; GFX10-NEXT: s_setpc_b64 s[30:31]4557;4558; GFX1250-LABEL: mul_u24_with_uneven_operands:4559; GFX1250: ; %bb.0: ; %entry4560; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04561; GFX1250-NEXT: s_wait_kmcnt 0x04562; GFX1250-NEXT: v_and_b32_e32 v0, 1, v04563; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4564; GFX1250-NEXT: v_add_nc_u32_e32 v1, 1, v04565; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v1, v04566; GFX1250-NEXT: v_mov_b32_e32 v1, 04567; GFX1250-NEXT: s_set_pc_i64 s[30:31]4568entry:4569 %c = and i32 %z, 14570 %d = add nuw nsw i32 %c, 14571 %f = call i64 @llvm.amdgcn.mul.u24(i32 %d, i32 %c)4572 ret i64 %f4573}4574 4575define i64 @mul_u24_with_uneven_operands_swapped(i32 %z) {4576; GFX67-LABEL: mul_u24_with_uneven_operands_swapped:4577; GFX67: ; %bb.0: ; %entry4578; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4579; GFX67-NEXT: v_and_b32_e32 v0, 1, v04580; GFX67-NEXT: v_add_i32_e32 v1, vcc, 1, v04581; GFX67-NEXT: v_mul_u32_u24_e32 v0, v0, v14582; GFX67-NEXT: v_mov_b32_e32 v1, 04583; GFX67-NEXT: s_setpc_b64 s[30:31]4584;4585; GFX8-LABEL: mul_u24_with_uneven_operands_swapped:4586; GFX8: ; %bb.0: ; %entry4587; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4588; GFX8-NEXT: v_and_b32_e32 v0, 1, v04589; GFX8-NEXT: v_add_u32_e32 v1, vcc, 1, v04590; GFX8-NEXT: v_mul_u32_u24_e32 v0, v0, v14591; GFX8-NEXT: v_mov_b32_e32 v1, 04592; GFX8-NEXT: s_setpc_b64 s[30:31]4593;4594; GFX9-LABEL: mul_u24_with_uneven_operands_swapped:4595; GFX9: ; %bb.0: ; %entry4596; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4597; GFX9-NEXT: v_and_b32_e32 v0, 1, v04598; GFX9-NEXT: v_add_u32_e32 v1, 1, v04599; GFX9-NEXT: v_mul_u32_u24_e32 v0, v0, v14600; GFX9-NEXT: v_mov_b32_e32 v1, 04601; GFX9-NEXT: s_setpc_b64 s[30:31]4602;4603; GFX10-LABEL: mul_u24_with_uneven_operands_swapped:4604; GFX10: ; %bb.0: ; %entry4605; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4606; GFX10-NEXT: v_and_b32_e32 v0, 1, v04607; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v04608; GFX10-NEXT: v_mul_u32_u24_e32 v0, v0, v14609; GFX10-NEXT: v_mov_b32_e32 v1, 04610; GFX10-NEXT: s_setpc_b64 s[30:31]4611;4612; GFX1250-LABEL: mul_u24_with_uneven_operands_swapped:4613; GFX1250: ; %bb.0: ; %entry4614; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04615; GFX1250-NEXT: s_wait_kmcnt 0x04616; GFX1250-NEXT: v_and_b32_e32 v0, 1, v04617; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4618; GFX1250-NEXT: v_add_nc_u32_e32 v1, 1, v04619; GFX1250-NEXT: v_mul_u32_u24_e32 v0, v0, v14620; GFX1250-NEXT: v_mov_b32_e32 v1, 04621; GFX1250-NEXT: s_set_pc_i64 s[30:31]4622entry:4623 %c = and i32 %z, 14624 %d = add nuw nsw i32 %c, 14625 %f = call i64 @llvm.amdgcn.mul.u24(i32 %c, i32 %d)4626 ret i64 %f4627}4628 4629; test mul_i24 intrinsic with (i32, i32) -> i644630define i64 @mul_i24_with_uneven_operands(i32 %z) {4631; GFX67-LABEL: mul_i24_with_uneven_operands:4632; GFX67: ; %bb.0: ; %entry4633; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4634; GFX67-NEXT: v_and_b32_e32 v0, 1, v04635; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v04636; GFX67-NEXT: v_mul_hi_i32_i24_e32 v1, v2, v04637; GFX67-NEXT: v_mul_i32_i24_e32 v0, v2, v04638; GFX67-NEXT: s_setpc_b64 s[30:31]4639;4640; GFX8-LABEL: mul_i24_with_uneven_operands:4641; GFX8: ; %bb.0: ; %entry4642; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4643; GFX8-NEXT: v_and_b32_e32 v0, 1, v04644; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v04645; GFX8-NEXT: v_mul_hi_i32_i24_e32 v1, v2, v04646; GFX8-NEXT: v_mul_i32_i24_e32 v0, v2, v04647; GFX8-NEXT: s_setpc_b64 s[30:31]4648;4649; GFX9-LABEL: mul_i24_with_uneven_operands:4650; GFX9: ; %bb.0: ; %entry4651; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4652; GFX9-NEXT: v_and_b32_e32 v0, 1, v04653; GFX9-NEXT: v_add_u32_e32 v2, 1, v04654; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v2, v04655; GFX9-NEXT: v_mul_i32_i24_e32 v0, v2, v04656; GFX9-NEXT: s_setpc_b64 s[30:31]4657;4658; GFX10-LABEL: mul_i24_with_uneven_operands:4659; GFX10: ; %bb.0: ; %entry4660; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4661; GFX10-NEXT: v_and_b32_e32 v1, 1, v04662; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v14663; GFX10-NEXT: v_mul_i32_i24_e32 v0, v2, v14664; GFX10-NEXT: v_mul_hi_i32_i24_e32 v1, v2, v14665; GFX10-NEXT: s_setpc_b64 s[30:31]4666;4667; GFX1250-LABEL: mul_i24_with_uneven_operands:4668; GFX1250: ; %bb.0: ; %entry4669; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04670; GFX1250-NEXT: s_wait_kmcnt 0x04671; GFX1250-NEXT: v_and_b32_e32 v1, 1, v04672; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4673; GFX1250-NEXT: v_add_nc_u32_e32 v2, 1, v14674; GFX1250-NEXT: v_mul_i32_i24_e32 v0, v2, v14675; GFX1250-NEXT: v_mul_hi_i32_i24_e32 v1, v2, v14676; GFX1250-NEXT: s_set_pc_i64 s[30:31]4677entry:4678 %c = and i32 %z, 14679 %d = add nuw nsw i32 %c, 14680 %f = call i64 @llvm.amdgcn.mul.i24(i32 %d, i32 %c)4681 ret i64 %f4682}4683 4684define i64 @mul_i24_with_uneven_operands_swapped(i32 %z) {4685; GFX67-LABEL: mul_i24_with_uneven_operands_swapped:4686; GFX67: ; %bb.0: ; %entry4687; GFX67-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4688; GFX67-NEXT: v_and_b32_e32 v0, 1, v04689; GFX67-NEXT: v_add_i32_e32 v2, vcc, 1, v04690; GFX67-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v24691; GFX67-NEXT: v_mul_i32_i24_e32 v0, v0, v24692; GFX67-NEXT: s_setpc_b64 s[30:31]4693;4694; GFX8-LABEL: mul_i24_with_uneven_operands_swapped:4695; GFX8: ; %bb.0: ; %entry4696; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4697; GFX8-NEXT: v_and_b32_e32 v0, 1, v04698; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v04699; GFX8-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v24700; GFX8-NEXT: v_mul_i32_i24_e32 v0, v0, v24701; GFX8-NEXT: s_setpc_b64 s[30:31]4702;4703; GFX9-LABEL: mul_i24_with_uneven_operands_swapped:4704; GFX9: ; %bb.0: ; %entry4705; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4706; GFX9-NEXT: v_and_b32_e32 v0, 1, v04707; GFX9-NEXT: v_add_u32_e32 v2, 1, v04708; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v24709; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v24710; GFX9-NEXT: s_setpc_b64 s[30:31]4711;4712; GFX10-LABEL: mul_i24_with_uneven_operands_swapped:4713; GFX10: ; %bb.0: ; %entry4714; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4715; GFX10-NEXT: v_and_b32_e32 v1, 1, v04716; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v14717; GFX10-NEXT: v_mul_i32_i24_e32 v0, v1, v24718; GFX10-NEXT: v_mul_hi_i32_i24_e32 v1, v1, v24719; GFX10-NEXT: s_setpc_b64 s[30:31]4720;4721; GFX1250-LABEL: mul_i24_with_uneven_operands_swapped:4722; GFX1250: ; %bb.0: ; %entry4723; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x04724; GFX1250-NEXT: s_wait_kmcnt 0x04725; GFX1250-NEXT: v_and_b32_e32 v1, 1, v04726; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)4727; GFX1250-NEXT: v_add_nc_u32_e32 v2, 1, v14728; GFX1250-NEXT: v_mul_i32_i24_e32 v0, v1, v24729; GFX1250-NEXT: v_mul_hi_i32_i24_e32 v1, v1, v24730; GFX1250-NEXT: s_set_pc_i64 s[30:31]4731entry:4732 %c = and i32 %z, 14733 %d = add nuw nsw i32 %c, 14734 %f = call i64 @llvm.amdgcn.mul.i24(i32 %c, i32 %d)4735 ret i64 %f4736}4737 4738declare align 4 ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #24739declare i32 @llvm.amdgcn.workitem.id.x() #24740declare align 4 ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #24741declare i32 @llvm.amdgcn.workgroup.id.x() #24742declare i64 @llvm.amdgcn.mul.u24(i32, i32)4743declare i64 @llvm.amdgcn.mul.i24(i32, i32)4744 4745attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }4746attributes #1 = { mustprogress nofree nosync nounwind willreturn memory(read, argmem: readwrite, inaccessiblemem: none) }4747attributes #2 = { mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none) }4748 4749!0 = !{i32 0, i32 1024}4750