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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s4 5; The register coalescer introduces a verifier error which later6; results in a crash during scheduling.7 8declare i32 @llvm.amdgcn.workitem.id.x() #09 10define amdgpu_kernel void @reg_coalescer_breaks_dead(ptr addrspace(1) nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3, i1 %c0) #1 {11; GFX6-LABEL: reg_coalescer_breaks_dead:12; GFX6: ; %bb.0: ; %bb13; GFX6-NEXT: v_mov_b32_e32 v1, 014; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v015; GFX6-NEXT: v_mov_b32_e32 v2, 016; GFX6-NEXT: s_and_saveexec_b64 s[0:1], vcc17; GFX6-NEXT: s_cbranch_execz .LBB0_218; GFX6-NEXT: ; %bb.1: ; %bb319; GFX6-NEXT: s_load_dword s2, s[4:5], 0xb20; GFX6-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x921; GFX6-NEXT: s_waitcnt lgkmcnt(0)22; GFX6-NEXT: s_ashr_i32 s3, s2, 3123; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 324; GFX6-NEXT: s_add_u32 s2, s6, s225; GFX6-NEXT: s_addc_u32 s3, s7, s326; GFX6-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x027; GFX6-NEXT: s_waitcnt lgkmcnt(0)28; GFX6-NEXT: v_mov_b32_e32 v1, s229; GFX6-NEXT: v_mov_b32_e32 v2, s330; GFX6-NEXT: .LBB0_2: ; %bb431; GFX6-NEXT: s_or_b64 exec, exec, s[0:1]32; GFX6-NEXT: s_load_dword s0, s[4:5], 0xe33; GFX6-NEXT: s_waitcnt lgkmcnt(0)34; GFX6-NEXT: s_bitcmp0_b32 s0, 035; GFX6-NEXT: s_cbranch_scc1 .LBB0_436; GFX6-NEXT: ; %bb.3: ; %bb1537; GFX6-NEXT: s_mov_b32 m0, -138; GFX6-NEXT: ds_write_b64 v0, v[1:2]39; GFX6-NEXT: .LBB0_4: ; %bb1640;41; GFX8-LABEL: reg_coalescer_breaks_dead:42; GFX8: ; %bb.0: ; %bb43; GFX8-NEXT: v_mov_b32_e32 v1, 044; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v045; GFX8-NEXT: v_mov_b32_e32 v2, 046; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc47; GFX8-NEXT: s_cbranch_execz .LBB0_248; GFX8-NEXT: ; %bb.1: ; %bb349; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c50; GFX8-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2451; GFX8-NEXT: s_waitcnt lgkmcnt(0)52; GFX8-NEXT: s_ashr_i32 s3, s2, 3153; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 354; GFX8-NEXT: s_add_u32 s2, s6, s255; GFX8-NEXT: s_addc_u32 s3, s7, s356; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x057; GFX8-NEXT: s_waitcnt lgkmcnt(0)58; GFX8-NEXT: v_mov_b32_e32 v1, s259; GFX8-NEXT: v_mov_b32_e32 v2, s360; GFX8-NEXT: .LBB0_2: ; %bb461; GFX8-NEXT: s_or_b64 exec, exec, s[0:1]62; GFX8-NEXT: s_load_dword s0, s[4:5], 0x3863; GFX8-NEXT: s_waitcnt lgkmcnt(0)64; GFX8-NEXT: s_bitcmp0_b32 s0, 065; GFX8-NEXT: s_cbranch_scc1 .LBB0_466; GFX8-NEXT: ; %bb.3: ; %bb1567; GFX8-NEXT: s_mov_b32 m0, -168; GFX8-NEXT: ds_write_b64 v0, v[1:2]69; GFX8-NEXT: .LBB0_4: ; %bb1670bb:71 %id.x = call i32 @llvm.amdgcn.workitem.id.x()72 %cmp0 = icmp eq i32 %id.x, 073 br i1 %cmp0, label %bb3, label %bb474 75bb3: ; preds = %bb76 %tmp = ashr exact i32 poison, 877 br label %bb678 79bb4: ; preds = %bb6, %bb80 %tmp5 = phi <2 x i32> [ zeroinitializer, %bb ], [ %tmp13, %bb6 ]81 br i1 %c0, label %bb15, label %bb1682 83bb6: ; preds = %bb6, %bb384 %tmp7 = phi <2 x i32> [ zeroinitializer, %bb3 ], [ %tmp13, %bb6 ]85 %tmp8 = add nsw i32 0, %arg186 %tmp9 = add nsw i32 %tmp8, 087 %tmp10 = sext i32 %tmp9 to i6488 %tmp11 = getelementptr inbounds <2 x i32>, ptr addrspace(1) %arg, i64 %tmp1089 %tmp12 = load <2 x i32>, ptr addrspace(1) %tmp11, align 890 %tmp13 = add <2 x i32> %tmp12, %tmp791 %tmp14 = icmp slt i32 poison, %arg292 br i1 %tmp14, label %bb6, label %bb493 94bb15: ; preds = %bb495 store <2 x i32> %tmp5, ptr addrspace(3) poison, align 896 br label %bb1697 98bb16: ; preds = %bb15, %bb499 unreachable100}101 102attributes #0 = { nounwind readnone }103attributes #1 = { nounwind }104