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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 62# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s3 4# This test is to check fix for failure with "Bad machine code: Defining instruction does not modify register" due to corrupt lane mask.5 6---7name: reg_coalescer_subreg_liveness8tracksRegLiveness: true9liveins:10body: |11 ; CHECK-LABEL: name: reg_coalescer_subreg_liveness12 ; CHECK: bb.0:13 ; CHECK-NEXT: successors: %bb.1(0x80000000)14 ; CHECK-NEXT: liveins: $sgpr4_sgpr515 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr517 ; CHECK-NEXT: undef [[S_LOAD_DWORD_IMM:%[0-9]+]].sub1:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)18 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 119 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 020 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 021 ; CHECK-NEXT: TENSOR_LOAD_TO_LDS_D2 [[S_MOV_B32_]], [[S_MOV_B32_1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt22 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 123 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub024 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: bb.1:26 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)27 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub029 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub030 ; CHECK-NEXT: TENSOR_LOAD_TO_LDS_D2 [[S_MOV_B32_]], [[S_MOV_B32_1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt31 ; CHECK-NEXT: TENSOR_LOAD_TO_LDS_D2 [[S_LOAD_DWORD_IMM]], [[S_MOV_B32_1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt32 ; CHECK-NEXT: $vcc_lo = COPY $exec_lo33 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 034 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 135 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc_lo, implicit $vcc_lo, implicit $vcc_lo36 ; CHECK-NEXT: S_BRANCH %bb.237 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: bb.2:39 ; CHECK-NEXT: S_ENDPGM 040 bb.0:41 successors: %bb.1(0x80000000)42 liveins: $sgpr4_sgpr543 44 %0:sgpr_64 = COPY killed $sgpr4_sgpr545 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %0, 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)46 %2:sreg_32 = S_MOV_B32 147 undef %3.sub0:sgpr_128 = COPY %248 %4:sreg_32 = S_MOV_B32 049 undef %5.sub0:sgpr_256 = COPY %450 TENSOR_LOAD_TO_LDS_D2 %3, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt51 %6:sgpr_128 = COPY killed %352 %6.sub1:sgpr_128 = COPY killed %153 %7:sreg_32 = COPY $exec_lo54 %8:sreg_32 = COPY %255 %9:sreg_32 = COPY %456 57 bb.1:58 successors: %bb.1(0x40000000), %bb.2(0x40000000)59 60 %10:sreg_32 = COPY killed %861 undef %11.sub0:sgpr_128 = COPY %262 %11.sub1:sgpr_128 = COPY killed %1063 %11.sub2:sgpr_128 = COPY %264 %11.sub3:sgpr_128 = COPY %265 TENSOR_LOAD_TO_LDS_D2 killed %11, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt66 %12:sreg_32 = COPY killed %967 %13:sgpr_128 = COPY %668 %13.sub2:sgpr_128 = COPY killed %1269 TENSOR_LOAD_TO_LDS_D2 killed %13, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt70 $vcc_lo = COPY %771 %8:sreg_32 = COPY %472 %9:sreg_32 = COPY %273 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc_lo, implicit $vcc_lo, implicit $vcc74 S_BRANCH %bb.275 76 bb.2:77 S_ENDPGM 078...79---80name: reg_coalescer_subreg_liveness_281tracksRegLiveness: true82liveins:83body: |84 ; CHECK-LABEL: name: reg_coalescer_subreg_liveness_285 ; CHECK: bb.0:86 ; CHECK-NEXT: successors: %bb.1(0x80000000)87 ; CHECK-NEXT: liveins: $sgpr4_sgpr588 ; CHECK-NEXT: {{ $}}89 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr590 ; CHECK-NEXT: undef [[S_LOAD_DWORD_IMM:%[0-9]+]].sub2:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]], 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)91 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub1:sgpr_128 = S_LOAD_DWORD_IMM [[COPY]], 24, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)92 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 193 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 094 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: bb.1:96 ; CHECK-NEXT: successors: %bb.2(0x80000000)97 ; CHECK-NEXT: {{ $}}98 ; CHECK-NEXT: S_NOP 0, implicit [[S_LOAD_DWORD_IMM]], implicit [[S_MOV_B32_]]99 ; CHECK-NEXT: S_BRANCH %bb.2100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: bb.2:102 ; CHECK-NEXT: S_ENDPGM 0103 bb.0:104 successors: %bb.1(0x80000000)105 liveins: $sgpr4_sgpr5106 107 %0:sgpr_64 = COPY killed $sgpr4_sgpr5108 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)109 %2:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %0, 24, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)110 %3:sreg_32 = S_MOV_B32 1111 undef %4.sub0:sgpr_128 = COPY %3112 %5:sgpr_128 = COPY %4113 %5.sub1:sgpr_128 = COPY killed %2114 %6:sgpr_128 = COPY %5115 %6.sub2:sgpr_128 = COPY killed %1116 %7:sreg_32 = S_MOV_B32 0117 undef %8.sub0:sgpr_256 = COPY %7118 %9:sreg_32 = COPY %3119 120 bb.1:121 successors: %bb.2(0x80000000)122 123 %10:sreg_32 = COPY killed %9124 undef %11.sub0:sgpr_128 = COPY %3125 %11.sub1:sgpr_128 = COPY killed %10126 S_NOP 0, implicit %5, implicit %8127 S_BRANCH %bb.2128 129 bb.2:130 S_ENDPGM 0131...132