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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=register-coalescer -verify-machineinstrs -o - %s | FileCheck %s3 4# Bug 39602: Avoid "Couldn't join subrange" error when clearing valid5# lanes on an implicit_def that later cannot be erased.6 7---8name: lost_valid_lanes_maybe_erasable_implicit_def9tracksRegLiveness: true10body: |11 ; CHECK-LABEL: name: lost_valid_lanes_maybe_erasable_implicit_def12 ; CHECK: bb.0:13 ; CHECK-NEXT: successors: %bb.1(0x80000000)14 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: undef [[DEF:%[0-9]+]].sub1:sreg_64 = IMPLICIT_DEF16 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: bb.1:18 ; CHECK-NEXT: [[DEF:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 019 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[DEF]]20 ; CHECK-NEXT: dead [[DEF:%[0-9]+]].sub1:sreg_64 = COPY [[DEF]].sub021 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub122 bb.0:23 successors: %bb.124 undef %0.sub1:sreg_64 = IMPLICIT_DEF25 26 bb.1:27 %0.sub0:sreg_64 = S_MOV_B32 028 %1:sreg_64 = COPY %0:sreg_6429 dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_6430 S_ENDPGM 0, implicit %1.sub1:sreg_6431 32...33---34# Same as previous, except with a real value instead of35# IMPLICIT_DEF. These should both be handled the same way.36 37name: lost_valid_lanes_real_value38tracksRegLiveness: true39body: |40 ; CHECK-LABEL: name: lost_valid_lanes_real_value41 ; CHECK: bb.0:42 ; CHECK-NEXT: successors: %bb.1(0x80000000)43 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = S_MOV_B32 -145 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: bb.1:47 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64 = S_MOV_B32 048 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY [[S_MOV_B32_]]49 ; CHECK-NEXT: dead [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64 = COPY [[S_MOV_B32_]].sub050 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub151 bb.0:52 successors: %bb.153 undef %0.sub1:sreg_64 = S_MOV_B32 -154 55 bb.1:56 %0.sub0:sreg_64 = S_MOV_B32 057 %1:sreg_64 = COPY %0:sreg_6458 dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_6459 S_ENDPGM 0, implicit %1.sub1:sreg_6460 61...62