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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s3#4 5 6---7# the COPY can be coalesced based on subregister liveness8name: subrange_coalesce_liveout9tracksRegLiveness: true10body: |11 ; GCN-LABEL: name: subrange_coalesce_liveout12 ; GCN: bb.0:13 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)14 ; GCN-NEXT: liveins: $vgpr0_vgpr115 ; GCN-NEXT: {{ $}}16 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr117 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec18 ; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec19 ; GCN-NEXT: S_BRANCH %bb.120 ; GCN-NEXT: {{ $}}21 ; GCN-NEXT: bb.1:22 ; GCN-NEXT: successors: %bb.2(0x80000000)23 ; GCN-NEXT: {{ $}}24 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub1, implicit $exec25 ; GCN-NEXT: S_BRANCH %bb.226 ; GCN-NEXT: {{ $}}27 ; GCN-NEXT: bb.2:28 ; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub2, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec29 ; GCN-NEXT: S_ENDPGM 030 bb.0:31 successors: %bb.1, %bb.232 liveins: $vgpr0_vgpr133 34 %0:vreg_64 = COPY $vgpr0_vgpr135 %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec36 %2:vgpr_32 = COPY %1.sub037 S_CBRANCH_EXECZ %bb.2, implicit $exec38 S_BRANCH %bb.139 40 bb.1:41 successors: %bb.242 43 %2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub1, implicit $exec44 S_BRANCH %bb.245 46 bb.2:47 %4:vgpr_32 = V_ADD_U32_e32 %1.sub2, %2, implicit $exec48 S_ENDPGM 049...50 51---52# early-clobber stops the coalescer from coalescing the COPY53name: subrange_coalesce_early_clobber54tracksRegLiveness: true55body: |56 ; GCN-LABEL: name: subrange_coalesce_early_clobber57 ; GCN: bb.0:58 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)59 ; GCN-NEXT: liveins: $vgpr0_vgpr160 ; GCN-NEXT: {{ $}}61 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr162 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec63 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX4_]].sub064 ; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec65 ; GCN-NEXT: S_BRANCH %bb.166 ; GCN-NEXT: {{ $}}67 ; GCN-NEXT: bb.1:68 ; GCN-NEXT: successors: %bb.2(0x80000000)69 ; GCN-NEXT: {{ $}}70 ; GCN-NEXT: early-clobber [[COPY1]]:vgpr_32 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec71 ; GCN-NEXT: S_BRANCH %bb.272 ; GCN-NEXT: {{ $}}73 ; GCN-NEXT: bb.2:74 ; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub2, [[COPY1]], implicit $exec75 ; GCN-NEXT: S_ENDPGM 076 bb.0:77 successors: %bb.1, %bb.278 liveins: $vgpr0_vgpr179 80 %0:vreg_64 = COPY $vgpr0_vgpr181 %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec82 %2:vgpr_32 = COPY %1.sub083 S_CBRANCH_EXECZ %bb.2, implicit $exec84 S_BRANCH %bb.185 86 bb.1:87 successors: %bb.288 89 early-clobber %2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub2, implicit $exec90 S_BRANCH %bb.291 92 bb.2:93 %4:vgpr_32 = V_ADD_U32_e32 %1.sub2, %2, implicit $exec94 S_ENDPGM 095...96 97---98# non-conflict lane(sub1) was redefined, coalescable99name: subrange_coalesce_unrelated_sub_redefined100tracksRegLiveness: true101body: |102 ; GCN-LABEL: name: subrange_coalesce_unrelated_sub_redefined103 ; GCN: bb.0:104 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)105 ; GCN-NEXT: liveins: $vgpr0_vgpr1106 ; GCN-NEXT: {{ $}}107 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1108 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec109 ; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec110 ; GCN-NEXT: S_BRANCH %bb.1111 ; GCN-NEXT: {{ $}}112 ; GCN-NEXT: bb.1:113 ; GCN-NEXT: successors: %bb.2(0x80000000)114 ; GCN-NEXT: {{ $}}115 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub1, implicit $exec116 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub1:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec117 ; GCN-NEXT: S_BRANCH %bb.2118 ; GCN-NEXT: {{ $}}119 ; GCN-NEXT: bb.2:120 ; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec121 ; GCN-NEXT: S_ENDPGM 0122 bb.0:123 successors: %bb.1, %bb.2124 liveins: $vgpr0_vgpr1125 126 %0:vreg_64 = COPY $vgpr0_vgpr1127 %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec128 %2:vgpr_32 = COPY %1.sub0129 S_CBRANCH_EXECZ %bb.2, implicit $exec130 S_BRANCH %bb.1131 132 bb.1:133 successors: %bb.2134 135 %2:vgpr_32 = V_AND_B32_e64 %1.sub0, %1.sub1, implicit $exec136 %1.sub1:vreg_128 = V_AND_B32_e64 %2, %2, implicit $exec137 S_BRANCH %bb.2138 139 bb.2:140 %4:vgpr_32 = V_ADD_U32_e32 %1.sub1, %2, implicit $exec141 S_ENDPGM 0142...143 144---145# Another complex example showing the capability of resolving lane conflict146# based on subranges.147name: subrange_coalesce_complex_pattern148tracksRegLiveness: true149body: |150 ; GCN-LABEL: name: subrange_coalesce_complex_pattern151 ; GCN: bb.0:152 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)153 ; GCN-NEXT: liveins: $vgpr0_vgpr1154 ; GCN-NEXT: {{ $}}155 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1156 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY]], 0, 0, implicit $exec157 ; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec158 ; GCN-NEXT: S_BRANCH %bb.1159 ; GCN-NEXT: {{ $}}160 ; GCN-NEXT: bb.1:161 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)162 ; GCN-NEXT: {{ $}}163 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub0:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec164 ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]].sub2:vreg_128 = V_AND_B32_e64 [[GLOBAL_LOAD_DWORDX4_]].sub0, [[GLOBAL_LOAD_DWORDX4_]].sub0, implicit $exec165 ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec166 ; GCN-NEXT: S_BRANCH %bb.2167 ; GCN-NEXT: {{ $}}168 ; GCN-NEXT: bb.2:169 ; GCN-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[GLOBAL_LOAD_DWORDX4_]].sub1, [[GLOBAL_LOAD_DWORDX4_]].sub2, implicit $exec170 ; GCN-NEXT: S_ENDPGM 0171 bb.0:172 successors: %bb.1, %bb.2173 liveins: $vgpr0_vgpr1174 175 %0:vreg_64 = COPY $vgpr0_vgpr1176 %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, implicit $exec177 %2:vgpr_32 = COPY %1.sub0178 S_CBRANCH_EXECZ %bb.2, implicit $exec179 S_BRANCH %bb.1180 181 bb.1:182 successors: %bb.1, %bb.2183 184 %2:vgpr_32 = V_AND_B32_e64 %1.sub1, %2, implicit $exec185 %1.sub2:vreg_128 = V_AND_B32_e64 %2, %2, implicit $exec186 S_CBRANCH_EXECZ %bb.1, implicit $exec187 S_BRANCH %bb.2188 189 bb.2:190 %4:vgpr_32 = V_ADD_U32_e32 %1.sub1, %1.sub2, implicit $exec191 S_ENDPGM 0192 193...194