51 lines · plain
1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s3 4; Rematerialization test for fp64 constants (w/ intentionally high register pressure).5; Check to make sure we have at least six constant MOVs, not necessarily consecutive, inside the loop.6 7; GCN-LABEL: {{^}}test_remat_sgpr:8; GCN-NOT: v_writelane_b329; GCN: {{^}}[[LOOP:.LBB[0-9_]+]]:10; GCN-COUNT-6: {{s_mov_b32|v_mov_b32_e32}} {{[sv]}}{{[0-9]+}}, 0x11; GCN-NOT: v_writelane_b3212; GCN: s_cbranch_{{[^ ]+}} [[LOOP]]13; GCN: .sgpr_spill_count: 014define amdgpu_kernel void @test_remat_sgpr(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {15bb:16 %i = tail call i32 @llvm.amdgcn.workitem.id.x()17 br label %bb318 19bb2: ; preds = %bb320 ret void21 22bb3: ; preds = %bb3, %bb23 %i4 = phi i32 [ 0, %bb ], [ %i22, %bb3 ]24 %i5 = add nuw nsw i32 %i4, %i25 %i6 = zext i32 %i5 to i6426 %i7 = getelementptr inbounds double, ptr addrspace(1) %arg, i64 %i627 %i8 = load double, ptr addrspace(1) %i7, align 828 %i9 = fadd double %i8, 0x3EFC01997CC9E6B029 %i10 = tail call double @llvm.fma.f64(double %i8, double %i9, double 0x3FBE25E43ABE935A)30 %i11 = tail call double @llvm.fma.f64(double %i10, double %i9, double 0x3FC110EF47E6C9C2)31 %i12 = tail call double @llvm.fma.f64(double %i11, double %i9, double 0x3FC3B13BCFA74449)32 %i13 = tail call double @llvm.fma.f64(double %i12, double %i9, double 0x3FC745D171BF3C30)33 %i14 = tail call double @llvm.fma.f64(double %i13, double %i9, double 0x3FCC71C71C7792CE)34 %i15 = tail call double @llvm.fma.f64(double %i14, double %i9, double 0x3FD24924924920DA)35 %i16 = tail call double @llvm.fma.f64(double %i15, double %i9, double 0x3FD999999999999C)36 %i17 = tail call double @llvm.fma.f64(double %i16, double %i9, double 0x3FD899999999899C)37 %i18 = tail call double @llvm.fma.f64(double %i17, double %i9, double 0x3FD799999999799C)38 %i19 = tail call double @llvm.fma.f64(double %i18, double %i9, double 0x3FD699999999699C)39 %i20 = tail call double @llvm.fma.f64(double %i19, double %i9, double 0x3FD599999999599C)40 %i21 = getelementptr inbounds double, ptr addrspace(1) %arg1, i64 %i641 store double %i19, ptr addrspace(1) %i21, align 842 %i22 = add nuw nsw i32 %i4, 143 %i23 = icmp eq i32 %i22, 102444 br i1 %i23, label %bb2, label %bb345}46 47declare double @llvm.fma.f64(double, double, double)48declare i32 @llvm.amdgcn.workitem.id.x()49 50attributes #0 = { "amdgpu-flat-work-group-size"="1024,1024" }51