191 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-pre-emit-peephole -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=si-pre-emit-peephole %s -o - | FileCheck %s4# Make sure mandatory skips are not removed around mode defs.5 6---7 8name: need_skip_setreg_imm32_b329body: |10 ; CHECK-LABEL: name: need_skip_setreg_imm32_b3211 ; CHECK: bb.0:12 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)13 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec15 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: bb.1:17 ; CHECK-NEXT: successors: %bb.2(0x80000000)18 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec20 ; CHECK-NEXT: S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: bb.2:23 ; CHECK-NEXT: S_ENDPGM 024 bb.0:25 successors: %bb.1, %bb.226 S_CBRANCH_EXECZ %bb.2, implicit $exec27 28 bb.1:29 successors: %bb.230 $vgpr0 = V_MOV_B32_e32 0, implicit $exec31 S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode32 33 bb.2:34 S_ENDPGM 035...36 37---38 39name: need_skip_setreg_b3240body: |41 ; CHECK-LABEL: name: need_skip_setreg_b3242 ; CHECK: bb.0:43 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)44 ; CHECK-NEXT: liveins: $sgpr045 ; CHECK-NEXT: {{ $}}46 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec47 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: bb.1:49 ; CHECK-NEXT: successors: %bb.2(0x80000000)50 ; CHECK-NEXT: liveins: $sgpr051 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec53 ; CHECK-NEXT: S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode54 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: bb.2:56 ; CHECK-NEXT: S_ENDPGM 057 bb.0:58 liveins: $sgpr059 successors: %bb.1, %bb.260 S_CBRANCH_EXECZ %bb.2, implicit $exec61 62 bb.1:63 liveins: $sgpr064 $vgpr0 = V_MOV_B32_e32 0, implicit $exec65 S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode66 67 bb.2:68 S_ENDPGM 069...70 71---72 73name: need_skip_denorm_mode74body: |75 ; CHECK-LABEL: name: need_skip_denorm_mode76 ; CHECK: bb.0:77 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)78 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec80 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: bb.1:82 ; CHECK-NEXT: successors: %bb.2(0x80000000)83 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec85 ; CHECK-NEXT: S_DENORM_MODE 3, implicit-def $mode, implicit $mode86 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: bb.2:88 ; CHECK-NEXT: S_ENDPGM 089 bb.0:90 successors: %bb.1, %bb.291 S_CBRANCH_EXECZ %bb.2, implicit $exec92 93 bb.1:94 $vgpr0 = V_MOV_B32_e32 0, implicit $exec95 S_DENORM_MODE 3, implicit-def $mode, implicit $mode96 97 bb.2:98 S_ENDPGM 099...100 101---102 103name: need_skip_round_mode104body: |105 ; CHECK-LABEL: name: need_skip_round_mode106 ; CHECK: bb.0:107 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: bb.1:112 ; CHECK-NEXT: successors: %bb.2(0x80000000)113 ; CHECK-NEXT: {{ $}}114 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec115 ; CHECK-NEXT: S_ROUND_MODE 3, implicit-def $mode, implicit $mode116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: bb.2:118 ; CHECK-NEXT: S_ENDPGM 0119 bb.0:120 successors: %bb.1, %bb.2121 S_CBRANCH_EXECZ %bb.2, implicit $exec122 123 bb.1:124 $vgpr0 = V_MOV_B32_e32 0, implicit $exec125 S_ROUND_MODE 3, implicit-def $mode, implicit $mode126 127 bb.2:128 S_ENDPGM 0129...130 131---132 133name: need_skip_writelane_b32134body: |135 ; CHECK-LABEL: name: need_skip_writelane_b32136 ; CHECK: bb.0:137 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: bb.1:142 ; CHECK-NEXT: successors: %bb.2(0x80000000)143 ; CHECK-NEXT: {{ $}}144 ; CHECK-NEXT: $sgpr0 = IMPLICIT_DEF145 ; CHECK-NEXT: $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: bb.2:148 ; CHECK-NEXT: S_ENDPGM 0149 bb.0:150 successors: %bb.1, %bb.2151 S_CBRANCH_EXECZ %bb.2, implicit $exec152 153 bb.1:154 successors: %bb.2155 $sgpr0 = IMPLICIT_DEF156 $vgpr0 = V_WRITELANE_B32 $sgpr0, 0, $vgpr0157 158 bb.2:159 S_ENDPGM 0160...161 162---163name: need_skip_readlane_b32164body: |165 ; CHECK-LABEL: name: need_skip_readlane_b32166 ; CHECK: bb.0:167 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)168 ; CHECK-NEXT: {{ $}}169 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: bb.1:172 ; CHECK-NEXT: successors: %bb.2(0x80000000)173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: $vgpr0 = IMPLICIT_DEF175 ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr0, 0176 ; CHECK-NEXT: {{ $}}177 ; CHECK-NEXT: bb.2:178 ; CHECK-NEXT: S_ENDPGM 0179 bb.0:180 successors: %bb.1, %bb.2181 S_CBRANCH_EXECZ %bb.2, implicit $exec182 183 bb.1:184 successors: %bb.2185 $vgpr0 = IMPLICIT_DEF186 $sgpr0 = V_READLANE_B32 $vgpr0, 0187 188 bb.2:189 S_ENDPGM 0190...191