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1# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass register-coalescer,rename-independent-subregs -o - %s | FileCheck %s2--- |3 define amdgpu_kernel void @test0() { ret void }4 define amdgpu_kernel void @test1() { ret void }5 define amdgpu_kernel void @test2() { ret void }6...7---8# In the test below we have two independent def+use pairs of subregister1 which9# can be moved to a new virtual register. The third def of sub1 however is used10# in combination with sub0 and needs to stay with the original vreg.11# CHECK-LABEL: name: test012# CHECK: S_NOP 0, implicit-def undef %0.sub013# CHECK: S_NOP 0, implicit-def undef %2.sub114# CHECK: S_NOP 0, implicit %2.sub115# CHECK: S_NOP 0, implicit-def undef %1.sub116# CHECK: S_NOP 0, implicit %1.sub117# CHECK: S_NOP 0, implicit-def %0.sub118# CHECK: S_NOP 0, implicit %019name: test020registers:21 - { id: 0, class: sgpr_128 }22body: |23 bb.0:24 S_NOP 0, implicit-def undef %0.sub025 S_NOP 0, implicit-def %0.sub126 S_NOP 0, implicit %0.sub127 S_NOP 0, implicit-def %0.sub128 S_NOP 0, implicit %0.sub129 S_NOP 0, implicit-def %0.sub130 S_NOP 0, implicit %031...32---33# Test for a bug where we would incorrectly query liveness at the instruction34# index in rewriteOperands(). This should pass the verifier afterwards.35# CHECK-LABEL: test136# CHECK: bb.037# CHECK: S_NOP 0, implicit-def undef %2.sub238# CHECK: bb.139# CHECK: S_NOP 0, implicit-def %2.sub140# CHECK-NEXT: S_NOP 0, implicit-def %2.sub341# CHECK-NEXT: S_NOP 0, implicit %242# CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub043# CHECK-NEXT: S_NOP 0, implicit %2.sub144# CHECK-NEXT: S_NOP 0, implicit %0.sub045# CHECK: bb.246# CHECK: S_NOP 0, implicit %2.sub47name: test148registers:49 - { id: 0, class: sgpr_128 }50 - { id: 1, class: sgpr_128 }51body: |52 bb.0:53 S_NOP 0, implicit-def undef %0.sub254 S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc55 S_BRANCH %bb.256 57 bb.1:58 S_NOP 0, implicit-def %0.sub159 S_NOP 0, implicit-def %0.sub360 %1 = COPY %061 S_NOP 0, implicit %162 63 S_NOP 0, implicit-def %1.sub064 S_NOP 0, implicit %1.sub165 S_NOP 0, implicit %1.sub066 67 bb.2:68 S_NOP 0, implicit %0.sub269 70...71# In this test, there are two pairs of tied operands72# within the inline asm statement:73# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub174# Check that renaming (2) does not inadvertently rename (1).75# CHECK-LABEL: name: test276# CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0, 1245194 /* regdef:VGPR_32 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)77name: test278body: |79 bb.0:80 undef %0.sub0:vreg_64 = IMPLICIT_DEF81 82 bb.1:83 undef %0.sub1:vreg_64 = V_ALIGNBIT_B32_e64 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec84 INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0:vreg_64, 1245194 /* regdef:VGPR_32 */, def %0.sub1:vreg_64, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0:vreg_64(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %0.sub1:vreg_64(tied-def 5)85 S_BRANCH %bb.186 87...88