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1; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s4; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s5 6; GCN-LABEL: {{^}}vgpr:7; GCN-DAG: v_mov_b32_e32 v1, v08; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm9; GCN: s_waitcnt expcnt(0)10; GCN: v_add_f32_e32 v0, 1.0, v111; GCN-NOT: s_endpgm12define amdgpu_vs { float, float } @vgpr(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {13bb:14 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #015 %x = fadd float %arg3, 1.000000e+0016 %a = insertvalue { float, float } poison, float %x, 017 %b = insertvalue { float, float } %a, float %arg3, 118 ret { float, float } %b19}20 21; GCN-LABEL: {{^}}vgpr_literal:22; GCN: exp mrt0 v0, v0, v0, v0 done vm23 24; GCN-DAG: v_mov_b32_e32 v0, 1.025; GCN-DAG: v_mov_b32_e32 v1, 2.026; GCN-DAG: v_mov_b32_e32 v2, 4.027; GCN-DAG: v_mov_b32_e32 v3, -1.028; GCN-DAG: s_waitcnt expcnt(0)29; GCN-NOT: s_endpgm30define amdgpu_vs { float, float, float, float } @vgpr_literal(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {31bb:32 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #033 ret { float, float, float, float } { float 1.000000e+00, float 2.000000e+00, float 4.000000e+00, float -1.000000e+00 }34}35 36; GCN: .long 16558037; GCN-NEXT: .long 56238; GCN-NEXT: .long 16558439; GCN-NEXT: .long 56240; GCN-LABEL: {{^}}vgpr_ps_addr0:41; GCN-NOT: v_mov_b32_e32 v042; GCN-NOT: v_mov_b32_e32 v143; GCN-NOT: v_mov_b32_e32 v244; GCN: v_mov_b32_e32 v3, v445; GCN: v_mov_b32_e32 v4, v646; GCN-NOT: s_endpgm47define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr0(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {48bb:49 %i0 = extractelement <2 x i32> %arg4, i32 050 %i1 = extractelement <2 x i32> %arg4, i32 151 %i2 = extractelement <2 x i32> %arg7, i32 052 %i3 = extractelement <2 x i32> %arg8, i32 053 %f0 = bitcast i32 %i0 to float54 %f1 = bitcast i32 %i1 to float55 %f2 = bitcast i32 %i2 to float56 %f3 = bitcast i32 %i3 to float57 %r0 = insertvalue { float, float, float, float, float } poison, float %f0, 058 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 159 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 260 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 361 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 462 ret { float, float, float, float, float } %r463}64 65; GCN: .long 16558066; GCN-NEXT: .long 167; GCN-NEXT: .long 16558468; GCN-NEXT: .long 169; GCN-LABEL: {{^}}ps_input_ena_no_inputs:70; GCN: v_mov_b32_e32 v0, 1.071; GCN-NOT: s_endpgm72define amdgpu_ps float @ps_input_ena_no_inputs(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {73bb:74 ret float 1.000000e+0075}76 77; GCN: .long 16558078; GCN-NEXT: .long 208179; GCN-NEXT: .long 16558480; GCN-NEXT: .long 208181; GCN-LABEL: {{^}}ps_input_ena_pos_w:82; GCN-DAG: v_mov_b32_e32 v0, v483; GCN-DAG: v_mov_b32_e32 v1, v284; GCN-DAG: v_mov_b32_e32 v2, v385; GCN-NOT: s_endpgm86define amdgpu_ps { float, <2 x float> } @ps_input_ena_pos_w(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {87bb:88 %f = bitcast <2 x i32> %arg8 to <2 x float>89 %s = insertvalue { float, <2 x float> } poison, float %arg14, 090 %s1 = insertvalue { float, <2 x float> } %s, <2 x float> %f, 191 ret { float, <2 x float> } %s192}93 94; GCN: .long 16558095; GCN-NEXT: .long 56296; GCN-NEXT: .long 16558497; GCN-NEXT: .long 56398; GCN-LABEL: {{^}}vgpr_ps_addr1:99; GCN-DAG: v_mov_b32_e32 v0, v2100; GCN-DAG: v_mov_b32_e32 v1, v3101; GCN: v_mov_b32_e32 v2, v4102; GCN-DAG: v_mov_b32_e32 v3, v6103; GCN-DAG: v_mov_b32_e32 v4, v8104; GCN-NOT: s_endpgm105define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr1(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #2 {106bb:107 %i0 = extractelement <2 x i32> %arg4, i32 0108 %i1 = extractelement <2 x i32> %arg4, i32 1109 %i2 = extractelement <2 x i32> %arg7, i32 0110 %i3 = extractelement <2 x i32> %arg8, i32 0111 %f0 = bitcast i32 %i0 to float112 %f1 = bitcast i32 %i1 to float113 %f2 = bitcast i32 %i2 to float114 %f3 = bitcast i32 %i3 to float115 %r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0116 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1117 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2118 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3119 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4120 ret { float, float, float, float, float } %r4121}122 123; GCN: .long 165580124; GCN-NEXT: .long 562125; GCN-NEXT: .long 165584126; GCN-NEXT: .long 631127; GCN-LABEL: {{^}}vgpr_ps_addr119:128; GCN-DAG: v_mov_b32_e32 v0, v2129; GCN-DAG: v_mov_b32_e32 v1, v3130; GCN-DAG: v_mov_b32_e32 v2, v6131; GCN-DAG: v_mov_b32_e32 v3, v8132; GCN-DAG: v_mov_b32_e32 v4, v12133; GCN-NOT: s_endpgm134define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 {135bb:136 %i0 = extractelement <2 x i32> %arg4, i32 0137 %i1 = extractelement <2 x i32> %arg4, i32 1138 %i2 = extractelement <2 x i32> %arg7, i32 0139 %i3 = extractelement <2 x i32> %arg8, i32 0140 %f0 = bitcast i32 %i0 to float141 %f1 = bitcast i32 %i1 to float142 %f2 = bitcast i32 %i2 to float143 %f3 = bitcast i32 %i3 to float144 %r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0145 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1146 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2147 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3148 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4149 ret { float, float, float, float, float } %r4150}151 152; GCN: .long 165580153; GCN-NEXT: .long 562154; GCN-NEXT: .long 165584155; GCN-NEXT: .long 946156; GCN-LABEL: {{^}}vgpr_ps_addr418:157; GCN-NOT: v_mov_b32_e32 v0158; GCN-NOT: v_mov_b32_e32 v1159; GCN-NOT: v_mov_b32_e32 v2160; GCN: v_mov_b32_e32 v3, v4161; GCN: v_mov_b32_e32 v4, v8162; GCN-NOT: s_endpgm163define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr418(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #4 {164bb:165 %i0 = extractelement <2 x i32> %arg4, i32 0166 %i1 = extractelement <2 x i32> %arg4, i32 1167 %i2 = extractelement <2 x i32> %arg7, i32 0168 %i3 = extractelement <2 x i32> %arg8, i32 0169 %f0 = bitcast i32 %i0 to float170 %f1 = bitcast i32 %i1 to float171 %f2 = bitcast i32 %i2 to float172 %f3 = bitcast i32 %i3 to float173 %r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0174 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1175 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2176 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3177 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4178 ret { float, float, float, float, float } %r4179}180 181; GCN-LABEL: {{^}}sgpr:182; GCN-DAG: s_mov_b32 s2, s3183; GCN-DAG: s_add_{{i|u}}32 s0, s3, 2184; GCN-NOT: s_endpgm185define amdgpu_vs { i32, i32, i32 } @sgpr(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {186bb:187 %x = add i32 %arg2, 2188 %a = insertvalue { i32, i32, i32 } poison, i32 %x, 0189 %b = insertvalue { i32, i32, i32 } %a, i32 %arg1, 1190 %c = insertvalue { i32, i32, i32 } %a, i32 %arg2, 2191 ret { i32, i32, i32 } %c192}193 194; GCN-LABEL: {{^}}sgpr_literal:195; GCN: s_mov_b32 s0, 5196; GCN-NOT: s_mov_b32 s0, s0197; GCN-DAG: s_mov_b32 s1, 6198; GCN-DAG: s_mov_b32 s2, 7199; GCN-DAG: s_mov_b32 s3, 8200; GCN-NOT: s_endpgm201define amdgpu_vs { i32, i32, i32, i32 } @sgpr_literal(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {202bb:203 %x = add i32 %arg2, 2204 ret { i32, i32, i32, i32 } { i32 5, i32 6, i32 7, i32 8 }205}206 207; GCN-LABEL: {{^}}both:208; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm209; GCN-DAG: v_mov_b32_e32 v1, v0210; GCN-DAG: s_mov_b32 s1, s2211; GCN-DAG: s_waitcnt expcnt(0)212; GCN-DAG: v_add_f32_e32 v0, 1.0, v1213; GCN-DAG: s_add_{{i|u}}32 s0, s3, 2214; GCN-DAG: s_mov_b32 s2, s3215; GCN-NOT: s_endpgm216define amdgpu_vs { float, i32, float, i32, i32 } @both(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {217bb:218 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0219 %v = fadd float %arg3, 1.000000e+00220 %s = add i32 %arg2, 2221 %a0 = insertvalue { float, i32, float, i32, i32 } poison, float %v, 0222 %a1 = insertvalue { float, i32, float, i32, i32 } %a0, i32 %s, 1223 %a2 = insertvalue { float, i32, float, i32, i32 } %a1, float %arg3, 2224 %a3 = insertvalue { float, i32, float, i32, i32 } %a2, i32 %arg1, 3225 %a4 = insertvalue { float, i32, float, i32, i32 } %a3, i32 %arg2, 4226 ret { float, i32, float, i32, i32 } %a4227}228 229; GCN-LABEL: {{^}}structure_literal:230; GCN: exp mrt0 v0, v0, v0, v0 done vm231 232; GCN-DAG: v_mov_b32_e32 v0, 1.0233; GCN-DAG: s_mov_b32 s0, 2234; GCN-DAG: s_mov_b32 s1, 3235; GCN-DAG: v_mov_b32_e32 v1, 2.0236; GCN-DAG: v_mov_b32_e32 v2, 4.0237; GCN-DAG: s_waitcnt expcnt(0)238define amdgpu_vs { { float, i32 }, { i32, <2 x float> } } @structure_literal(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {239bb:240 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0241 ret { { float, i32 }, { i32, <2 x float> } } { { float, i32 } { float 1.000000e+00, i32 2 }, { i32, <2 x float> } { i32 3, <2 x float> <float 2.000000e+00, float 4.000000e+00> } }242}243 244; GCN-LABEL: {{^}}ret_return_to_epilog_pseudo_size:245; GCN: codeLenInByte = 0{{$}}246define amdgpu_ps float @ret_return_to_epilog_pseudo_size() #0 {247 ret float poison248}249 250declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0251 252attributes #0 = { nounwind }253attributes #1 = { nounwind "InitialPSInputAddr"="0" }254attributes #2 = { nounwind "InitialPSInputAddr"="1" }255attributes #3 = { nounwind "InitialPSInputAddr"="119" }256attributes #4 = { nounwind "InitialPSInputAddr"="418" }257