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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s3 4; This should end with an no-op sequence of exec mask manipulations5; Mask should be in original state after executed unreachable block6 7 8; GCN-LABEL: {{^}}uniform_br_trivial_ret_divergent_br_trivial_unreachable:9; GCN: s_cbranch_scc1 [[RET_BB:.LBB[0-9]+_[0-9]+]]10 11; GCN-NEXT: ; %else12 13; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc14 15; GCN: ; %bb.{{[0-9]+}}: ; %unreachable.bb16; GCN-NEXT: ; divergent unreachable17 18; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %Flow19; GCN-NEXT: s_or_b64 exec, exec20 21; GCN-NEXT: [[RET_BB]]:22; GCN-NEXT: ; return23; GCN-NEXT: .Lfunc_end024define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_trivial_ret_divergent_br_trivial_unreachable(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, i32 inreg %arg17, i32 %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {25entry:26 %i.i = extractelement <2 x i32> %arg7, i32 027 %j.i = extractelement <2 x i32> %arg7, i32 128 %i.f.i = bitcast i32 %i.i to float29 %j.f.i = bitcast i32 %j.i to float30 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #231 %p2 = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #232 %p87 = fmul float %p2, %p233 %p88 = fadd float %p87, %p8734 %p93 = fadd float %p88, %p8835 %p97 = fmul float %p93, %p9336 %p102 = fsub float %p97, %p9737 %p104 = fmul float %p102, %p10238 %p106 = fadd float 0.000000e+00, %p10439 %p108 = fadd float %p106, %p10640 %uniform.cond = icmp slt i32 %arg17, 041 br i1 %uniform.cond, label %ret.bb, label %else42 43else: ; preds = %main_body44 %p124 = fmul float %p108, %p10845 %p125 = fsub float %p124, %p12446 %divergent.cond = fcmp olt float %p125, 0.000000e+0047 br i1 %divergent.cond, label %ret.bb, label %unreachable.bb48 49unreachable.bb: ; preds = %else50 unreachable51 52ret.bb: ; preds = %else, %main_body53 ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison54}55 56; GCN-LABEL: {{^}}uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable:57; GCN: s_cbranch_vccz58 59; GCN: ; %bb.{{[0-9]+}}: ; %Flow60; GCN: s_cbranch_execnz [[RETURN:.LBB[0-9]+_[0-9]+]]61 62; GCN: ; %UnifiedReturnBlock63; GCN-NEXT: s_or_b64 exec, exec64; GCN-NEXT: s_waitcnt65 66; GCN: .LBB{{[0-9]+_[0-9]+}}: ; %else67; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc68 69; GCN-NEXT: ; %unreachable.bb70; GCN: ds_write_b3271; GCN: ; divergent unreachable72 73; GCN: ; %ret.bb74; GCN: store_dword75define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {76main_body:77 %i.i = extractelement <2 x i32> %arg7, i32 078 %j.i = extractelement <2 x i32> %arg7, i32 179 %i.f.i = bitcast i32 %i.i to float80 %j.f.i = bitcast i32 %j.i to float81 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #282 %p2 = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #283 %p87 = fmul float %p2, %p284 %p88 = fadd float %p87, %p8785 %p93 = fadd float %p88, %p8886 %p97 = fmul float %p93, %p9387 %p102 = fsub float %p97, %p9788 %p104 = fmul float %p102, %p10289 %p106 = fadd float 0.000000e+00, %p10490 %p108 = fadd float %p106, %p10691 %uniform.cond = icmp slt i32 %arg18, 092 br i1 %uniform.cond, label %ret.bb, label %else93 94else: ; preds = %main_body95 %p124 = fmul float %p108, %p10896 %p125 = fsub float %p124, %p12497 %divergent.cond = fcmp olt float %p125, 0.000000e+0098 br i1 %divergent.cond, label %ret.bb, label %unreachable.bb99 100unreachable.bb: ; preds = %else101 store volatile i32 8, ptr addrspace(3) poison102 unreachable103 104ret.bb: ; preds = %else, %main_body105 store volatile i32 11, ptr addrspace(1) poison106 ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison107}108 109; Function Attrs: nounwind readnone110declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1111 112; Function Attrs: nounwind readnone113declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1114 115; Function Attrs: nounwind readnone116declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1117 118; Function Attrs: nounwind readnone119declare float @llvm.fabs.f32(float) #1120 121; Function Attrs: nounwind readnone122declare float @llvm.sqrt.f32(float) #1123 124; Function Attrs: nounwind readnone125declare float @llvm.floor.f32(float) #1126 127attributes #0 = { "InitialPSInputAddr"="36983" }128attributes #1 = { nounwind readnone }129attributes #2 = { nounwind }130