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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s4---5name: test_subregs_composition_vreg_10246tracksRegLiveness: true7body: |8 bb.0:9 ; CHECK-LABEL: name: test_subregs_composition_vreg_102410 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec11 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec12 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub113 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1_sub214 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec15 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec16 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub217 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1_sub2_sub318 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec19 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec20 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub321 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub1_sub2_sub3_sub422 ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec23 ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec24 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub425 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub1_sub2_sub3_sub4_sub526 ; CHECK-NEXT: undef [[V_MOV_B32_e32_4:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec27 ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec28 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub0_sub1_sub2_sub3_sub4_sub529 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub2_sub3_sub4_sub5_sub6_sub730 undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec31 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec32 S_NOP 0, implicit %0.sub1_sub233 S_NOP 0, implicit %0.sub2_sub334 35 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec36 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec37 S_NOP 0, implicit %1.sub1_sub2_sub338 S_NOP 0, implicit %1.sub2_sub3_sub439 40 undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec41 %2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec42 S_NOP 0, implicit %2.sub1_sub2_sub3_sub443 S_NOP 0, implicit %2.sub2_sub3_sub4_sub544 45 undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec46 %3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec47 S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub548 S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub649 50 undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec51 %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec52 S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub653 S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub854 55...56---57name: test_vreg_64_w3258tracksRegLiveness: true59body: |60 bb.0:61 ; CHECK-LABEL: name: test_vreg_64_w3262 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec63 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]64 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec65 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]66 undef %0.sub0:vreg_64 = V_MOV_B32_e32 00, implicit $exec67 S_NOP 0, implicit %0.sub068 69 undef %1.sub1:vreg_64 = V_MOV_B32_e32 11, implicit $exec70 S_NOP 0, implicit %1.sub171 72...73---74name: test_vreg_96_w3275tracksRegLiveness: true76body: |77 bb.0:78 ; CHECK-LABEL: name: test_vreg_96_w3279 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec80 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]81 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec82 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]83 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 22, implicit $exec84 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]85 undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec86 S_NOP 0, implicit %0.sub087 88 undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec89 S_NOP 0, implicit %1.sub190 91 undef %2.sub2:vreg_96 = V_MOV_B32_e32 22, implicit $exec92 S_NOP 0, implicit %2.sub293 94...95---96name: test_vreg_96_w6497tracksRegLiveness: true98body: |99 bb.0:100 ; CHECK-LABEL: name: test_vreg_96_w64101 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec102 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec103 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]104 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec105 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec106 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]107 undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec108 %0.sub1:vreg_96 = V_MOV_B32_e32 01, implicit $exec109 S_NOP 0, implicit %0.sub0_sub1110 111 undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec112 %1.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec113 S_NOP 0, implicit %1.sub1_sub2114 115...116---117name: test_vreg_128_w32118tracksRegLiveness: true119body: |120 bb.0:121 ; CHECK-LABEL: name: test_vreg_128_w32122 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec123 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]124 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec125 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]126 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 23, implicit $exec127 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]128 undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec129 S_NOP 0, implicit %0.sub0130 131 undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec132 S_NOP 0, implicit %1.sub1133 134 undef %2.sub3:vreg_128 = V_MOV_B32_e32 23, implicit $exec135 S_NOP 0, implicit %2.sub3136 137...138---139name: test_vreg_128_w64140tracksRegLiveness: true141body: |142 bb.0:143 ; CHECK-LABEL: name: test_vreg_128_w64144 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec145 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec146 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]147 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec148 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec149 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]150 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 22, implicit $exec151 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 23, implicit $exec152 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]153 undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec154 %0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec155 S_NOP 0, implicit %0.sub0_sub1156 157 undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec158 %1.sub2:vreg_128 = V_MOV_B32_e32 12, implicit $exec159 S_NOP 0, implicit %1.sub1_sub2160 161 undef %2.sub2:vreg_128 = V_MOV_B32_e32 22, implicit $exec162 %2.sub3:vreg_128 = V_MOV_B32_e32 23, implicit $exec163 S_NOP 0, implicit %2.sub2_sub3164 165...166---167name: test_vreg_128_w96168tracksRegLiveness: true169body: |170 bb.0:171 ; CHECK-LABEL: name: test_vreg_128_w96172 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec173 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec174 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec175 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]176 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec177 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec178 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec179 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]180 undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec181 %0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec182 %0.sub2:vreg_128 = V_MOV_B32_e32 02, implicit $exec183 S_NOP 0, implicit %0.sub0_sub1_sub2184 185 undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec186 %1.sub2:vreg_128 = V_MOV_B32_e32 12, implicit $exec187 %1.sub3:vreg_128 = V_MOV_B32_e32 13, implicit $exec188 S_NOP 0, implicit %1.sub1_sub2_sub3189 190...191---192name: test_vreg_160_w32193tracksRegLiveness: true194body: |195 bb.0:196 ; CHECK-LABEL: name: test_vreg_160_w32197 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec198 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]199 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec200 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]201 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 24, implicit $exec202 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]203 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec204 S_NOP 0, implicit %0.sub0205 206 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec207 S_NOP 0, implicit %1.sub1208 209 undef %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec210 S_NOP 0, implicit %2.sub4211 212...213---214name: test_vreg_160_w64215tracksRegLiveness: true216body: |217 bb.0:218 ; CHECK-LABEL: name: test_vreg_160_w64219 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec220 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec221 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]222 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec223 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec224 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]225 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 23, implicit $exec226 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 24, implicit $exec227 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]228 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec229 %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec230 S_NOP 0, implicit %0.sub0_sub1231 232 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec233 %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec234 S_NOP 0, implicit %1.sub1_sub2235 236 undef %2.sub3:vreg_160 = V_MOV_B32_e32 23, implicit $exec237 %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec238 S_NOP 0, implicit %2.sub3_sub4239 240...241---242name: test_vreg_160_w96243tracksRegLiveness: true244body: |245 bb.0:246 ; CHECK-LABEL: name: test_vreg_160_w96247 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec248 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec249 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec250 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]251 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec252 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec253 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec254 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]255 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 22, implicit $exec256 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 23, implicit $exec257 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 24, implicit $exec258 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]259 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec260 %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec261 %0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec262 S_NOP 0, implicit %0.sub0_sub1_sub2263 264 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec265 %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec266 %1.sub3:vreg_160 = V_MOV_B32_e32 13, implicit $exec267 S_NOP 0, implicit %1.sub1_sub2_sub3268 269 undef %2.sub2:vreg_160 = V_MOV_B32_e32 22, implicit $exec270 %2.sub3:vreg_160 = V_MOV_B32_e32 23, implicit $exec271 %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec272 S_NOP 0, implicit %2.sub2_sub3_sub4273 274...275---276name: test_vreg_160_w128277tracksRegLiveness: true278body: |279 bb.0:280 ; CHECK-LABEL: name: test_vreg_160_w128281 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec282 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec283 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec284 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec285 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]286 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec287 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec288 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec289 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec290 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]291 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec292 %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec293 %0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec294 %0.sub3:vreg_160 = V_MOV_B32_e32 03, implicit $exec295 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3296 297 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec298 %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec299 %1.sub3:vreg_160 = V_MOV_B32_e32 13, implicit $exec300 %1.sub4:vreg_160 = V_MOV_B32_e32 14, implicit $exec301 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4302 303...304---305name: test_vreg_192_w32306tracksRegLiveness: true307body: |308 bb.0:309 ; CHECK-LABEL: name: test_vreg_192_w32310 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec311 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]312 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec313 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]314 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 25, implicit $exec315 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]316 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec317 S_NOP 0, implicit %0.sub0318 319 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec320 S_NOP 0, implicit %1.sub1321 322 undef %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec323 S_NOP 0, implicit %2.sub5324 325...326---327name: test_vreg_192_w64328tracksRegLiveness: true329body: |330 bb.0:331 ; CHECK-LABEL: name: test_vreg_192_w64332 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec333 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec334 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]335 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec336 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec337 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]338 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 24, implicit $exec339 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 25, implicit $exec340 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]341 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec342 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec343 S_NOP 0, implicit %0.sub0_sub1344 345 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec346 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec347 S_NOP 0, implicit %1.sub1_sub2348 349 undef %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec350 %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec351 S_NOP 0, implicit %2.sub4_sub5352 353...354---355name: test_vreg_192_w96356tracksRegLiveness: true357body: |358 bb.0:359 ; CHECK-LABEL: name: test_vreg_192_w96360 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec361 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec362 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec363 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]364 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec365 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec366 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec367 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]368 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 23, implicit $exec369 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 24, implicit $exec370 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 25, implicit $exec371 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]372 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec373 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec374 %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec375 S_NOP 0, implicit %0.sub0_sub1_sub2376 377 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec378 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec379 %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec380 S_NOP 0, implicit %1.sub1_sub2_sub3381 382 undef %2.sub3:vreg_192 = V_MOV_B32_e32 23, implicit $exec383 %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec384 %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec385 S_NOP 0, implicit %2.sub3_sub4_sub5386 387...388---389name: test_vreg_192_w128390tracksRegLiveness: true391body: |392 bb.0:393 ; CHECK-LABEL: name: test_vreg_192_w128394 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec395 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec396 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec397 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec398 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]399 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec400 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec401 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec402 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec403 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]404 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 22, implicit $exec405 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 23, implicit $exec406 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 24, implicit $exec407 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 25, implicit $exec408 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]409 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec410 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec411 %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec412 %0.sub3:vreg_192 = V_MOV_B32_e32 03, implicit $exec413 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3414 415 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec416 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec417 %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec418 %1.sub4:vreg_192 = V_MOV_B32_e32 14, implicit $exec419 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4420 421 undef %2.sub2:vreg_192 = V_MOV_B32_e32 22, implicit $exec422 %2.sub3:vreg_192 = V_MOV_B32_e32 23, implicit $exec423 %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec424 %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec425 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5426 427...428---429name: test_vreg_192_w160430tracksRegLiveness: true431body: |432 bb.0:433 ; CHECK-LABEL: name: test_vreg_192_w160434 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec435 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec436 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec437 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec438 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec439 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]440 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec441 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec442 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec443 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec444 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec445 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]446 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec447 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec448 %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec449 %0.sub3:vreg_192 = V_MOV_B32_e32 03, implicit $exec450 %0.sub4:vreg_192 = V_MOV_B32_e32 04, implicit $exec451 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4452 453 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec454 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec455 %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec456 %1.sub4:vreg_192 = V_MOV_B32_e32 14, implicit $exec457 %1.sub5:vreg_192 = V_MOV_B32_e32 15, implicit $exec458 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5459 460...461---462name: test_vreg_224_w32463tracksRegLiveness: true464body: |465 bb.0:466 ; CHECK-LABEL: name: test_vreg_224_w32467 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec468 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]469 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec470 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]471 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 26, implicit $exec472 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]473 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec474 S_NOP 0, implicit %0.sub0475 476 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec477 S_NOP 0, implicit %1.sub1478 479 undef %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec480 S_NOP 0, implicit %2.sub6481 482...483---484name: test_vreg_224_w64485tracksRegLiveness: true486body: |487 bb.0:488 ; CHECK-LABEL: name: test_vreg_224_w64489 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec490 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec491 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]492 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec493 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec494 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]495 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 25, implicit $exec496 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 26, implicit $exec497 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]498 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec499 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec500 S_NOP 0, implicit %0.sub0_sub1501 502 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec503 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec504 S_NOP 0, implicit %1.sub1_sub2505 506 undef %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec507 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec508 S_NOP 0, implicit %2.sub5_sub6509 510...511---512name: test_vreg_224_w96513tracksRegLiveness: true514body: |515 bb.0:516 ; CHECK-LABEL: name: test_vreg_224_w96517 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec518 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec519 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec520 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]521 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec522 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec523 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec524 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]525 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 24, implicit $exec526 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 25, implicit $exec527 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 26, implicit $exec528 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]529 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec530 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec531 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec532 S_NOP 0, implicit %0.sub0_sub1_sub2533 534 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec535 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec536 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec537 S_NOP 0, implicit %1.sub1_sub2_sub3538 539 undef %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec540 %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec541 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec542 S_NOP 0, implicit %2.sub4_sub5_sub6543 544...545---546name: test_vreg_224_w128547tracksRegLiveness: true548body: |549 bb.0:550 ; CHECK-LABEL: name: test_vreg_224_w128551 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec552 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec553 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec554 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec555 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]556 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec557 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec558 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec559 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec560 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]561 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 23, implicit $exec562 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 24, implicit $exec563 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 25, implicit $exec564 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 26, implicit $exec565 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]566 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec567 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec568 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec569 %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec570 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3571 572 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec573 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec574 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec575 %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec576 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4577 578 undef %2.sub3:vreg_224 = V_MOV_B32_e32 23, implicit $exec579 %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec580 %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec581 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec582 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6583 584...585---586name: test_vreg_224_w160587tracksRegLiveness: true588body: |589 bb.0:590 ; CHECK-LABEL: name: test_vreg_224_w160591 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec592 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec593 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec594 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec595 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec596 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]597 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec598 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec599 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec600 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec601 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec602 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]603 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 22, implicit $exec604 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 23, implicit $exec605 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 24, implicit $exec606 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 25, implicit $exec607 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 26, implicit $exec608 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]609 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec610 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec611 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec612 %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec613 %0.sub4:vreg_224 = V_MOV_B32_e32 04, implicit $exec614 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4615 616 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec617 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec618 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec619 %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec620 %1.sub5:vreg_224 = V_MOV_B32_e32 15, implicit $exec621 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5622 623 undef %2.sub2:vreg_224 = V_MOV_B32_e32 22, implicit $exec624 %2.sub3:vreg_224 = V_MOV_B32_e32 23, implicit $exec625 %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec626 %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec627 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec628 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6629 630...631---632name: test_vreg_224_w192633tracksRegLiveness: true634body: |635 bb.0:636 ; CHECK-LABEL: name: test_vreg_224_w192637 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec638 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec639 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec640 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec641 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec642 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec643 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]644 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec645 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec646 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec647 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec648 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec649 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec650 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]651 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec652 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec653 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec654 %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec655 %0.sub4:vreg_224 = V_MOV_B32_e32 04, implicit $exec656 %0.sub5:vreg_224 = V_MOV_B32_e32 05, implicit $exec657 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5658 659 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec660 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec661 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec662 %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec663 %1.sub5:vreg_224 = V_MOV_B32_e32 15, implicit $exec664 %1.sub6:vreg_224 = V_MOV_B32_e32 16, implicit $exec665 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6666 667...668---669name: test_vreg_256_w32670tracksRegLiveness: true671body: |672 bb.0:673 ; CHECK-LABEL: name: test_vreg_256_w32674 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec675 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]676 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec677 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]678 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec679 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]680 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec681 S_NOP 0, implicit %0.sub0682 683 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec684 S_NOP 0, implicit %1.sub1685 686 undef %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec687 S_NOP 0, implicit %2.sub7688 689...690---691name: test_vreg_256_w64692tracksRegLiveness: true693body: |694 bb.0:695 ; CHECK-LABEL: name: test_vreg_256_w64696 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec697 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec698 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]699 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec700 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec701 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]702 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 26, implicit $exec703 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 27, implicit $exec704 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]705 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec706 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec707 S_NOP 0, implicit %0.sub0_sub1708 709 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec710 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec711 S_NOP 0, implicit %1.sub1_sub2712 713 undef %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec714 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec715 S_NOP 0, implicit %2.sub6_sub7716 717...718---719name: test_vreg_256_w96720tracksRegLiveness: true721body: |722 bb.0:723 ; CHECK-LABEL: name: test_vreg_256_w96724 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec725 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec726 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec727 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]728 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec729 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec730 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec731 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]732 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 25, implicit $exec733 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 26, implicit $exec734 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 27, implicit $exec735 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]736 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec737 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec738 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec739 S_NOP 0, implicit %0.sub0_sub1_sub2740 741 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec742 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec743 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec744 S_NOP 0, implicit %1.sub1_sub2_sub3745 746 undef %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec747 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec748 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec749 S_NOP 0, implicit %2.sub5_sub6_sub7750 751...752---753name: test_vreg_256_w128754tracksRegLiveness: true755body: |756 bb.0:757 ; CHECK-LABEL: name: test_vreg_256_w128758 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec759 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec760 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec761 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec762 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]763 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec764 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec765 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec766 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec767 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]768 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 24, implicit $exec769 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 25, implicit $exec770 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 26, implicit $exec771 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 27, implicit $exec772 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]773 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec774 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec775 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec776 %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec777 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3778 779 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec780 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec781 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec782 %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec783 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4784 785 undef %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec786 %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec787 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec788 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec789 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7790 791...792---793name: test_vreg_256_w160794tracksRegLiveness: true795body: |796 bb.0:797 ; CHECK-LABEL: name: test_vreg_256_w160798 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec799 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec800 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec801 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec802 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec803 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]804 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec805 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec806 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec807 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec808 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec809 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]810 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 23, implicit $exec811 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 24, implicit $exec812 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 25, implicit $exec813 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 26, implicit $exec814 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 27, implicit $exec815 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]816 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec817 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec818 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec819 %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec820 %0.sub4:vreg_256 = V_MOV_B32_e32 04, implicit $exec821 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4822 823 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec824 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec825 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec826 %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec827 %1.sub5:vreg_256 = V_MOV_B32_e32 15, implicit $exec828 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5829 830 undef %2.sub3:vreg_256 = V_MOV_B32_e32 23, implicit $exec831 %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec832 %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec833 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec834 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec835 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7836 837...838---839name: test_vreg_256_w192840tracksRegLiveness: true841body: |842 bb.0:843 ; CHECK-LABEL: name: test_vreg_256_w192844 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec845 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec846 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec847 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec848 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec849 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec850 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]851 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec852 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec853 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec854 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec855 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec856 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec857 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]858 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 22, implicit $exec859 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 23, implicit $exec860 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 24, implicit $exec861 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 25, implicit $exec862 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 26, implicit $exec863 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 27, implicit $exec864 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]865 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec866 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec867 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec868 %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec869 %0.sub4:vreg_256 = V_MOV_B32_e32 04, implicit $exec870 %0.sub5:vreg_256 = V_MOV_B32_e32 05, implicit $exec871 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5872 873 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec874 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec875 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec876 %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec877 %1.sub5:vreg_256 = V_MOV_B32_e32 15, implicit $exec878 %1.sub6:vreg_256 = V_MOV_B32_e32 16, implicit $exec879 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6880 881 undef %2.sub2:vreg_256 = V_MOV_B32_e32 22, implicit $exec882 %2.sub3:vreg_256 = V_MOV_B32_e32 23, implicit $exec883 %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec884 %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec885 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec886 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec887 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7888 889...890---891name: test_vreg_288_w32892tracksRegLiveness: true893body: |894 bb.0:895 ; CHECK-LABEL: name: test_vreg_288_w32896 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec897 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]898 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec899 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]900 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 28, implicit $exec901 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]902 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec903 S_NOP 0, implicit %0.sub0904 905 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec906 S_NOP 0, implicit %1.sub1907 908 undef %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec909 S_NOP 0, implicit %2.sub8910 911...912---913name: test_vreg_288_w64914tracksRegLiveness: true915body: |916 bb.0:917 ; CHECK-LABEL: name: test_vreg_288_w64918 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec919 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec920 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]921 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec922 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec923 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]924 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 27, implicit $exec925 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 28, implicit $exec926 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]927 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec928 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec929 S_NOP 0, implicit %0.sub0_sub1930 931 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec932 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec933 S_NOP 0, implicit %1.sub1_sub2934 935 undef %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec936 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec937 S_NOP 0, implicit %2.sub7_sub8938 939...940---941name: test_vreg_288_w96942tracksRegLiveness: true943body: |944 bb.0:945 ; CHECK-LABEL: name: test_vreg_288_w96946 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec947 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec948 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec949 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]950 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec951 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec952 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec953 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]954 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 26, implicit $exec955 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 27, implicit $exec956 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 28, implicit $exec957 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]958 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec959 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec960 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec961 S_NOP 0, implicit %0.sub0_sub1_sub2962 963 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec964 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec965 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec966 S_NOP 0, implicit %1.sub1_sub2_sub3967 968 undef %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec969 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec970 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec971 S_NOP 0, implicit %2.sub6_sub7_sub8972 973...974---975name: test_vreg_288_w128976tracksRegLiveness: true977body: |978 bb.0:979 ; CHECK-LABEL: name: test_vreg_288_w128980 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec981 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec982 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec983 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec984 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]985 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec986 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec987 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec988 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec989 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]990 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 25, implicit $exec991 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 26, implicit $exec992 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 27, implicit $exec993 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 28, implicit $exec994 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]995 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec996 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec997 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec998 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec999 S_NOP 0, implicit %0.sub0_sub1_sub2_sub31000 1001 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec1002 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec1003 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec1004 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec1005 S_NOP 0, implicit %1.sub1_sub2_sub3_sub41006 1007 undef %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec1008 %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec1009 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec1010 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec1011 S_NOP 0, implicit %2.sub5_sub6_sub7_sub81012 1013...1014---1015name: test_vreg_288_w1601016tracksRegLiveness: true1017body: |1018 bb.0:1019 ; CHECK-LABEL: name: test_vreg_288_w1601020 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec1021 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec1022 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec1023 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec1024 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec1025 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1026 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec1027 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec1028 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec1029 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec1030 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec1031 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1032 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 24, implicit $exec1033 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 25, implicit $exec1034 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 26, implicit $exec1035 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 27, implicit $exec1036 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 28, implicit $exec1037 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1038 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec1039 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec1040 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec1041 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec1042 %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec1043 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub41044 1045 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec1046 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec1047 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec1048 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec1049 %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec1050 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub51051 1052 undef %2.sub4:vreg_288 = V_MOV_B32_e32 24, implicit $exec1053 %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec1054 %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec1055 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec1056 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec1057 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub81058 1059...1060---1061name: test_vreg_288_w1921062tracksRegLiveness: true1063body: |1064 bb.0:1065 ; CHECK-LABEL: name: test_vreg_288_w1921066 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec1067 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec1068 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec1069 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec1070 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec1071 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec1072 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1073 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec1074 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec1075 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec1076 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec1077 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec1078 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec1079 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1080 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 23, implicit $exec1081 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 24, implicit $exec1082 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 25, implicit $exec1083 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 26, implicit $exec1084 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 27, implicit $exec1085 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 28, implicit $exec1086 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1087 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec1088 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec1089 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec1090 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec1091 %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec1092 %0.sub5:vreg_288 = V_MOV_B32_e32 05, implicit $exec1093 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub51094 1095 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec1096 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec1097 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec1098 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec1099 %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec1100 %1.sub6:vreg_288 = V_MOV_B32_e32 16, implicit $exec1101 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub61102 1103 undef %2.sub3:vreg_288 = V_MOV_B32_e32 23, implicit $exec1104 %2.sub4:vreg_288 = V_MOV_B32_e32 24, implicit $exec1105 %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec1106 %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec1107 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec1108 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec1109 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7_sub81110 1111...1112---1113name: test_vreg_288_w2561114tracksRegLiveness: true1115body: |1116 bb.0:1117 ; CHECK-LABEL: name: test_vreg_288_w2561118 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec1119 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec1120 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec1121 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec1122 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec1123 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec1124 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec1125 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec1126 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1127 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec1128 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec1129 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec1130 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec1131 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec1132 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec1133 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec1134 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec1135 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1136 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec1137 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec1138 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec1139 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec1140 %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec1141 %0.sub5:vreg_288 = V_MOV_B32_e32 05, implicit $exec1142 %0.sub6:vreg_288 = V_MOV_B32_e32 06, implicit $exec1143 %0.sub7:vreg_288 = V_MOV_B32_e32 07, implicit $exec1144 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub71145 1146 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec1147 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec1148 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec1149 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec1150 %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec1151 %1.sub6:vreg_288 = V_MOV_B32_e32 16, implicit $exec1152 %1.sub7:vreg_288 = V_MOV_B32_e32 17, implicit $exec1153 %1.sub8:vreg_288 = V_MOV_B32_e32 18, implicit $exec1154 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub81155 1156...1157---1158name: test_vreg_320_w321159tracksRegLiveness: true1160body: |1161 bb.0:1162 ; CHECK-LABEL: name: test_vreg_320_w321163 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec1164 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1165 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec1166 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1167 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 29, implicit $exec1168 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1169 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1170 S_NOP 0, implicit %0.sub01171 1172 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1173 S_NOP 0, implicit %1.sub11174 1175 undef %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1176 S_NOP 0, implicit %2.sub91177 1178...1179---1180name: test_vreg_320_w641181tracksRegLiveness: true1182body: |1183 bb.0:1184 ; CHECK-LABEL: name: test_vreg_320_w641185 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec1186 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec1187 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1188 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec1189 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec1190 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1191 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 28, implicit $exec1192 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 29, implicit $exec1193 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1194 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1195 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec1196 S_NOP 0, implicit %0.sub0_sub11197 1198 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1199 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec1200 S_NOP 0, implicit %1.sub1_sub21201 1202 undef %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec1203 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1204 S_NOP 0, implicit %2.sub8_sub91205 1206...1207---1208name: test_vreg_320_w961209tracksRegLiveness: true1210body: |1211 bb.0:1212 ; CHECK-LABEL: name: test_vreg_320_w961213 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec1214 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec1215 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec1216 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1217 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec1218 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec1219 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec1220 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1221 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 27, implicit $exec1222 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 28, implicit $exec1223 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 29, implicit $exec1224 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1225 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1226 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec1227 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec1228 S_NOP 0, implicit %0.sub0_sub1_sub21229 1230 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1231 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec1232 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec1233 S_NOP 0, implicit %1.sub1_sub2_sub31234 1235 undef %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec1236 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec1237 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1238 S_NOP 0, implicit %2.sub7_sub8_sub91239 1240...1241---1242name: test_vreg_320_w1281243tracksRegLiveness: true1244body: |1245 bb.0:1246 ; CHECK-LABEL: name: test_vreg_320_w1281247 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec1248 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec1249 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec1250 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec1251 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1252 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec1253 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec1254 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec1255 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec1256 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1257 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 26, implicit $exec1258 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 27, implicit $exec1259 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 28, implicit $exec1260 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 29, implicit $exec1261 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1262 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1263 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec1264 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec1265 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec1266 S_NOP 0, implicit %0.sub0_sub1_sub2_sub31267 1268 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1269 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec1270 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec1271 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec1272 S_NOP 0, implicit %1.sub1_sub2_sub3_sub41273 1274 undef %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec1275 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec1276 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec1277 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1278 S_NOP 0, implicit %2.sub6_sub7_sub8_sub91279 1280...1281---1282name: test_vreg_320_w1601283tracksRegLiveness: true1284body: |1285 bb.0:1286 ; CHECK-LABEL: name: test_vreg_320_w1601287 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec1288 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec1289 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec1290 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec1291 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec1292 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1293 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec1294 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec1295 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec1296 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec1297 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec1298 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1299 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 25, implicit $exec1300 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 26, implicit $exec1301 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 27, implicit $exec1302 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 28, implicit $exec1303 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 29, implicit $exec1304 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1305 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1306 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec1307 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec1308 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec1309 %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec1310 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub41311 1312 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1313 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec1314 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec1315 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec1316 %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec1317 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub51318 1319 undef %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec1320 %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec1321 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec1322 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec1323 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1324 S_NOP 0, implicit %2.sub5_sub6_sub7_sub8_sub91325 1326...1327---1328name: test_vreg_320_w1921329tracksRegLiveness: true1330body: |1331 bb.0:1332 ; CHECK-LABEL: name: test_vreg_320_w1921333 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec1334 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec1335 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec1336 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec1337 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec1338 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec1339 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1340 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec1341 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec1342 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec1343 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec1344 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec1345 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec1346 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1347 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 24, implicit $exec1348 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 25, implicit $exec1349 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 26, implicit $exec1350 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 27, implicit $exec1351 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 28, implicit $exec1352 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 29, implicit $exec1353 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1354 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1355 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec1356 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec1357 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec1358 %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec1359 %0.sub5:vreg_320 = V_MOV_B32_e32 05, implicit $exec1360 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub51361 1362 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1363 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec1364 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec1365 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec1366 %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec1367 %1.sub6:vreg_320 = V_MOV_B32_e32 16, implicit $exec1368 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub61369 1370 undef %2.sub4:vreg_320 = V_MOV_B32_e32 24, implicit $exec1371 %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec1372 %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec1373 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec1374 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec1375 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1376 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub91377 1378...1379---1380name: test_vreg_320_w2561381tracksRegLiveness: true1382body: |1383 bb.0:1384 ; CHECK-LABEL: name: test_vreg_320_w2561385 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec1386 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec1387 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec1388 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec1389 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec1390 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec1391 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec1392 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec1393 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1394 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec1395 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec1396 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec1397 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec1398 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec1399 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec1400 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec1401 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec1402 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1403 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 22, implicit $exec1404 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 23, implicit $exec1405 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 24, implicit $exec1406 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 25, implicit $exec1407 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 26, implicit $exec1408 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 27, implicit $exec1409 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 28, implicit $exec1410 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 29, implicit $exec1411 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1412 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec1413 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec1414 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec1415 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec1416 %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec1417 %0.sub5:vreg_320 = V_MOV_B32_e32 05, implicit $exec1418 %0.sub6:vreg_320 = V_MOV_B32_e32 06, implicit $exec1419 %0.sub7:vreg_320 = V_MOV_B32_e32 07, implicit $exec1420 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub71421 1422 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec1423 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec1424 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec1425 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec1426 %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec1427 %1.sub6:vreg_320 = V_MOV_B32_e32 16, implicit $exec1428 %1.sub7:vreg_320 = V_MOV_B32_e32 17, implicit $exec1429 %1.sub8:vreg_320 = V_MOV_B32_e32 18, implicit $exec1430 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub81431 1432 undef %2.sub2:vreg_320 = V_MOV_B32_e32 22, implicit $exec1433 %2.sub3:vreg_320 = V_MOV_B32_e32 23, implicit $exec1434 %2.sub4:vreg_320 = V_MOV_B32_e32 24, implicit $exec1435 %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec1436 %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec1437 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec1438 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec1439 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec1440 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub91441 1442...1443---1444name: test_vreg_352_w321445tracksRegLiveness: true1446body: |1447 bb.0:1448 ; CHECK-LABEL: name: test_vreg_352_w321449 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec1450 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1451 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec1452 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1453 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 210, implicit $exec1454 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1455 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1456 S_NOP 0, implicit %0.sub01457 1458 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1459 S_NOP 0, implicit %1.sub11460 1461 undef %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1462 S_NOP 0, implicit %2.sub101463 1464...1465---1466name: test_vreg_352_w641467tracksRegLiveness: true1468body: |1469 bb.0:1470 ; CHECK-LABEL: name: test_vreg_352_w641471 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec1472 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec1473 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1474 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec1475 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec1476 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1477 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 29, implicit $exec1478 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 210, implicit $exec1479 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1480 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1481 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec1482 S_NOP 0, implicit %0.sub0_sub11483 1484 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1485 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec1486 S_NOP 0, implicit %1.sub1_sub21487 1488 undef %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec1489 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1490 S_NOP 0, implicit %2.sub9_sub101491 1492...1493---1494name: test_vreg_352_w961495tracksRegLiveness: true1496body: |1497 bb.0:1498 ; CHECK-LABEL: name: test_vreg_352_w961499 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec1500 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec1501 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec1502 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1503 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec1504 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec1505 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec1506 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1507 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 28, implicit $exec1508 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 29, implicit $exec1509 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 210, implicit $exec1510 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1511 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1512 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec1513 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec1514 S_NOP 0, implicit %0.sub0_sub1_sub21515 1516 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1517 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec1518 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec1519 S_NOP 0, implicit %1.sub1_sub2_sub31520 1521 undef %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec1522 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec1523 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1524 S_NOP 0, implicit %2.sub8_sub9_sub101525 1526...1527---1528name: test_vreg_352_w1281529tracksRegLiveness: true1530body: |1531 bb.0:1532 ; CHECK-LABEL: name: test_vreg_352_w1281533 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec1534 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec1535 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec1536 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec1537 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1538 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec1539 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec1540 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec1541 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec1542 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1543 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 27, implicit $exec1544 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 28, implicit $exec1545 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 29, implicit $exec1546 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 210, implicit $exec1547 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1548 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1549 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec1550 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec1551 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec1552 S_NOP 0, implicit %0.sub0_sub1_sub2_sub31553 1554 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1555 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec1556 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec1557 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec1558 S_NOP 0, implicit %1.sub1_sub2_sub3_sub41559 1560 undef %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec1561 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec1562 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec1563 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1564 S_NOP 0, implicit %2.sub7_sub8_sub9_sub101565 1566...1567---1568name: test_vreg_352_w1601569tracksRegLiveness: true1570body: |1571 bb.0:1572 ; CHECK-LABEL: name: test_vreg_352_w1601573 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec1574 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec1575 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec1576 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec1577 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec1578 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1579 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec1580 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec1581 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec1582 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec1583 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec1584 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1585 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 26, implicit $exec1586 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 27, implicit $exec1587 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 28, implicit $exec1588 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 29, implicit $exec1589 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 210, implicit $exec1590 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1591 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1592 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec1593 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec1594 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec1595 %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec1596 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub41597 1598 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1599 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec1600 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec1601 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec1602 %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec1603 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub51604 1605 undef %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec1606 %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec1607 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec1608 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec1609 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1610 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub101611 1612...1613---1614name: test_vreg_352_w1921615tracksRegLiveness: true1616body: |1617 bb.0:1618 ; CHECK-LABEL: name: test_vreg_352_w1921619 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec1620 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec1621 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec1622 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec1623 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec1624 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec1625 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1626 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec1627 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec1628 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec1629 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec1630 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec1631 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec1632 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1633 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 25, implicit $exec1634 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 26, implicit $exec1635 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 27, implicit $exec1636 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 28, implicit $exec1637 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 29, implicit $exec1638 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 210, implicit $exec1639 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1640 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1641 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec1642 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec1643 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec1644 %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec1645 %0.sub5:vreg_352 = V_MOV_B32_e32 05, implicit $exec1646 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub51647 1648 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1649 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec1650 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec1651 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec1652 %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec1653 %1.sub6:vreg_352 = V_MOV_B32_e32 16, implicit $exec1654 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub61655 1656 undef %2.sub5:vreg_352 = V_MOV_B32_e32 25, implicit $exec1657 %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec1658 %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec1659 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec1660 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec1661 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1662 S_NOP 0, implicit %2.sub5_sub6_sub7_sub8_sub9_sub101663 1664...1665---1666name: test_vreg_352_w2561667tracksRegLiveness: true1668body: |1669 bb.0:1670 ; CHECK-LABEL: name: test_vreg_352_w2561671 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec1672 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec1673 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec1674 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec1675 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec1676 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec1677 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec1678 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec1679 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1680 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec1681 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec1682 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec1683 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec1684 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec1685 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec1686 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec1687 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec1688 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1689 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 23, implicit $exec1690 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 24, implicit $exec1691 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 25, implicit $exec1692 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 26, implicit $exec1693 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 27, implicit $exec1694 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 28, implicit $exec1695 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 29, implicit $exec1696 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 210, implicit $exec1697 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1698 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec1699 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec1700 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec1701 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec1702 %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec1703 %0.sub5:vreg_352 = V_MOV_B32_e32 05, implicit $exec1704 %0.sub6:vreg_352 = V_MOV_B32_e32 06, implicit $exec1705 %0.sub7:vreg_352 = V_MOV_B32_e32 07, implicit $exec1706 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub71707 1708 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec1709 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec1710 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec1711 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec1712 %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec1713 %1.sub6:vreg_352 = V_MOV_B32_e32 16, implicit $exec1714 %1.sub7:vreg_352 = V_MOV_B32_e32 17, implicit $exec1715 %1.sub8:vreg_352 = V_MOV_B32_e32 18, implicit $exec1716 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub81717 1718 undef %2.sub3:vreg_352 = V_MOV_B32_e32 23, implicit $exec1719 %2.sub4:vreg_352 = V_MOV_B32_e32 24, implicit $exec1720 %2.sub5:vreg_352 = V_MOV_B32_e32 25, implicit $exec1721 %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec1722 %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec1723 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec1724 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec1725 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec1726 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub101727 1728...1729---1730name: test_vreg_384_w321731tracksRegLiveness: true1732body: |1733 bb.0:1734 ; CHECK-LABEL: name: test_vreg_384_w321735 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec1736 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1737 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec1738 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1739 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 211, implicit $exec1740 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1741 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1742 S_NOP 0, implicit %0.sub01743 1744 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1745 S_NOP 0, implicit %1.sub11746 1747 undef %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec1748 S_NOP 0, implicit %2.sub111749 1750...1751---1752name: test_vreg_384_w641753tracksRegLiveness: true1754body: |1755 bb.0:1756 ; CHECK-LABEL: name: test_vreg_384_w641757 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec1758 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec1759 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1760 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec1761 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec1762 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1763 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 210, implicit $exec1764 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 211, implicit $exec1765 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1766 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1767 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec1768 S_NOP 0, implicit %0.sub0_sub11769 1770 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1771 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec1772 S_NOP 0, implicit %1.sub1_sub21773 1774 undef %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec1775 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec1776 S_NOP 0, implicit %2.sub10_sub111777 1778...1779---1780name: test_vreg_384_w961781tracksRegLiveness: true1782body: |1783 bb.0:1784 ; CHECK-LABEL: name: test_vreg_384_w961785 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec1786 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec1787 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec1788 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1789 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec1790 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec1791 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec1792 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1793 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 29, implicit $exec1794 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 210, implicit $exec1795 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 211, implicit $exec1796 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1797 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1798 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec1799 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec1800 S_NOP 0, implicit %0.sub0_sub1_sub21801 1802 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1803 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec1804 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec1805 S_NOP 0, implicit %1.sub1_sub2_sub31806 1807 undef %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec1808 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec1809 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec1810 S_NOP 0, implicit %2.sub9_sub10_sub111811 1812...1813---1814name: test_vreg_384_w1281815tracksRegLiveness: true1816body: |1817 bb.0:1818 ; CHECK-LABEL: name: test_vreg_384_w1281819 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec1820 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec1821 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec1822 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec1823 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1824 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec1825 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec1826 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec1827 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec1828 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1829 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 28, implicit $exec1830 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 29, implicit $exec1831 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 210, implicit $exec1832 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 211, implicit $exec1833 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1834 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1835 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec1836 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec1837 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec1838 S_NOP 0, implicit %0.sub0_sub1_sub2_sub31839 1840 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1841 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec1842 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec1843 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec1844 S_NOP 0, implicit %1.sub1_sub2_sub3_sub41845 1846 undef %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec1847 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec1848 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec1849 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec1850 S_NOP 0, implicit %2.sub8_sub9_sub10_sub111851 1852...1853---1854name: test_vreg_384_w1601855tracksRegLiveness: true1856body: |1857 bb.0:1858 ; CHECK-LABEL: name: test_vreg_384_w1601859 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec1860 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec1861 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec1862 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec1863 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec1864 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1865 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec1866 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec1867 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec1868 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec1869 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec1870 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1871 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 27, implicit $exec1872 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 28, implicit $exec1873 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 29, implicit $exec1874 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 210, implicit $exec1875 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 211, implicit $exec1876 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1877 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1878 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec1879 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec1880 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec1881 %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec1882 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub41883 1884 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1885 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec1886 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec1887 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec1888 %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec1889 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub51890 1891 undef %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec1892 %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec1893 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec1894 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec1895 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec1896 S_NOP 0, implicit %2.sub7_sub8_sub9_sub10_sub111897 1898...1899---1900name: test_vreg_384_w1921901tracksRegLiveness: true1902body: |1903 bb.0:1904 ; CHECK-LABEL: name: test_vreg_384_w1921905 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec1906 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec1907 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec1908 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec1909 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec1910 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec1911 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1912 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec1913 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec1914 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec1915 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec1916 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec1917 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec1918 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1919 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 26, implicit $exec1920 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 27, implicit $exec1921 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 28, implicit $exec1922 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 29, implicit $exec1923 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 210, implicit $exec1924 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 211, implicit $exec1925 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1926 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1927 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec1928 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec1929 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec1930 %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec1931 %0.sub5:vreg_384 = V_MOV_B32_e32 05, implicit $exec1932 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub51933 1934 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1935 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec1936 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec1937 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec1938 %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec1939 %1.sub6:vreg_384 = V_MOV_B32_e32 16, implicit $exec1940 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub61941 1942 undef %2.sub6:vreg_384 = V_MOV_B32_e32 26, implicit $exec1943 %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec1944 %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec1945 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec1946 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec1947 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec1948 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10_sub111949 1950...1951---1952name: test_vreg_384_w2561953tracksRegLiveness: true1954body: |1955 bb.0:1956 ; CHECK-LABEL: name: test_vreg_384_w2561957 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec1958 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec1959 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec1960 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec1961 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec1962 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec1963 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec1964 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec1965 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]1966 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec1967 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec1968 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec1969 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec1970 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec1971 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec1972 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec1973 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec1974 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]1975 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 24, implicit $exec1976 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 25, implicit $exec1977 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 26, implicit $exec1978 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 27, implicit $exec1979 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 28, implicit $exec1980 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 29, implicit $exec1981 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 210, implicit $exec1982 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 211, implicit $exec1983 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]1984 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec1985 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec1986 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec1987 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec1988 %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec1989 %0.sub5:vreg_384 = V_MOV_B32_e32 05, implicit $exec1990 %0.sub6:vreg_384 = V_MOV_B32_e32 06, implicit $exec1991 %0.sub7:vreg_384 = V_MOV_B32_e32 07, implicit $exec1992 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub71993 1994 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec1995 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec1996 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec1997 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec1998 %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec1999 %1.sub6:vreg_384 = V_MOV_B32_e32 16, implicit $exec2000 %1.sub7:vreg_384 = V_MOV_B32_e32 17, implicit $exec2001 %1.sub8:vreg_384 = V_MOV_B32_e32 18, implicit $exec2002 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub82003 2004 undef %2.sub4:vreg_384 = V_MOV_B32_e32 24, implicit $exec2005 %2.sub5:vreg_384 = V_MOV_B32_e32 25, implicit $exec2006 %2.sub6:vreg_384 = V_MOV_B32_e32 26, implicit $exec2007 %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec2008 %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec2009 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec2010 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec2011 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec2012 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub112013 2014...2015---2016name: test_vreg_512_w322017tracksRegLiveness: true2018body: |2019 bb.0:2020 ; CHECK-LABEL: name: test_vreg_512_w322021 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec2022 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2023 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec2024 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2025 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 215, implicit $exec2026 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2027 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2028 S_NOP 0, implicit %0.sub02029 2030 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2031 S_NOP 0, implicit %1.sub12032 2033 undef %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2034 S_NOP 0, implicit %2.sub152035 2036...2037---2038name: test_vreg_512_w642039tracksRegLiveness: true2040body: |2041 bb.0:2042 ; CHECK-LABEL: name: test_vreg_512_w642043 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec2044 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec2045 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2046 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec2047 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec2048 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2049 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 214, implicit $exec2050 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 215, implicit $exec2051 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2052 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2053 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec2054 S_NOP 0, implicit %0.sub0_sub12055 2056 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2057 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec2058 S_NOP 0, implicit %1.sub1_sub22059 2060 undef %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec2061 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2062 S_NOP 0, implicit %2.sub14_sub152063 2064...2065---2066name: test_vreg_512_w962067tracksRegLiveness: true2068body: |2069 bb.0:2070 ; CHECK-LABEL: name: test_vreg_512_w962071 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec2072 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec2073 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec2074 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2075 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec2076 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec2077 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec2078 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2079 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 213, implicit $exec2080 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 214, implicit $exec2081 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 215, implicit $exec2082 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2083 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2084 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec2085 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec2086 S_NOP 0, implicit %0.sub0_sub1_sub22087 2088 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2089 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec2090 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec2091 S_NOP 0, implicit %1.sub1_sub2_sub32092 2093 undef %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec2094 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec2095 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2096 S_NOP 0, implicit %2.sub13_sub14_sub152097 2098...2099---2100name: test_vreg_512_w1282101tracksRegLiveness: true2102body: |2103 bb.0:2104 ; CHECK-LABEL: name: test_vreg_512_w1282105 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec2106 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec2107 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec2108 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec2109 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2110 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec2111 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec2112 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec2113 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec2114 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2115 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 212, implicit $exec2116 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 213, implicit $exec2117 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 214, implicit $exec2118 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 215, implicit $exec2119 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2120 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2121 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec2122 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec2123 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec2124 S_NOP 0, implicit %0.sub0_sub1_sub2_sub32125 2126 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2127 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec2128 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec2129 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec2130 S_NOP 0, implicit %1.sub1_sub2_sub3_sub42131 2132 undef %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec2133 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec2134 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec2135 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2136 S_NOP 0, implicit %2.sub12_sub13_sub14_sub152137 2138...2139---2140name: test_vreg_512_w1602141tracksRegLiveness: true2142body: |2143 bb.0:2144 ; CHECK-LABEL: name: test_vreg_512_w1602145 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec2146 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec2147 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec2148 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec2149 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec2150 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2151 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec2152 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec2153 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec2154 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec2155 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec2156 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2157 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 211, implicit $exec2158 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 212, implicit $exec2159 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 213, implicit $exec2160 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 214, implicit $exec2161 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 215, implicit $exec2162 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2163 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2164 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec2165 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec2166 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec2167 %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec2168 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub42169 2170 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2171 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec2172 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec2173 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec2174 %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec2175 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub52176 2177 undef %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec2178 %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec2179 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec2180 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec2181 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2182 S_NOP 0, implicit %2.sub11_sub12_sub13_sub14_sub152183 2184...2185---2186name: test_vreg_512_w1922187tracksRegLiveness: true2188body: |2189 bb.0:2190 ; CHECK-LABEL: name: test_vreg_512_w1922191 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec2192 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec2193 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec2194 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec2195 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec2196 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec2197 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2198 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec2199 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec2200 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec2201 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec2202 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec2203 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec2204 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2205 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 210, implicit $exec2206 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 211, implicit $exec2207 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 212, implicit $exec2208 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 213, implicit $exec2209 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 214, implicit $exec2210 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 215, implicit $exec2211 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2212 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2213 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec2214 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec2215 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec2216 %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec2217 %0.sub5:vreg_512 = V_MOV_B32_e32 05, implicit $exec2218 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub52219 2220 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2221 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec2222 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec2223 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec2224 %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec2225 %1.sub6:vreg_512 = V_MOV_B32_e32 16, implicit $exec2226 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub62227 2228 undef %2.sub10:vreg_512 = V_MOV_B32_e32 210, implicit $exec2229 %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec2230 %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec2231 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec2232 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec2233 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2234 S_NOP 0, implicit %2.sub10_sub11_sub12_sub13_sub14_sub152235 2236...2237---2238name: test_vreg_512_w2562239tracksRegLiveness: true2240body: |2241 bb.0:2242 ; CHECK-LABEL: name: test_vreg_512_w2562243 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec2244 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec2245 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec2246 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec2247 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec2248 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec2249 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec2250 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec2251 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2252 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec2253 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec2254 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec2255 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec2256 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec2257 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec2258 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec2259 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec2260 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2261 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 28, implicit $exec2262 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 29, implicit $exec2263 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 210, implicit $exec2264 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 211, implicit $exec2265 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 212, implicit $exec2266 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 213, implicit $exec2267 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 214, implicit $exec2268 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 215, implicit $exec2269 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2270 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec2271 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec2272 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec2273 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec2274 %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec2275 %0.sub5:vreg_512 = V_MOV_B32_e32 05, implicit $exec2276 %0.sub6:vreg_512 = V_MOV_B32_e32 06, implicit $exec2277 %0.sub7:vreg_512 = V_MOV_B32_e32 07, implicit $exec2278 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub72279 2280 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec2281 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec2282 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec2283 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec2284 %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec2285 %1.sub6:vreg_512 = V_MOV_B32_e32 16, implicit $exec2286 %1.sub7:vreg_512 = V_MOV_B32_e32 17, implicit $exec2287 %1.sub8:vreg_512 = V_MOV_B32_e32 18, implicit $exec2288 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub82289 2290 undef %2.sub8:vreg_512 = V_MOV_B32_e32 28, implicit $exec2291 %2.sub9:vreg_512 = V_MOV_B32_e32 29, implicit $exec2292 %2.sub10:vreg_512 = V_MOV_B32_e32 210, implicit $exec2293 %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec2294 %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec2295 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec2296 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec2297 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec2298 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub152299 2300...2301---2302name: test_vreg_1024_w322303tracksRegLiveness: true2304body: |2305 bb.0:2306 ; CHECK-LABEL: name: test_vreg_1024_w322307 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec2308 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2309 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec2310 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2311 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 231, implicit $exec2312 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2313 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2314 S_NOP 0, implicit %0.sub02315 2316 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2317 S_NOP 0, implicit %1.sub12318 2319 undef %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2320 S_NOP 0, implicit %2.sub312321 2322...2323---2324name: test_vreg_1024_w642325tracksRegLiveness: true2326body: |2327 bb.0:2328 ; CHECK-LABEL: name: test_vreg_1024_w642329 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec2330 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec2331 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2332 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec2333 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec2334 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2335 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 230, implicit $exec2336 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 231, implicit $exec2337 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2338 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2339 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2340 S_NOP 0, implicit %0.sub0_sub12341 2342 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2343 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2344 S_NOP 0, implicit %1.sub1_sub22345 2346 undef %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2347 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2348 S_NOP 0, implicit %2.sub30_sub312349 2350...2351---2352name: test_vreg_1024_w962353tracksRegLiveness: true2354body: |2355 bb.0:2356 ; CHECK-LABEL: name: test_vreg_1024_w962357 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec2358 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec2359 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec2360 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2361 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec2362 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec2363 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec2364 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2365 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 229, implicit $exec2366 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 230, implicit $exec2367 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96 = V_MOV_B32_e32 231, implicit $exec2368 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2369 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2370 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2371 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec2372 S_NOP 0, implicit %0.sub0_sub1_sub22373 2374 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2375 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2376 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec2377 S_NOP 0, implicit %1.sub1_sub2_sub32378 2379 undef %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec2380 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2381 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2382 S_NOP 0, implicit %2.sub29_sub30_sub312383 2384...2385---2386name: test_vreg_1024_w1282387tracksRegLiveness: true2388body: |2389 bb.0:2390 ; CHECK-LABEL: name: test_vreg_1024_w1282391 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec2392 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec2393 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec2394 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec2395 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2396 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec2397 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec2398 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec2399 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec2400 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2401 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 228, implicit $exec2402 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 229, implicit $exec2403 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128 = V_MOV_B32_e32 230, implicit $exec2404 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128 = V_MOV_B32_e32 231, implicit $exec2405 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2406 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2407 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2408 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec2409 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec2410 S_NOP 0, implicit %0.sub0_sub1_sub2_sub32411 2412 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2413 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2414 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec2415 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec2416 S_NOP 0, implicit %1.sub1_sub2_sub3_sub42417 2418 undef %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec2419 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec2420 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2421 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2422 S_NOP 0, implicit %2.sub28_sub29_sub30_sub312423 2424...2425---2426name: test_vreg_1024_w1602427tracksRegLiveness: true2428body: |2429 bb.0:2430 ; CHECK-LABEL: name: test_vreg_1024_w1602431 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec2432 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec2433 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec2434 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec2435 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec2436 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2437 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec2438 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec2439 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec2440 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec2441 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec2442 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2443 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 227, implicit $exec2444 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 228, implicit $exec2445 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160 = V_MOV_B32_e32 229, implicit $exec2446 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160 = V_MOV_B32_e32 230, implicit $exec2447 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160 = V_MOV_B32_e32 231, implicit $exec2448 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2449 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2450 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2451 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec2452 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec2453 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec2454 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub42455 2456 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2457 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2458 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec2459 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec2460 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec2461 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub52462 2463 undef %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec2464 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec2465 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec2466 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2467 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2468 S_NOP 0, implicit %2.sub27_sub28_sub29_sub30_sub312469 2470...2471---2472name: test_vreg_1024_w1922473tracksRegLiveness: true2474body: |2475 bb.0:2476 ; CHECK-LABEL: name: test_vreg_1024_w1922477 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec2478 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec2479 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec2480 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec2481 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec2482 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec2483 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2484 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec2485 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec2486 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec2487 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec2488 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec2489 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec2490 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2491 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 226, implicit $exec2492 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 227, implicit $exec2493 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192 = V_MOV_B32_e32 228, implicit $exec2494 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192 = V_MOV_B32_e32 229, implicit $exec2495 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192 = V_MOV_B32_e32 230, implicit $exec2496 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192 = V_MOV_B32_e32 231, implicit $exec2497 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2498 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2499 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2500 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec2501 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec2502 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec2503 %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec2504 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub52505 2506 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2507 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2508 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec2509 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec2510 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec2511 %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec2512 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub62513 2514 undef %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec2515 %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec2516 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec2517 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec2518 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2519 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2520 S_NOP 0, implicit %2.sub26_sub27_sub28_sub29_sub30_sub312521 2522...2523---2524name: test_vreg_1024_w2562525tracksRegLiveness: true2526body: |2527 bb.0:2528 ; CHECK-LABEL: name: test_vreg_1024_w2562529 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec2530 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec2531 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec2532 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec2533 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec2534 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec2535 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec2536 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec2537 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2538 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec2539 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec2540 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec2541 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec2542 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec2543 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec2544 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec2545 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec2546 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2547 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 224, implicit $exec2548 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256 = V_MOV_B32_e32 225, implicit $exec2549 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 226, implicit $exec2550 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256 = V_MOV_B32_e32 227, implicit $exec2551 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256 = V_MOV_B32_e32 228, implicit $exec2552 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256 = V_MOV_B32_e32 229, implicit $exec2553 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256 = V_MOV_B32_e32 230, implicit $exec2554 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256 = V_MOV_B32_e32 231, implicit $exec2555 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2556 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2557 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2558 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec2559 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec2560 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec2561 %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec2562 %0.sub6:vreg_1024 = V_MOV_B32_e32 06, implicit $exec2563 %0.sub7:vreg_1024 = V_MOV_B32_e32 07, implicit $exec2564 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub72565 2566 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2567 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2568 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec2569 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec2570 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec2571 %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec2572 %1.sub7:vreg_1024 = V_MOV_B32_e32 17, implicit $exec2573 %1.sub8:vreg_1024 = V_MOV_B32_e32 18, implicit $exec2574 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub82575 2576 undef %2.sub24:vreg_1024 = V_MOV_B32_e32 224, implicit $exec2577 %2.sub25:vreg_1024 = V_MOV_B32_e32 225, implicit $exec2578 %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec2579 %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec2580 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec2581 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec2582 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2583 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2584 S_NOP 0, implicit %2.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub312585 2586...2587---2588name: test_vreg_1024_w5122589tracksRegLiveness: true2590body: |2591 bb.0:2592 ; CHECK-LABEL: name: test_vreg_1024_w5122593 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_512 = V_MOV_B32_e32 0, implicit $exec2594 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_512 = V_MOV_B32_e32 1, implicit $exec2595 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_512 = V_MOV_B32_e32 2, implicit $exec2596 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 3, implicit $exec2597 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_512 = V_MOV_B32_e32 4, implicit $exec2598 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec2599 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_512 = V_MOV_B32_e32 6, implicit $exec2600 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_512 = V_MOV_B32_e32 7, implicit $exec2601 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub8:vreg_512 = V_MOV_B32_e32 8, implicit $exec2602 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub9:vreg_512 = V_MOV_B32_e32 9, implicit $exec2603 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub10:vreg_512 = V_MOV_B32_e32 10, implicit $exec2604 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub11:vreg_512 = V_MOV_B32_e32 11, implicit $exec2605 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub12:vreg_512 = V_MOV_B32_e32 12, implicit $exec2606 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub13:vreg_512 = V_MOV_B32_e32 13, implicit $exec2607 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub14:vreg_512 = V_MOV_B32_e32 14, implicit $exec2608 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub15:vreg_512 = V_MOV_B32_e32 15, implicit $exec2609 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2610 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_512 = V_MOV_B32_e32 11, implicit $exec2611 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_512 = V_MOV_B32_e32 12, implicit $exec2612 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_512 = V_MOV_B32_e32 13, implicit $exec2613 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 14, implicit $exec2614 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_512 = V_MOV_B32_e32 15, implicit $exec2615 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_512 = V_MOV_B32_e32 16, implicit $exec2616 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_512 = V_MOV_B32_e32 17, implicit $exec2617 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_512 = V_MOV_B32_e32 18, implicit $exec2618 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub8:vreg_512 = V_MOV_B32_e32 19, implicit $exec2619 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub9:vreg_512 = V_MOV_B32_e32 110, implicit $exec2620 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub10:vreg_512 = V_MOV_B32_e32 111, implicit $exec2621 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub11:vreg_512 = V_MOV_B32_e32 112, implicit $exec2622 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub12:vreg_512 = V_MOV_B32_e32 113, implicit $exec2623 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub13:vreg_512 = V_MOV_B32_e32 114, implicit $exec2624 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub14:vreg_512 = V_MOV_B32_e32 115, implicit $exec2625 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub15:vreg_512 = V_MOV_B32_e32 116, implicit $exec2626 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2627 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_512 = V_MOV_B32_e32 216, implicit $exec2628 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_512 = V_MOV_B32_e32 217, implicit $exec2629 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_512 = V_MOV_B32_e32 218, implicit $exec2630 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 219, implicit $exec2631 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_512 = V_MOV_B32_e32 220, implicit $exec2632 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_512 = V_MOV_B32_e32 221, implicit $exec2633 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_512 = V_MOV_B32_e32 222, implicit $exec2634 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_512 = V_MOV_B32_e32 223, implicit $exec2635 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub8:vreg_512 = V_MOV_B32_e32 224, implicit $exec2636 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub9:vreg_512 = V_MOV_B32_e32 225, implicit $exec2637 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub10:vreg_512 = V_MOV_B32_e32 226, implicit $exec2638 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub11:vreg_512 = V_MOV_B32_e32 227, implicit $exec2639 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub12:vreg_512 = V_MOV_B32_e32 228, implicit $exec2640 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub13:vreg_512 = V_MOV_B32_e32 229, implicit $exec2641 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub14:vreg_512 = V_MOV_B32_e32 230, implicit $exec2642 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub15:vreg_512 = V_MOV_B32_e32 231, implicit $exec2643 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2644 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec2645 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec2646 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec2647 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec2648 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec2649 %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec2650 %0.sub6:vreg_1024 = V_MOV_B32_e32 06, implicit $exec2651 %0.sub7:vreg_1024 = V_MOV_B32_e32 07, implicit $exec2652 %0.sub8:vreg_1024 = V_MOV_B32_e32 08, implicit $exec2653 %0.sub9:vreg_1024 = V_MOV_B32_e32 09, implicit $exec2654 %0.sub10:vreg_1024 = V_MOV_B32_e32 010, implicit $exec2655 %0.sub11:vreg_1024 = V_MOV_B32_e32 011, implicit $exec2656 %0.sub12:vreg_1024 = V_MOV_B32_e32 012, implicit $exec2657 %0.sub13:vreg_1024 = V_MOV_B32_e32 013, implicit $exec2658 %0.sub14:vreg_1024 = V_MOV_B32_e32 014, implicit $exec2659 %0.sub15:vreg_1024 = V_MOV_B32_e32 015, implicit $exec2660 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub152661 2662 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec2663 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec2664 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec2665 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec2666 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec2667 %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec2668 %1.sub7:vreg_1024 = V_MOV_B32_e32 17, implicit $exec2669 %1.sub8:vreg_1024 = V_MOV_B32_e32 18, implicit $exec2670 %1.sub9:vreg_1024 = V_MOV_B32_e32 19, implicit $exec2671 %1.sub10:vreg_1024 = V_MOV_B32_e32 110, implicit $exec2672 %1.sub11:vreg_1024 = V_MOV_B32_e32 111, implicit $exec2673 %1.sub12:vreg_1024 = V_MOV_B32_e32 112, implicit $exec2674 %1.sub13:vreg_1024 = V_MOV_B32_e32 113, implicit $exec2675 %1.sub14:vreg_1024 = V_MOV_B32_e32 114, implicit $exec2676 %1.sub15:vreg_1024 = V_MOV_B32_e32 115, implicit $exec2677 %1.sub16:vreg_1024 = V_MOV_B32_e32 116, implicit $exec2678 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub162679 2680 undef %2.sub16:vreg_1024 = V_MOV_B32_e32 216, implicit $exec2681 %2.sub17:vreg_1024 = V_MOV_B32_e32 217, implicit $exec2682 %2.sub18:vreg_1024 = V_MOV_B32_e32 218, implicit $exec2683 %2.sub19:vreg_1024 = V_MOV_B32_e32 219, implicit $exec2684 %2.sub20:vreg_1024 = V_MOV_B32_e32 220, implicit $exec2685 %2.sub21:vreg_1024 = V_MOV_B32_e32 221, implicit $exec2686 %2.sub22:vreg_1024 = V_MOV_B32_e32 222, implicit $exec2687 %2.sub23:vreg_1024 = V_MOV_B32_e32 223, implicit $exec2688 %2.sub24:vreg_1024 = V_MOV_B32_e32 224, implicit $exec2689 %2.sub25:vreg_1024 = V_MOV_B32_e32 225, implicit $exec2690 %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec2691 %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec2692 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec2693 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec2694 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec2695 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec2696 S_NOP 0, implicit %2.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub312697 2698...2699---2700name: test_subregs_composition_vreg_1024_align22701tracksRegLiveness: true2702body: |2703 bb.0:2704 ; CHECK-LABEL: name: test_subregs_composition_vreg_1024_align22705 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec2706 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec2707 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub1_sub22708 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub2_sub3_sub42709 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec2710 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec2711 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub2_sub32712 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub2_sub3_sub4_sub52713 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_224_align2 = V_MOV_B32_e32 32, implicit $exec2714 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_224_align2 = V_MOV_B32_e32 34, implicit $exec2715 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub3_sub42716 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub2_sub3_sub4_sub5_sub62717 ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 42, implicit $exec2718 ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 44, implicit $exec2719 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub4_sub52720 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub2_sub3_sub4_sub5_sub6_sub72721 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec2722 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec2723 S_NOP 0, implicit %1.sub2_sub3_sub42724 S_NOP 0, implicit %1.sub4_sub5_sub62725 2726 undef %2.sub2:vreg_1024_align2 = V_MOV_B32_e32 22, implicit $exec2727 %2.sub4:vreg_1024_align2 = V_MOV_B32_e32 24, implicit $exec2728 S_NOP 0, implicit %2.sub2_sub3_sub4_sub52729 S_NOP 0, implicit %2.sub4_sub5_sub6_sub72730 2731 undef %3.sub2:vreg_1024_align2 = V_MOV_B32_e32 32, implicit $exec2732 %3.sub4:vreg_1024_align2 = V_MOV_B32_e32 34, implicit $exec2733 S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub62734 S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub82735 2736 undef %4.sub2:vreg_1024_align2 = V_MOV_B32_e32 42, implicit $exec2737 %4.sub4:vreg_1024_align2 = V_MOV_B32_e32 44, implicit $exec2738 S_NOP 0, implicit %4.sub2_sub3_sub4_sub5_sub6_sub72739 S_NOP 0, implicit %4.sub4_sub5_sub6_sub7_sub8_sub92740 2741...2742---2743name: test_vreg_64_align2_w322744tracksRegLiveness: true2745body: |2746 bb.0:2747 ; CHECK-LABEL: name: test_vreg_64_align2_w322748 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec2749 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub02750 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec2751 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub12752 undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 00, implicit $exec2753 S_NOP 0, implicit %0.sub02754 2755 undef %1.sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec2756 S_NOP 0, implicit %1.sub12757 2758...2759---2760name: test_vreg_96_align2_w322761tracksRegLiveness: true2762body: |2763 bb.0:2764 ; CHECK-LABEL: name: test_vreg_96_align2_w322765 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec2766 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub02767 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec2768 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub12769 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec2770 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub22771 undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 00, implicit $exec2772 S_NOP 0, implicit %0.sub02773 2774 undef %1.sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec2775 S_NOP 0, implicit %1.sub12776 2777 undef %2.sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec2778 S_NOP 0, implicit %2.sub22779 2780...2781# Skip test_vreg_96_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_96_align22782---2783name: test_vreg_128_align2_w322784tracksRegLiveness: true2785body: |2786 bb.0:2787 ; CHECK-LABEL: name: test_vreg_128_align2_w322788 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec2789 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub02790 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec2791 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub12792 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec2793 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub32794 undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec2795 S_NOP 0, implicit %0.sub02796 2797 undef %1.sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec2798 S_NOP 0, implicit %1.sub12799 2800 undef %2.sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec2801 S_NOP 0, implicit %2.sub32802 2803...2804---2805name: test_vreg_128_align2_w642806tracksRegLiveness: true2807body: |2808 bb.0:2809 ; CHECK-LABEL: name: test_vreg_128_align2_w642810 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec2811 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec2812 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2813 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec2814 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec2815 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2816 undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec2817 %0.sub1:vreg_128_align2 = V_MOV_B32_e32 01, implicit $exec2818 S_NOP 0, implicit %0.sub0_sub12819 2820 undef %1.sub2:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec2821 %1.sub3:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec2822 S_NOP 0, implicit %1.sub2_sub32823 2824...2825# Skip test_vreg_128_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_128_align22826---2827name: test_vreg_160_align2_w322828tracksRegLiveness: true2829body: |2830 bb.0:2831 ; CHECK-LABEL: name: test_vreg_160_align2_w322832 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec2833 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub02834 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec2835 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub12836 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec2837 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub42838 undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec2839 S_NOP 0, implicit %0.sub02840 2841 undef %1.sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec2842 S_NOP 0, implicit %1.sub12843 2844 undef %2.sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec2845 S_NOP 0, implicit %2.sub42846 2847...2848# Skip test_vreg_160_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_160_align22849---2850name: test_vreg_160_align2_w962851tracksRegLiveness: true2852body: |2853 bb.0:2854 ; CHECK-LABEL: name: test_vreg_160_align2_w962855 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec2856 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec2857 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec2858 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2859 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec2860 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec2861 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec2862 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2863 undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec2864 %0.sub1:vreg_160_align2 = V_MOV_B32_e32 01, implicit $exec2865 %0.sub2:vreg_160_align2 = V_MOV_B32_e32 02, implicit $exec2866 S_NOP 0, implicit %0.sub0_sub1_sub22867 2868 undef %1.sub2:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec2869 %1.sub3:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec2870 %1.sub4:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec2871 S_NOP 0, implicit %1.sub2_sub3_sub42872 2873...2874# Skip test_vreg_160_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_160_align22875---2876name: test_vreg_192_align2_w322877tracksRegLiveness: true2878body: |2879 bb.0:2880 ; CHECK-LABEL: name: test_vreg_192_align2_w322881 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec2882 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub02883 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec2884 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub12885 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec2886 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub52887 undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec2888 S_NOP 0, implicit %0.sub02889 2890 undef %1.sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec2891 S_NOP 0, implicit %1.sub12892 2893 undef %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec2894 S_NOP 0, implicit %2.sub52895 2896...2897---2898name: test_vreg_192_align2_w642899tracksRegLiveness: true2900body: |2901 bb.0:2902 ; CHECK-LABEL: name: test_vreg_192_align2_w642903 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec2904 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec2905 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2906 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec2907 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec2908 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2909 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 24, implicit $exec2910 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 25, implicit $exec2911 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2912 undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec2913 %0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec2914 S_NOP 0, implicit %0.sub0_sub12915 2916 undef %1.sub2:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec2917 %1.sub3:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec2918 S_NOP 0, implicit %1.sub2_sub32919 2920 undef %2.sub4:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec2921 %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec2922 S_NOP 0, implicit %2.sub4_sub52923 2924...2925# Skip test_vreg_192_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_192_align22926---2927name: test_vreg_192_align2_w1282928tracksRegLiveness: true2929body: |2930 bb.0:2931 ; CHECK-LABEL: name: test_vreg_192_align2_w1282932 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec2933 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec2934 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec2935 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec2936 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2937 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec2938 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec2939 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec2940 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec2941 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2942 undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec2943 %0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec2944 %0.sub2:vreg_192_align2 = V_MOV_B32_e32 02, implicit $exec2945 %0.sub3:vreg_192_align2 = V_MOV_B32_e32 03, implicit $exec2946 S_NOP 0, implicit %0.sub0_sub1_sub2_sub32947 2948 undef %1.sub2:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec2949 %1.sub3:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec2950 %1.sub4:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec2951 %1.sub5:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec2952 S_NOP 0, implicit %1.sub2_sub3_sub4_sub52953 2954...2955# Skip test_vreg_192_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_192_align22956---2957name: test_vreg_224_align2_w322958tracksRegLiveness: true2959body: |2960 bb.0:2961 ; CHECK-LABEL: name: test_vreg_224_align2_w322962 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_224_align2 = V_MOV_B32_e32 0, implicit $exec2963 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub02964 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec2965 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub12966 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec2967 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub62968 undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec2969 S_NOP 0, implicit %0.sub02970 2971 undef %1.sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec2972 S_NOP 0, implicit %1.sub12973 2974 undef %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec2975 S_NOP 0, implicit %2.sub62976 2977...2978# Skip test_vreg_224_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_224_align22979---2980name: test_vreg_224_align2_w962981tracksRegLiveness: true2982body: |2983 bb.0:2984 ; CHECK-LABEL: name: test_vreg_224_align2_w962985 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec2986 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec2987 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec2988 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]2989 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec2990 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec2991 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec2992 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]2993 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 24, implicit $exec2994 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 25, implicit $exec2995 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec2996 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]2997 undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec2998 %0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec2999 %0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec3000 S_NOP 0, implicit %0.sub0_sub1_sub23001 3002 undef %1.sub2:vreg_224_align2 = V_MOV_B32_e32 12, implicit $exec3003 %1.sub3:vreg_224_align2 = V_MOV_B32_e32 13, implicit $exec3004 %1.sub4:vreg_224_align2 = V_MOV_B32_e32 14, implicit $exec3005 S_NOP 0, implicit %1.sub2_sub3_sub43006 3007 undef %2.sub4:vreg_224_align2 = V_MOV_B32_e32 24, implicit $exec3008 %2.sub5:vreg_224_align2 = V_MOV_B32_e32 25, implicit $exec3009 %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec3010 S_NOP 0, implicit %2.sub4_sub5_sub63011 3012...3013# Skip test_vreg_224_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_224_align23014---3015name: test_vreg_224_align2_w1603016tracksRegLiveness: true3017body: |3018 bb.0:3019 ; CHECK-LABEL: name: test_vreg_224_align2_w1603020 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec3021 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec3022 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec3023 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec3024 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec3025 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3026 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec3027 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec3028 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec3029 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec3030 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec3031 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3032 undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec3033 %0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec3034 %0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec3035 %0.sub3:vreg_224_align2 = V_MOV_B32_e32 03, implicit $exec3036 %0.sub4:vreg_224_align2 = V_MOV_B32_e32 04, implicit $exec3037 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub43038 3039 undef %1.sub2:vreg_224_align2 = V_MOV_B32_e32 12, implicit $exec3040 %1.sub3:vreg_224_align2 = V_MOV_B32_e32 13, implicit $exec3041 %1.sub4:vreg_224_align2 = V_MOV_B32_e32 14, implicit $exec3042 %1.sub5:vreg_224_align2 = V_MOV_B32_e32 15, implicit $exec3043 %1.sub6:vreg_224_align2 = V_MOV_B32_e32 16, implicit $exec3044 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub63045 3046...3047# Skip test_vreg_224_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_224_align23048---3049name: test_vreg_256_align2_w323050tracksRegLiveness: true3051body: |3052 bb.0:3053 ; CHECK-LABEL: name: test_vreg_256_align2_w323054 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec3055 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub03056 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec3057 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub13058 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec3059 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub73060 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec3061 S_NOP 0, implicit %0.sub03062 3063 undef %1.sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec3064 S_NOP 0, implicit %1.sub13065 3066 undef %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec3067 S_NOP 0, implicit %2.sub73068 3069...3070---3071name: test_vreg_256_align2_w643072tracksRegLiveness: true3073body: |3074 bb.0:3075 ; CHECK-LABEL: name: test_vreg_256_align2_w643076 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec3077 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec3078 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3079 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec3080 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec3081 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3082 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 26, implicit $exec3083 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 27, implicit $exec3084 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3085 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec3086 %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec3087 S_NOP 0, implicit %0.sub0_sub13088 3089 undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec3090 %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec3091 S_NOP 0, implicit %1.sub2_sub33092 3093 undef %2.sub6:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec3094 %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec3095 S_NOP 0, implicit %2.sub6_sub73096 3097...3098# Skip test_vreg_256_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_256_align23099---3100name: test_vreg_256_align2_w1283101tracksRegLiveness: true3102body: |3103 bb.0:3104 ; CHECK-LABEL: name: test_vreg_256_align2_w1283105 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec3106 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec3107 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec3108 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec3109 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3110 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec3111 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec3112 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec3113 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec3114 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3115 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec3116 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec3117 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec3118 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec3119 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3120 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec3121 %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec3122 %0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec3123 %0.sub3:vreg_256_align2 = V_MOV_B32_e32 03, implicit $exec3124 S_NOP 0, implicit %0.sub0_sub1_sub2_sub33125 3126 undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec3127 %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec3128 %1.sub4:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec3129 %1.sub5:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec3130 S_NOP 0, implicit %1.sub2_sub3_sub4_sub53131 3132 undef %2.sub4:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec3133 %2.sub5:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec3134 %2.sub6:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec3135 %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec3136 S_NOP 0, implicit %2.sub4_sub5_sub6_sub73137 3138...3139# Skip test_vreg_256_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_256_align23140---3141name: test_vreg_256_align2_w1923142tracksRegLiveness: true3143body: |3144 bb.0:3145 ; CHECK-LABEL: name: test_vreg_256_align2_w1923146 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec3147 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec3148 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec3149 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec3150 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec3151 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec3152 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3153 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec3154 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec3155 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec3156 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec3157 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec3158 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec3159 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3160 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec3161 %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec3162 %0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec3163 %0.sub3:vreg_256_align2 = V_MOV_B32_e32 03, implicit $exec3164 %0.sub4:vreg_256_align2 = V_MOV_B32_e32 04, implicit $exec3165 %0.sub5:vreg_256_align2 = V_MOV_B32_e32 05, implicit $exec3166 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub53167 3168 undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec3169 %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec3170 %1.sub4:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec3171 %1.sub5:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec3172 %1.sub6:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec3173 %1.sub7:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec3174 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub73175 3176...3177---3178name: test_vreg_288_align2_w323179tracksRegLiveness: true3180body: |3181 bb.0:3182 ; CHECK-LABEL: name: test_vreg_288_align2_w323183 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_288_align2 = V_MOV_B32_e32 0, implicit $exec3184 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub03185 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec3186 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub13187 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec3188 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub83189 undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec3190 S_NOP 0, implicit %0.sub03191 3192 undef %1.sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec3193 S_NOP 0, implicit %1.sub13194 3195 undef %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec3196 S_NOP 0, implicit %2.sub83197 3198...3199# Skip test_vreg_288_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_288_align23200---3201name: test_vreg_288_align2_w963202tracksRegLiveness: true3203body: |3204 bb.0:3205 ; CHECK-LABEL: name: test_vreg_288_align2_w963206 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec3207 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec3208 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec3209 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3210 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec3211 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec3212 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec3213 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3214 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec3215 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 27, implicit $exec3216 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec3217 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3218 undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec3219 %0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec3220 %0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec3221 S_NOP 0, implicit %0.sub0_sub1_sub23222 3223 undef %1.sub2:vreg_288_align2 = V_MOV_B32_e32 12, implicit $exec3224 %1.sub3:vreg_288_align2 = V_MOV_B32_e32 13, implicit $exec3225 %1.sub4:vreg_288_align2 = V_MOV_B32_e32 14, implicit $exec3226 S_NOP 0, implicit %1.sub2_sub3_sub43227 3228 undef %2.sub6:vreg_288_align2 = V_MOV_B32_e32 26, implicit $exec3229 %2.sub7:vreg_288_align2 = V_MOV_B32_e32 27, implicit $exec3230 %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec3231 S_NOP 0, implicit %2.sub6_sub7_sub83232 3233...3234# Skip test_vreg_288_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_288_align23235---3236name: test_vreg_288_align2_w1603237tracksRegLiveness: true3238body: |3239 bb.0:3240 ; CHECK-LABEL: name: test_vreg_288_align2_w1603241 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec3242 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec3243 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec3244 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec3245 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec3246 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3247 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec3248 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec3249 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec3250 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec3251 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec3252 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3253 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec3254 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 25, implicit $exec3255 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec3256 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec3257 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec3258 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3259 undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec3260 %0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec3261 %0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec3262 %0.sub3:vreg_288_align2 = V_MOV_B32_e32 03, implicit $exec3263 %0.sub4:vreg_288_align2 = V_MOV_B32_e32 04, implicit $exec3264 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub43265 3266 undef %1.sub2:vreg_288_align2 = V_MOV_B32_e32 12, implicit $exec3267 %1.sub3:vreg_288_align2 = V_MOV_B32_e32 13, implicit $exec3268 %1.sub4:vreg_288_align2 = V_MOV_B32_e32 14, implicit $exec3269 %1.sub5:vreg_288_align2 = V_MOV_B32_e32 15, implicit $exec3270 %1.sub6:vreg_288_align2 = V_MOV_B32_e32 16, implicit $exec3271 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub63272 3273 undef %2.sub4:vreg_288_align2 = V_MOV_B32_e32 24, implicit $exec3274 %2.sub5:vreg_288_align2 = V_MOV_B32_e32 25, implicit $exec3275 %2.sub6:vreg_288_align2 = V_MOV_B32_e32 26, implicit $exec3276 %2.sub7:vreg_288_align2 = V_MOV_B32_e32 27, implicit $exec3277 %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec3278 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub83279 3280...3281# Skip test_vreg_288_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_288_align23282# Skip test_vreg_288_align2_w256: the 256-bit subreg isn't fully supported for the regclass vreg_288_align23283---3284name: test_vreg_320_align2_w323285tracksRegLiveness: true3286body: |3287 bb.0:3288 ; CHECK-LABEL: name: test_vreg_320_align2_w323289 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_320_align2 = V_MOV_B32_e32 0, implicit $exec3290 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub03291 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec3292 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub13293 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec3294 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub93295 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec3296 S_NOP 0, implicit %0.sub03297 3298 undef %1.sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec3299 S_NOP 0, implicit %1.sub13300 3301 undef %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec3302 S_NOP 0, implicit %2.sub93303 3304...3305---3306name: test_vreg_320_align2_w643307tracksRegLiveness: true3308body: |3309 bb.0:3310 ; CHECK-LABEL: name: test_vreg_320_align2_w643311 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec3312 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec3313 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3314 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec3315 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec3316 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3317 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 28, implicit $exec3318 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 29, implicit $exec3319 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3320 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec3321 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec3322 S_NOP 0, implicit %0.sub0_sub13323 3324 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec3325 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec3326 S_NOP 0, implicit %1.sub2_sub33327 3328 undef %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec3329 %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec3330 S_NOP 0, implicit %2.sub8_sub93331 3332...3333# Skip test_vreg_320_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_320_align23334---3335name: test_vreg_320_align2_w1283336tracksRegLiveness: true3337body: |3338 bb.0:3339 ; CHECK-LABEL: name: test_vreg_320_align2_w1283340 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec3341 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec3342 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec3343 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec3344 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3345 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec3346 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec3347 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec3348 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec3349 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3350 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec3351 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec3352 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec3353 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec3354 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3355 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec3356 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec3357 %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec3358 %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec3359 S_NOP 0, implicit %0.sub0_sub1_sub2_sub33360 3361 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec3362 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec3363 %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec3364 %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec3365 S_NOP 0, implicit %1.sub2_sub3_sub4_sub53366 3367 undef %2.sub6:vreg_320_align2 = V_MOV_B32_e32 26, implicit $exec3368 %2.sub7:vreg_320_align2 = V_MOV_B32_e32 27, implicit $exec3369 %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec3370 %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec3371 S_NOP 0, implicit %2.sub6_sub7_sub8_sub93372 3373...3374# Skip test_vreg_320_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_320_align23375---3376name: test_vreg_320_align2_w1923377tracksRegLiveness: true3378body: |3379 bb.0:3380 ; CHECK-LABEL: name: test_vreg_320_align2_w1923381 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec3382 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec3383 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec3384 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec3385 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec3386 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec3387 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3388 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec3389 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec3390 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec3391 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec3392 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec3393 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec3394 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3395 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec3396 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec3397 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec3398 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec3399 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec3400 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec3401 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3402 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec3403 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec3404 %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec3405 %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec3406 %0.sub4:vreg_320_align2 = V_MOV_B32_e32 04, implicit $exec3407 %0.sub5:vreg_320_align2 = V_MOV_B32_e32 05, implicit $exec3408 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub53409 3410 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec3411 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec3412 %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec3413 %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec3414 %1.sub6:vreg_320_align2 = V_MOV_B32_e32 16, implicit $exec3415 %1.sub7:vreg_320_align2 = V_MOV_B32_e32 17, implicit $exec3416 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub73417 3418 undef %2.sub4:vreg_320_align2 = V_MOV_B32_e32 24, implicit $exec3419 %2.sub5:vreg_320_align2 = V_MOV_B32_e32 25, implicit $exec3420 %2.sub6:vreg_320_align2 = V_MOV_B32_e32 26, implicit $exec3421 %2.sub7:vreg_320_align2 = V_MOV_B32_e32 27, implicit $exec3422 %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec3423 %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec3424 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub93425 3426...3427---3428name: test_vreg_320_align2_w2563429tracksRegLiveness: true3430body: |3431 bb.0:3432 ; CHECK-LABEL: name: test_vreg_320_align2_w2563433 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec3434 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec3435 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec3436 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec3437 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec3438 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec3439 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec3440 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec3441 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3442 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec3443 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec3444 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec3445 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec3446 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec3447 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec3448 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec3449 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec3450 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3451 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec3452 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec3453 %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec3454 %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec3455 %0.sub4:vreg_320_align2 = V_MOV_B32_e32 04, implicit $exec3456 %0.sub5:vreg_320_align2 = V_MOV_B32_e32 05, implicit $exec3457 %0.sub6:vreg_320_align2 = V_MOV_B32_e32 06, implicit $exec3458 %0.sub7:vreg_320_align2 = V_MOV_B32_e32 07, implicit $exec3459 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub73460 3461 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec3462 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec3463 %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec3464 %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec3465 %1.sub6:vreg_320_align2 = V_MOV_B32_e32 16, implicit $exec3466 %1.sub7:vreg_320_align2 = V_MOV_B32_e32 17, implicit $exec3467 %1.sub8:vreg_320_align2 = V_MOV_B32_e32 18, implicit $exec3468 %1.sub9:vreg_320_align2 = V_MOV_B32_e32 19, implicit $exec3469 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub93470 3471...3472---3473name: test_vreg_352_align2_w323474tracksRegLiveness: true3475body: |3476 bb.0:3477 ; CHECK-LABEL: name: test_vreg_352_align2_w323478 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_352_align2 = V_MOV_B32_e32 0, implicit $exec3479 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub03480 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec3481 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub13482 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec3483 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub103484 undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec3485 S_NOP 0, implicit %0.sub03486 3487 undef %1.sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec3488 S_NOP 0, implicit %1.sub13489 3490 undef %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec3491 S_NOP 0, implicit %2.sub103492 3493...3494# Skip test_vreg_352_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_352_align23495---3496name: test_vreg_352_align2_w963497tracksRegLiveness: true3498body: |3499 bb.0:3500 ; CHECK-LABEL: name: test_vreg_352_align2_w963501 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec3502 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec3503 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec3504 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3505 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec3506 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec3507 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec3508 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3509 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec3510 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_96_align2 = V_MOV_B32_e32 29, implicit $exec3511 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_96_align2 = V_MOV_B32_e32 210, implicit $exec3512 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3513 undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec3514 %0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec3515 %0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec3516 S_NOP 0, implicit %0.sub0_sub1_sub23517 3518 undef %1.sub2:vreg_352_align2 = V_MOV_B32_e32 12, implicit $exec3519 %1.sub3:vreg_352_align2 = V_MOV_B32_e32 13, implicit $exec3520 %1.sub4:vreg_352_align2 = V_MOV_B32_e32 14, implicit $exec3521 S_NOP 0, implicit %1.sub2_sub3_sub43522 3523 undef %2.sub8:vreg_352_align2 = V_MOV_B32_e32 28, implicit $exec3524 %2.sub9:vreg_352_align2 = V_MOV_B32_e32 29, implicit $exec3525 %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec3526 S_NOP 0, implicit %2.sub8_sub9_sub103527 3528...3529# Skip test_vreg_352_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_352_align23530---3531name: test_vreg_352_align2_w1603532tracksRegLiveness: true3533body: |3534 bb.0:3535 ; CHECK-LABEL: name: test_vreg_352_align2_w1603536 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec3537 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec3538 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec3539 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec3540 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec3541 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3542 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec3543 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec3544 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec3545 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec3546 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec3547 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3548 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec3549 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec3550 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec3551 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_160_align2 = V_MOV_B32_e32 29, implicit $exec3552 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_160_align2 = V_MOV_B32_e32 210, implicit $exec3553 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3554 undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec3555 %0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec3556 %0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec3557 %0.sub3:vreg_352_align2 = V_MOV_B32_e32 03, implicit $exec3558 %0.sub4:vreg_352_align2 = V_MOV_B32_e32 04, implicit $exec3559 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub43560 3561 undef %1.sub2:vreg_352_align2 = V_MOV_B32_e32 12, implicit $exec3562 %1.sub3:vreg_352_align2 = V_MOV_B32_e32 13, implicit $exec3563 %1.sub4:vreg_352_align2 = V_MOV_B32_e32 14, implicit $exec3564 %1.sub5:vreg_352_align2 = V_MOV_B32_e32 15, implicit $exec3565 %1.sub6:vreg_352_align2 = V_MOV_B32_e32 16, implicit $exec3566 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub63567 3568 undef %2.sub6:vreg_352_align2 = V_MOV_B32_e32 26, implicit $exec3569 %2.sub7:vreg_352_align2 = V_MOV_B32_e32 27, implicit $exec3570 %2.sub8:vreg_352_align2 = V_MOV_B32_e32 28, implicit $exec3571 %2.sub9:vreg_352_align2 = V_MOV_B32_e32 29, implicit $exec3572 %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec3573 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub103574 3575...3576# Skip test_vreg_352_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_352_align23577# Skip test_vreg_352_align2_w256: the 256-bit subreg isn't fully supported for the regclass vreg_352_align23578---3579name: test_vreg_384_align2_w323580tracksRegLiveness: true3581body: |3582 bb.0:3583 ; CHECK-LABEL: name: test_vreg_384_align2_w323584 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_384_align2 = V_MOV_B32_e32 0, implicit $exec3585 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub03586 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec3587 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub13588 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec3589 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub113590 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec3591 S_NOP 0, implicit %0.sub03592 3593 undef %1.sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec3594 S_NOP 0, implicit %1.sub13595 3596 undef %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec3597 S_NOP 0, implicit %2.sub113598 3599...3600---3601name: test_vreg_384_align2_w643602tracksRegLiveness: true3603body: |3604 bb.0:3605 ; CHECK-LABEL: name: test_vreg_384_align2_w643606 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec3607 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec3608 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3609 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 110, implicit $exec3610 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 111, implicit $exec3611 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3612 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec3613 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec3614 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3615 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec3616 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec3617 S_NOP 0, implicit %0.sub0_sub13618 3619 undef %1.sub10:vreg_384_align2 = V_MOV_B32_e32 110, implicit $exec3620 %1.sub11:vreg_384_align2 = V_MOV_B32_e32 111, implicit $exec3621 S_NOP 0, implicit %1.sub10_sub113622 3623 undef %2.sub2:vreg_384_align2 = V_MOV_B32_e32 22, implicit $exec3624 %2.sub3:vreg_384_align2 = V_MOV_B32_e32 23, implicit $exec3625 S_NOP 0, implicit %2.sub2_sub33626 3627...3628# Skip test_vreg_384_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_384_align23629---3630name: test_vreg_384_align2_w1283631tracksRegLiveness: true3632body: |3633 bb.0:3634 ; CHECK-LABEL: name: test_vreg_384_align2_w1283635 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec3636 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec3637 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec3638 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec3639 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3640 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec3641 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec3642 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec3643 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec3644 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3645 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec3646 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec3647 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 210, implicit $exec3648 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 211, implicit $exec3649 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3650 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec3651 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec3652 %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec3653 %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec3654 S_NOP 0, implicit %0.sub0_sub1_sub2_sub33655 3656 undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec3657 %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec3658 %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec3659 %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec3660 S_NOP 0, implicit %1.sub2_sub3_sub4_sub53661 3662 undef %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec3663 %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec3664 %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec3665 %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec3666 S_NOP 0, implicit %2.sub8_sub9_sub10_sub113667 3668...3669# Skip test_vreg_384_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_384_align23670---3671name: test_vreg_384_align2_w1923672tracksRegLiveness: true3673body: |3674 bb.0:3675 ; CHECK-LABEL: name: test_vreg_384_align2_w1923676 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec3677 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec3678 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec3679 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec3680 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec3681 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec3682 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3683 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec3684 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec3685 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec3686 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec3687 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec3688 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec3689 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3690 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec3691 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec3692 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec3693 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec3694 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 210, implicit $exec3695 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 211, implicit $exec3696 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3697 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec3698 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec3699 %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec3700 %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec3701 %0.sub4:vreg_384_align2 = V_MOV_B32_e32 04, implicit $exec3702 %0.sub5:vreg_384_align2 = V_MOV_B32_e32 05, implicit $exec3703 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub53704 3705 undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec3706 %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec3707 %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec3708 %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec3709 %1.sub6:vreg_384_align2 = V_MOV_B32_e32 16, implicit $exec3710 %1.sub7:vreg_384_align2 = V_MOV_B32_e32 17, implicit $exec3711 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub73712 3713 undef %2.sub6:vreg_384_align2 = V_MOV_B32_e32 26, implicit $exec3714 %2.sub7:vreg_384_align2 = V_MOV_B32_e32 27, implicit $exec3715 %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec3716 %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec3717 %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec3718 %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec3719 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10_sub113720 3721...3722---3723name: test_vreg_384_align2_w2563724tracksRegLiveness: true3725body: |3726 bb.0:3727 ; CHECK-LABEL: name: test_vreg_384_align2_w2563728 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec3729 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec3730 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec3731 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec3732 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec3733 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec3734 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec3735 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec3736 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3737 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec3738 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec3739 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec3740 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec3741 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec3742 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec3743 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec3744 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec3745 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3746 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec3747 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec3748 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec3749 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec3750 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec3751 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec3752 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec3753 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec3754 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3755 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec3756 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec3757 %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec3758 %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec3759 %0.sub4:vreg_384_align2 = V_MOV_B32_e32 04, implicit $exec3760 %0.sub5:vreg_384_align2 = V_MOV_B32_e32 05, implicit $exec3761 %0.sub6:vreg_384_align2 = V_MOV_B32_e32 06, implicit $exec3762 %0.sub7:vreg_384_align2 = V_MOV_B32_e32 07, implicit $exec3763 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub73764 3765 undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec3766 %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec3767 %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec3768 %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec3769 %1.sub6:vreg_384_align2 = V_MOV_B32_e32 16, implicit $exec3770 %1.sub7:vreg_384_align2 = V_MOV_B32_e32 17, implicit $exec3771 %1.sub8:vreg_384_align2 = V_MOV_B32_e32 18, implicit $exec3772 %1.sub9:vreg_384_align2 = V_MOV_B32_e32 19, implicit $exec3773 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub93774 3775 undef %2.sub4:vreg_384_align2 = V_MOV_B32_e32 24, implicit $exec3776 %2.sub5:vreg_384_align2 = V_MOV_B32_e32 25, implicit $exec3777 %2.sub6:vreg_384_align2 = V_MOV_B32_e32 26, implicit $exec3778 %2.sub7:vreg_384_align2 = V_MOV_B32_e32 27, implicit $exec3779 %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec3780 %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec3781 %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec3782 %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec3783 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub113784 3785...3786---3787name: test_vreg_512_align2_w323788tracksRegLiveness: true3789body: |3790 bb.0:3791 ; CHECK-LABEL: name: test_vreg_512_align2_w323792 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec3793 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub03794 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec3795 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub13796 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec3797 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub153798 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec3799 S_NOP 0, implicit %0.sub03800 3801 undef %1.sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec3802 S_NOP 0, implicit %1.sub13803 3804 undef %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec3805 S_NOP 0, implicit %2.sub153806 3807...3808---3809name: test_vreg_512_align2_w643810tracksRegLiveness: true3811body: |3812 bb.0:3813 ; CHECK-LABEL: name: test_vreg_512_align2_w643814 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec3815 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec3816 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3817 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 114, implicit $exec3818 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 115, implicit $exec3819 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3820 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec3821 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec3822 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3823 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec3824 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec3825 S_NOP 0, implicit %0.sub0_sub13826 3827 undef %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec3828 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec3829 S_NOP 0, implicit %1.sub14_sub153830 3831 undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec3832 %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec3833 S_NOP 0, implicit %2.sub2_sub33834 3835...3836# Skip test_vreg_512_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_512_align23837---3838name: test_vreg_512_align2_w1283839tracksRegLiveness: true3840body: |3841 bb.0:3842 ; CHECK-LABEL: name: test_vreg_512_align2_w1283843 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec3844 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec3845 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec3846 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec3847 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3848 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 112, implicit $exec3849 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 113, implicit $exec3850 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 114, implicit $exec3851 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 115, implicit $exec3852 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3853 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 22, implicit $exec3854 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec3855 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec3856 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec3857 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3858 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec3859 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec3860 %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec3861 %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec3862 S_NOP 0, implicit %0.sub0_sub1_sub2_sub33863 3864 undef %1.sub12:vreg_512_align2 = V_MOV_B32_e32 112, implicit $exec3865 %1.sub13:vreg_512_align2 = V_MOV_B32_e32 113, implicit $exec3866 %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec3867 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec3868 S_NOP 0, implicit %1.sub12_sub13_sub14_sub153869 3870 undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec3871 %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec3872 %2.sub4:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec3873 %2.sub5:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec3874 S_NOP 0, implicit %2.sub2_sub3_sub4_sub53875 3876...3877# Skip test_vreg_512_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_512_align23878---3879name: test_vreg_512_align2_w1923880tracksRegLiveness: true3881body: |3882 bb.0:3883 ; CHECK-LABEL: name: test_vreg_512_align2_w1923884 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec3885 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec3886 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec3887 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec3888 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec3889 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec3890 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3891 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 110, implicit $exec3892 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 111, implicit $exec3893 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 112, implicit $exec3894 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 113, implicit $exec3895 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 114, implicit $exec3896 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 115, implicit $exec3897 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3898 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec3899 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 23, implicit $exec3900 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec3901 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec3902 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec3903 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec3904 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3905 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec3906 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec3907 %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec3908 %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec3909 %0.sub4:vreg_512_align2 = V_MOV_B32_e32 04, implicit $exec3910 %0.sub5:vreg_512_align2 = V_MOV_B32_e32 05, implicit $exec3911 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub53912 3913 undef %1.sub10:vreg_512_align2 = V_MOV_B32_e32 110, implicit $exec3914 %1.sub11:vreg_512_align2 = V_MOV_B32_e32 111, implicit $exec3915 %1.sub12:vreg_512_align2 = V_MOV_B32_e32 112, implicit $exec3916 %1.sub13:vreg_512_align2 = V_MOV_B32_e32 113, implicit $exec3917 %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec3918 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec3919 S_NOP 0, implicit %1.sub10_sub11_sub12_sub13_sub14_sub153920 3921 undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec3922 %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec3923 %2.sub4:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec3924 %2.sub5:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec3925 %2.sub6:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec3926 %2.sub7:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec3927 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub73928 3929...3930---3931name: test_vreg_512_align2_w2563932tracksRegLiveness: true3933body: |3934 bb.0:3935 ; CHECK-LABEL: name: test_vreg_512_align2_w2563936 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec3937 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec3938 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec3939 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec3940 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec3941 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec3942 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec3943 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec3944 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]3945 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec3946 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec3947 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec3948 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec3949 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec3950 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec3951 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec3952 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec3953 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]3954 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec3955 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec3956 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec3957 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec3958 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 212, implicit $exec3959 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 213, implicit $exec3960 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 214, implicit $exec3961 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 215, implicit $exec3962 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]3963 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec3964 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec3965 %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec3966 %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec3967 %0.sub4:vreg_512_align2 = V_MOV_B32_e32 04, implicit $exec3968 %0.sub5:vreg_512_align2 = V_MOV_B32_e32 05, implicit $exec3969 %0.sub6:vreg_512_align2 = V_MOV_B32_e32 06, implicit $exec3970 %0.sub7:vreg_512_align2 = V_MOV_B32_e32 07, implicit $exec3971 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub73972 3973 undef %1.sub2:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec3974 %1.sub3:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec3975 %1.sub4:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec3976 %1.sub5:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec3977 %1.sub6:vreg_512_align2 = V_MOV_B32_e32 16, implicit $exec3978 %1.sub7:vreg_512_align2 = V_MOV_B32_e32 17, implicit $exec3979 %1.sub8:vreg_512_align2 = V_MOV_B32_e32 18, implicit $exec3980 %1.sub9:vreg_512_align2 = V_MOV_B32_e32 19, implicit $exec3981 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub93982 3983 undef %2.sub8:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec3984 %2.sub9:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec3985 %2.sub10:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec3986 %2.sub11:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec3987 %2.sub12:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec3988 %2.sub13:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec3989 %2.sub14:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec3990 %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec3991 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub153992 3993...3994---3995name: test_vreg_1024_align2_w323996tracksRegLiveness: true3997body: |3998 bb.0:3999 ; CHECK-LABEL: name: test_vreg_1024_align2_w324000 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_1024_align2 = V_MOV_B32_e32 0, implicit $exec4001 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub04002 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec4003 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub14004 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec4005 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub314006 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec4007 S_NOP 0, implicit %0.sub04008 4009 undef %1.sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec4010 S_NOP 0, implicit %1.sub14011 4012 undef %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec4013 S_NOP 0, implicit %2.sub314014 4015...4016---4017name: test_vreg_1024_align2_w644018tracksRegLiveness: true4019body: |4020 bb.0:4021 ; CHECK-LABEL: name: test_vreg_1024_align2_w644022 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec4023 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec4024 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]4025 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec4026 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec4027 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]4028 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64_align2 = V_MOV_B32_e32 230, implicit $exec4029 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 231, implicit $exec4030 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]4031 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec4032 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec4033 S_NOP 0, implicit %0.sub0_sub14034 4035 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec4036 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec4037 S_NOP 0, implicit %1.sub2_sub34038 4039 undef %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec4040 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec4041 S_NOP 0, implicit %2.sub30_sub314042 4043...4044# Skip test_vreg_1024_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_1024_align24045---4046name: test_vreg_1024_align2_w1284047tracksRegLiveness: true4048body: |4049 bb.0:4050 ; CHECK-LABEL: name: test_vreg_1024_align2_w1284051 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec4052 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec4053 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec4054 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec4055 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]4056 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec4057 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec4058 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec4059 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec4060 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]4061 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_MOV_B32_e32 228, implicit $exec4062 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 229, implicit $exec4063 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_128_align2 = V_MOV_B32_e32 230, implicit $exec4064 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_128_align2 = V_MOV_B32_e32 231, implicit $exec4065 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]4066 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec4067 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec4068 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec4069 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec4070 S_NOP 0, implicit %0.sub0_sub1_sub2_sub34071 4072 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec4073 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec4074 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec4075 %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec4076 S_NOP 0, implicit %1.sub2_sub3_sub4_sub54077 4078 undef %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec4079 %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec4080 %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec4081 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec4082 S_NOP 0, implicit %2.sub28_sub29_sub30_sub314083 4084...4085# Skip test_vreg_1024_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_1024_align24086---4087name: test_vreg_1024_align2_w1924088tracksRegLiveness: true4089body: |4090 bb.0:4091 ; CHECK-LABEL: name: test_vreg_1024_align2_w1924092 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec4093 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec4094 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec4095 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec4096 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec4097 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec4098 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]4099 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec4100 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec4101 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec4102 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec4103 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec4104 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec4105 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]4106 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_192_align2 = V_MOV_B32_e32 226, implicit $exec4107 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_192_align2 = V_MOV_B32_e32 227, implicit $exec4108 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_192_align2 = V_MOV_B32_e32 228, implicit $exec4109 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_192_align2 = V_MOV_B32_e32 229, implicit $exec4110 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_192_align2 = V_MOV_B32_e32 230, implicit $exec4111 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_192_align2 = V_MOV_B32_e32 231, implicit $exec4112 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]4113 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec4114 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec4115 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec4116 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec4117 %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec4118 %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec4119 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub54120 4121 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec4122 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec4123 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec4124 %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec4125 %1.sub6:vreg_1024_align2 = V_MOV_B32_e32 16, implicit $exec4126 %1.sub7:vreg_1024_align2 = V_MOV_B32_e32 17, implicit $exec4127 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub74128 4129 undef %2.sub26:vreg_1024_align2 = V_MOV_B32_e32 226, implicit $exec4130 %2.sub27:vreg_1024_align2 = V_MOV_B32_e32 227, implicit $exec4131 %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec4132 %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec4133 %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec4134 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec4135 S_NOP 0, implicit %2.sub26_sub27_sub28_sub29_sub30_sub314136 4137...4138---4139name: test_vreg_1024_align2_w2564140tracksRegLiveness: true4141body: |4142 bb.0:4143 ; CHECK-LABEL: name: test_vreg_1024_align2_w2564144 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec4145 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec4146 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec4147 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec4148 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec4149 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec4150 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec4151 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec4152 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]4153 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec4154 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec4155 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec4156 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec4157 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec4158 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec4159 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec4160 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec4161 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]4162 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_256_align2 = V_MOV_B32_e32 224, implicit $exec4163 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_256_align2 = V_MOV_B32_e32 225, implicit $exec4164 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_256_align2 = V_MOV_B32_e32 226, implicit $exec4165 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_256_align2 = V_MOV_B32_e32 227, implicit $exec4166 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_256_align2 = V_MOV_B32_e32 228, implicit $exec4167 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_256_align2 = V_MOV_B32_e32 229, implicit $exec4168 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_256_align2 = V_MOV_B32_e32 230, implicit $exec4169 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_256_align2 = V_MOV_B32_e32 231, implicit $exec4170 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]4171 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec4172 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec4173 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec4174 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec4175 %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec4176 %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec4177 %0.sub6:vreg_1024_align2 = V_MOV_B32_e32 06, implicit $exec4178 %0.sub7:vreg_1024_align2 = V_MOV_B32_e32 07, implicit $exec4179 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub74180 4181 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec4182 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec4183 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec4184 %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec4185 %1.sub6:vreg_1024_align2 = V_MOV_B32_e32 16, implicit $exec4186 %1.sub7:vreg_1024_align2 = V_MOV_B32_e32 17, implicit $exec4187 %1.sub8:vreg_1024_align2 = V_MOV_B32_e32 18, implicit $exec4188 %1.sub9:vreg_1024_align2 = V_MOV_B32_e32 19, implicit $exec4189 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub94190 4191 undef %2.sub24:vreg_1024_align2 = V_MOV_B32_e32 224, implicit $exec4192 %2.sub25:vreg_1024_align2 = V_MOV_B32_e32 225, implicit $exec4193 %2.sub26:vreg_1024_align2 = V_MOV_B32_e32 226, implicit $exec4194 %2.sub27:vreg_1024_align2 = V_MOV_B32_e32 227, implicit $exec4195 %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec4196 %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec4197 %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec4198 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec4199 S_NOP 0, implicit %2.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub314200 4201...4202---4203name: test_vreg_1024_align2_w5124204tracksRegLiveness: true4205body: |4206 bb.0:4207 ; CHECK-LABEL: name: test_vreg_1024_align2_w5124208 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec4209 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 1, implicit $exec4210 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_512_align2 = V_MOV_B32_e32 2, implicit $exec4211 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_512_align2 = V_MOV_B32_e32 3, implicit $exec4212 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub4:vreg_512_align2 = V_MOV_B32_e32 4, implicit $exec4213 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub5:vreg_512_align2 = V_MOV_B32_e32 5, implicit $exec4214 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub6:vreg_512_align2 = V_MOV_B32_e32 6, implicit $exec4215 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub7:vreg_512_align2 = V_MOV_B32_e32 7, implicit $exec4216 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub8:vreg_512_align2 = V_MOV_B32_e32 8, implicit $exec4217 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub9:vreg_512_align2 = V_MOV_B32_e32 9, implicit $exec4218 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub10:vreg_512_align2 = V_MOV_B32_e32 10, implicit $exec4219 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub11:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec4220 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub12:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec4221 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub13:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec4222 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub14:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec4223 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec4224 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]4225 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 116, implicit $exec4226 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 117, implicit $exec4227 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub2:vreg_512_align2 = V_MOV_B32_e32 118, implicit $exec4228 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub3:vreg_512_align2 = V_MOV_B32_e32 119, implicit $exec4229 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub4:vreg_512_align2 = V_MOV_B32_e32 120, implicit $exec4230 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub5:vreg_512_align2 = V_MOV_B32_e32 121, implicit $exec4231 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub6:vreg_512_align2 = V_MOV_B32_e32 122, implicit $exec4232 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub7:vreg_512_align2 = V_MOV_B32_e32 123, implicit $exec4233 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub8:vreg_512_align2 = V_MOV_B32_e32 124, implicit $exec4234 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub9:vreg_512_align2 = V_MOV_B32_e32 125, implicit $exec4235 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub10:vreg_512_align2 = V_MOV_B32_e32 126, implicit $exec4236 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub11:vreg_512_align2 = V_MOV_B32_e32 127, implicit $exec4237 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub12:vreg_512_align2 = V_MOV_B32_e32 128, implicit $exec4238 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub13:vreg_512_align2 = V_MOV_B32_e32 129, implicit $exec4239 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub14:vreg_512_align2 = V_MOV_B32_e32 130, implicit $exec4240 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 131, implicit $exec4241 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]4242 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec4243 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec4244 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub2:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec4245 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub3:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec4246 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub4:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec4247 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub5:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec4248 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub6:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec4249 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub7:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec4250 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub8:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec4251 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub9:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec4252 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub10:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec4253 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub11:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec4254 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub12:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec4255 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub13:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec4256 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub14:vreg_512_align2 = V_MOV_B32_e32 216, implicit $exec4257 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub15:vreg_512_align2 = V_MOV_B32_e32 217, implicit $exec4258 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]4259 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec4260 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec4261 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec4262 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec4263 %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec4264 %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec4265 %0.sub6:vreg_1024_align2 = V_MOV_B32_e32 06, implicit $exec4266 %0.sub7:vreg_1024_align2 = V_MOV_B32_e32 07, implicit $exec4267 %0.sub8:vreg_1024_align2 = V_MOV_B32_e32 08, implicit $exec4268 %0.sub9:vreg_1024_align2 = V_MOV_B32_e32 09, implicit $exec4269 %0.sub10:vreg_1024_align2 = V_MOV_B32_e32 010, implicit $exec4270 %0.sub11:vreg_1024_align2 = V_MOV_B32_e32 011, implicit $exec4271 %0.sub12:vreg_1024_align2 = V_MOV_B32_e32 012, implicit $exec4272 %0.sub13:vreg_1024_align2 = V_MOV_B32_e32 013, implicit $exec4273 %0.sub14:vreg_1024_align2 = V_MOV_B32_e32 014, implicit $exec4274 %0.sub15:vreg_1024_align2 = V_MOV_B32_e32 015, implicit $exec4275 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub154276 4277 undef %1.sub16:vreg_1024_align2 = V_MOV_B32_e32 116, implicit $exec4278 %1.sub17:vreg_1024_align2 = V_MOV_B32_e32 117, implicit $exec4279 %1.sub18:vreg_1024_align2 = V_MOV_B32_e32 118, implicit $exec4280 %1.sub19:vreg_1024_align2 = V_MOV_B32_e32 119, implicit $exec4281 %1.sub20:vreg_1024_align2 = V_MOV_B32_e32 120, implicit $exec4282 %1.sub21:vreg_1024_align2 = V_MOV_B32_e32 121, implicit $exec4283 %1.sub22:vreg_1024_align2 = V_MOV_B32_e32 122, implicit $exec4284 %1.sub23:vreg_1024_align2 = V_MOV_B32_e32 123, implicit $exec4285 %1.sub24:vreg_1024_align2 = V_MOV_B32_e32 124, implicit $exec4286 %1.sub25:vreg_1024_align2 = V_MOV_B32_e32 125, implicit $exec4287 %1.sub26:vreg_1024_align2 = V_MOV_B32_e32 126, implicit $exec4288 %1.sub27:vreg_1024_align2 = V_MOV_B32_e32 127, implicit $exec4289 %1.sub28:vreg_1024_align2 = V_MOV_B32_e32 128, implicit $exec4290 %1.sub29:vreg_1024_align2 = V_MOV_B32_e32 129, implicit $exec4291 %1.sub30:vreg_1024_align2 = V_MOV_B32_e32 130, implicit $exec4292 %1.sub31:vreg_1024_align2 = V_MOV_B32_e32 131, implicit $exec4293 S_NOP 0, implicit %1.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub314294 4295 undef %2.sub2:vreg_1024_align2 = V_MOV_B32_e32 22, implicit $exec4296 %2.sub3:vreg_1024_align2 = V_MOV_B32_e32 23, implicit $exec4297 %2.sub4:vreg_1024_align2 = V_MOV_B32_e32 24, implicit $exec4298 %2.sub5:vreg_1024_align2 = V_MOV_B32_e32 25, implicit $exec4299 %2.sub6:vreg_1024_align2 = V_MOV_B32_e32 26, implicit $exec4300 %2.sub7:vreg_1024_align2 = V_MOV_B32_e32 27, implicit $exec4301 %2.sub8:vreg_1024_align2 = V_MOV_B32_e32 28, implicit $exec4302 %2.sub9:vreg_1024_align2 = V_MOV_B32_e32 29, implicit $exec4303 %2.sub10:vreg_1024_align2 = V_MOV_B32_e32 210, implicit $exec4304 %2.sub11:vreg_1024_align2 = V_MOV_B32_e32 211, implicit $exec4305 %2.sub12:vreg_1024_align2 = V_MOV_B32_e32 212, implicit $exec4306 %2.sub13:vreg_1024_align2 = V_MOV_B32_e32 213, implicit $exec4307 %2.sub14:vreg_1024_align2 = V_MOV_B32_e32 214, implicit $exec4308 %2.sub15:vreg_1024_align2 = V_MOV_B32_e32 215, implicit $exec4309 %2.sub16:vreg_1024_align2 = V_MOV_B32_e32 216, implicit $exec4310 %2.sub17:vreg_1024_align2 = V_MOV_B32_e32 217, implicit $exec4311 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub174312 4313...4314---4315name: test_subregs_composition_sgpr_10244316tracksRegLiveness: true4317body: |4318 bb.0:4319 ; CHECK-LABEL: name: test_subregs_composition_sgpr_10244320 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_288 = S_MOV_B32 344321 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_288 = S_MOV_B32 384322 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub0_sub1_sub2_sub3_sub44323 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub4_sub5_sub6_sub7_sub84324 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_320 = S_MOV_B32 444325 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_320 = S_MOV_B32 484326 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]].sub0_sub1_sub2_sub3_sub4_sub54327 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]].sub4_sub5_sub6_sub7_sub8_sub94328 undef %3.sub4:sgpr_1024 = S_MOV_B32 344329 %3.sub8:sgpr_1024 = S_MOV_B32 384330 S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub84331 S_NOP 0, implicit %3.sub8_sub9_sub10_sub11_sub124332 4333 undef %4.sub4:sgpr_1024 = S_MOV_B32 444334 %4.sub8:sgpr_1024 = S_MOV_B32 484335 S_NOP 0, implicit %4.sub4_sub5_sub6_sub7_sub8_sub94336 S_NOP 0, implicit %4.sub8_sub9_sub10_sub11_sub12_sub134337 4338...4339---4340name: test_sgpr_64_w324341tracksRegLiveness: true4342body: |4343 bb.0:4344 ; CHECK-LABEL: name: test_sgpr_64_w324345 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04346 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4347 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114348 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4349 undef %0.sub0:sgpr_64 = S_MOV_B32 004350 S_NOP 0, implicit %0.sub04351 4352 undef %1.sub1:sgpr_64 = S_MOV_B32 114353 S_NOP 0, implicit %1.sub14354 4355...4356---4357name: test_sgpr_96_w324358tracksRegLiveness: true4359body: |4360 bb.0:4361 ; CHECK-LABEL: name: test_sgpr_96_w324362 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04363 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4364 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114365 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4366 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 224367 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4368 undef %0.sub0:sgpr_96 = S_MOV_B32 004369 S_NOP 0, implicit %0.sub04370 4371 undef %1.sub1:sgpr_96 = S_MOV_B32 114372 S_NOP 0, implicit %1.sub14373 4374 undef %2.sub2:sgpr_96 = S_MOV_B32 224375 S_NOP 0, implicit %2.sub24376 4377...4378# Skip test_sgpr_96_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_964379---4380name: test_sgpr_128_w324381tracksRegLiveness: true4382body: |4383 bb.0:4384 ; CHECK-LABEL: name: test_sgpr_128_w324385 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04386 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4387 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114388 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4389 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 234390 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4391 undef %0.sub0:sgpr_128 = S_MOV_B32 004392 S_NOP 0, implicit %0.sub04393 4394 undef %1.sub1:sgpr_128 = S_MOV_B32 114395 S_NOP 0, implicit %1.sub14396 4397 undef %2.sub3:sgpr_128 = S_MOV_B32 234398 S_NOP 0, implicit %2.sub34399 4400...4401---4402name: test_sgpr_128_w644403tracksRegLiveness: true4404body: |4405 bb.0:4406 ; CHECK-LABEL: name: test_sgpr_128_w644407 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 04408 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 14409 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4410 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 124411 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 134412 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4413 undef %0.sub0:sgpr_128 = S_MOV_B32 004414 %0.sub1:sgpr_128 = S_MOV_B32 014415 S_NOP 0, implicit %0.sub0_sub14416 4417 undef %1.sub2:sgpr_128 = S_MOV_B32 124418 %1.sub3:sgpr_128 = S_MOV_B32 134419 S_NOP 0, implicit %1.sub2_sub34420 4421...4422# Skip test_sgpr_128_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_1284423---4424name: test_sgpr_160_w324425tracksRegLiveness: true4426body: |4427 bb.0:4428 ; CHECK-LABEL: name: test_sgpr_160_w324429 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04430 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4431 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114432 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4433 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 244434 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4435 undef %0.sub0:sgpr_160 = S_MOV_B32 004436 S_NOP 0, implicit %0.sub04437 4438 undef %1.sub1:sgpr_160 = S_MOV_B32 114439 S_NOP 0, implicit %1.sub14440 4441 undef %2.sub4:sgpr_160 = S_MOV_B32 244442 S_NOP 0, implicit %2.sub44443 4444...4445# Skip test_sgpr_160_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_1604446# Skip test_sgpr_160_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_1604447# Skip test_sgpr_160_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_1604448---4449name: test_sgpr_192_w324450tracksRegLiveness: true4451body: |4452 bb.0:4453 ; CHECK-LABEL: name: test_sgpr_192_w324454 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04455 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4456 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114457 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4458 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 254459 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4460 undef %0.sub0:sgpr_192 = S_MOV_B32 004461 S_NOP 0, implicit %0.sub04462 4463 undef %1.sub1:sgpr_192 = S_MOV_B32 114464 S_NOP 0, implicit %1.sub14465 4466 undef %2.sub5:sgpr_192 = S_MOV_B32 254467 S_NOP 0, implicit %2.sub54468 4469...4470---4471name: test_sgpr_192_w644472tracksRegLiveness: true4473body: |4474 bb.0:4475 ; CHECK-LABEL: name: test_sgpr_192_w644476 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 04477 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 14478 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4479 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 124480 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 134481 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4482 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 244483 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 254484 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4485 undef %0.sub0:sgpr_192 = S_MOV_B32 004486 %0.sub1:sgpr_192 = S_MOV_B32 014487 S_NOP 0, implicit %0.sub0_sub14488 4489 undef %1.sub2:sgpr_192 = S_MOV_B32 124490 %1.sub3:sgpr_192 = S_MOV_B32 134491 S_NOP 0, implicit %1.sub2_sub34492 4493 undef %2.sub4:sgpr_192 = S_MOV_B32 244494 %2.sub5:sgpr_192 = S_MOV_B32 254495 S_NOP 0, implicit %2.sub4_sub54496 4497...4498# Skip test_sgpr_192_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_1924499# Skip test_sgpr_192_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_1924500# Skip test_sgpr_192_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_1924501---4502name: test_sgpr_224_w324503tracksRegLiveness: true4504body: |4505 bb.0:4506 ; CHECK-LABEL: name: test_sgpr_224_w324507 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04508 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4509 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114510 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4511 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 264512 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4513 undef %0.sub0:sgpr_224 = S_MOV_B32 004514 S_NOP 0, implicit %0.sub04515 4516 undef %1.sub1:sgpr_224 = S_MOV_B32 114517 S_NOP 0, implicit %1.sub14518 4519 undef %2.sub6:sgpr_224 = S_MOV_B32 264520 S_NOP 0, implicit %2.sub64521 4522...4523# Skip test_sgpr_224_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_2244524# Skip test_sgpr_224_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_2244525# Skip test_sgpr_224_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_2244526# Skip test_sgpr_224_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_2244527# Skip test_sgpr_224_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_2244528---4529name: test_sgpr_256_w324530tracksRegLiveness: true4531body: |4532 bb.0:4533 ; CHECK-LABEL: name: test_sgpr_256_w324534 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04535 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4536 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114537 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4538 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 274539 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4540 undef %0.sub0:sgpr_256 = S_MOV_B32 004541 S_NOP 0, implicit %0.sub04542 4543 undef %1.sub1:sgpr_256 = S_MOV_B32 114544 S_NOP 0, implicit %1.sub14545 4546 undef %2.sub7:sgpr_256 = S_MOV_B32 274547 S_NOP 0, implicit %2.sub74548 4549...4550---4551name: test_sgpr_256_w644552tracksRegLiveness: true4553body: |4554 bb.0:4555 ; CHECK-LABEL: name: test_sgpr_256_w644556 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 04557 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 14558 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4559 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 124560 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 134561 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4562 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 264563 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 274564 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4565 undef %0.sub0:sgpr_256 = S_MOV_B32 004566 %0.sub1:sgpr_256 = S_MOV_B32 014567 S_NOP 0, implicit %0.sub0_sub14568 4569 undef %1.sub2:sgpr_256 = S_MOV_B32 124570 %1.sub3:sgpr_256 = S_MOV_B32 134571 S_NOP 0, implicit %1.sub2_sub34572 4573 undef %2.sub6:sgpr_256 = S_MOV_B32 264574 %2.sub7:sgpr_256 = S_MOV_B32 274575 S_NOP 0, implicit %2.sub6_sub74576 4577...4578# Skip test_sgpr_256_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_2564579---4580name: test_sgpr_256_w1284581tracksRegLiveness: true4582body: |4583 bb.0:4584 ; CHECK-LABEL: name: test_sgpr_256_w1284585 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 04586 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 14587 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 24588 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 34589 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4590 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 144591 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 154592 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 164593 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 174594 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4595 undef %0.sub0:sgpr_256 = S_MOV_B32 004596 %0.sub1:sgpr_256 = S_MOV_B32 014597 %0.sub2:sgpr_256 = S_MOV_B32 024598 %0.sub3:sgpr_256 = S_MOV_B32 034599 S_NOP 0, implicit %0.sub0_sub1_sub2_sub34600 4601 undef %1.sub4:sgpr_256 = S_MOV_B32 144602 %1.sub5:sgpr_256 = S_MOV_B32 154603 %1.sub6:sgpr_256 = S_MOV_B32 164604 %1.sub7:sgpr_256 = S_MOV_B32 174605 S_NOP 0, implicit %1.sub4_sub5_sub6_sub74606 4607...4608# Skip test_sgpr_256_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_2564609# Skip test_sgpr_256_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_2564610---4611name: test_sgpr_288_w324612tracksRegLiveness: true4613body: |4614 bb.0:4615 ; CHECK-LABEL: name: test_sgpr_288_w324616 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04617 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4618 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114619 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4620 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 284621 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4622 undef %0.sub0:sgpr_288 = S_MOV_B32 004623 S_NOP 0, implicit %0.sub04624 4625 undef %1.sub1:sgpr_288 = S_MOV_B32 114626 S_NOP 0, implicit %1.sub14627 4628 undef %2.sub8:sgpr_288 = S_MOV_B32 284629 S_NOP 0, implicit %2.sub84630 4631...4632# Skip test_sgpr_288_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_2884633# Skip test_sgpr_288_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_2884634# Skip test_sgpr_288_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_2884635---4636name: test_sgpr_288_w1604637tracksRegLiveness: true4638body: |4639 bb.0:4640 ; CHECK-LABEL: name: test_sgpr_288_w1604641 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_160 = S_MOV_B32 04642 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_160 = S_MOV_B32 14643 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_160 = S_MOV_B32 24644 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_160 = S_MOV_B32 34645 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_160 = S_MOV_B32 44646 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4647 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_160 = S_MOV_B32 144648 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_160 = S_MOV_B32 154649 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_160 = S_MOV_B32 164650 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_160 = S_MOV_B32 174651 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_160 = S_MOV_B32 184652 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4653 undef %0.sub0:sgpr_288 = S_MOV_B32 004654 %0.sub1:sgpr_288 = S_MOV_B32 014655 %0.sub2:sgpr_288 = S_MOV_B32 024656 %0.sub3:sgpr_288 = S_MOV_B32 034657 %0.sub4:sgpr_288 = S_MOV_B32 044658 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub44659 4660 undef %1.sub4:sgpr_288 = S_MOV_B32 144661 %1.sub5:sgpr_288 = S_MOV_B32 154662 %1.sub6:sgpr_288 = S_MOV_B32 164663 %1.sub7:sgpr_288 = S_MOV_B32 174664 %1.sub8:sgpr_288 = S_MOV_B32 184665 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub84666 4667...4668# Skip test_sgpr_288_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_2884669# Skip test_sgpr_288_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_2884670---4671name: test_sgpr_320_w324672tracksRegLiveness: true4673body: |4674 bb.0:4675 ; CHECK-LABEL: name: test_sgpr_320_w324676 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04677 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4678 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114679 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4680 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 294681 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4682 undef %0.sub0:sgpr_320 = S_MOV_B32 004683 S_NOP 0, implicit %0.sub04684 4685 undef %1.sub1:sgpr_320 = S_MOV_B32 114686 S_NOP 0, implicit %1.sub14687 4688 undef %2.sub9:sgpr_320 = S_MOV_B32 294689 S_NOP 0, implicit %2.sub94690 4691...4692---4693name: test_sgpr_320_w644694tracksRegLiveness: true4695body: |4696 bb.0:4697 ; CHECK-LABEL: name: test_sgpr_320_w644698 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 04699 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 14700 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4701 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 124702 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 134703 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4704 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 284705 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 294706 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4707 undef %0.sub0:sgpr_320 = S_MOV_B32 004708 %0.sub1:sgpr_320 = S_MOV_B32 014709 S_NOP 0, implicit %0.sub0_sub14710 4711 undef %1.sub2:sgpr_320 = S_MOV_B32 124712 %1.sub3:sgpr_320 = S_MOV_B32 134713 S_NOP 0, implicit %1.sub2_sub34714 4715 undef %2.sub8:sgpr_320 = S_MOV_B32 284716 %2.sub9:sgpr_320 = S_MOV_B32 294717 S_NOP 0, implicit %2.sub8_sub94718 4719...4720# Skip test_sgpr_320_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_3204721# Skip test_sgpr_320_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_3204722# Skip test_sgpr_320_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_3204723---4724name: test_sgpr_320_w1924725tracksRegLiveness: true4726body: |4727 bb.0:4728 ; CHECK-LABEL: name: test_sgpr_320_w1924729 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_192 = S_MOV_B32 04730 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_192 = S_MOV_B32 14731 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_192 = S_MOV_B32 24732 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_192 = S_MOV_B32 34733 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_192 = S_MOV_B32 44734 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_192 = S_MOV_B32 54735 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4736 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_192 = S_MOV_B32 144737 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_192 = S_MOV_B32 154738 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_192 = S_MOV_B32 164739 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_192 = S_MOV_B32 174740 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_192 = S_MOV_B32 184741 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_192 = S_MOV_B32 194742 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4743 undef %0.sub0:sgpr_320 = S_MOV_B32 004744 %0.sub1:sgpr_320 = S_MOV_B32 014745 %0.sub2:sgpr_320 = S_MOV_B32 024746 %0.sub3:sgpr_320 = S_MOV_B32 034747 %0.sub4:sgpr_320 = S_MOV_B32 044748 %0.sub5:sgpr_320 = S_MOV_B32 054749 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub54750 4751 undef %1.sub4:sgpr_320 = S_MOV_B32 144752 %1.sub5:sgpr_320 = S_MOV_B32 154753 %1.sub6:sgpr_320 = S_MOV_B32 164754 %1.sub7:sgpr_320 = S_MOV_B32 174755 %1.sub8:sgpr_320 = S_MOV_B32 184756 %1.sub9:sgpr_320 = S_MOV_B32 194757 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub94758 4759...4760# Skip test_sgpr_320_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_3204761---4762name: test_sgpr_352_w324763tracksRegLiveness: true4764body: |4765 bb.0:4766 ; CHECK-LABEL: name: test_sgpr_352_w324767 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04768 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4769 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114770 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4771 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 2104772 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4773 undef %0.sub0:sgpr_352 = S_MOV_B32 004774 S_NOP 0, implicit %0.sub04775 4776 undef %1.sub1:sgpr_352 = S_MOV_B32 114777 S_NOP 0, implicit %1.sub14778 4779 undef %2.sub10:sgpr_352 = S_MOV_B32 2104780 S_NOP 0, implicit %2.sub104781 4782...4783# Skip test_sgpr_352_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_3524784# Skip test_sgpr_352_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_3524785# Skip test_sgpr_352_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_3524786# Skip test_sgpr_352_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_3524787# Skip test_sgpr_352_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_3524788# Skip test_sgpr_352_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_3524789---4790name: test_sgpr_384_w324791tracksRegLiveness: true4792body: |4793 bb.0:4794 ; CHECK-LABEL: name: test_sgpr_384_w324795 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04796 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4797 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114798 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4799 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 2114800 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4801 undef %0.sub0:sgpr_384 = S_MOV_B32 004802 S_NOP 0, implicit %0.sub04803 4804 undef %1.sub1:sgpr_384 = S_MOV_B32 114805 S_NOP 0, implicit %1.sub14806 4807 undef %2.sub11:sgpr_384 = S_MOV_B32 2114808 S_NOP 0, implicit %2.sub114809 4810...4811---4812name: test_sgpr_384_w644813tracksRegLiveness: true4814body: |4815 bb.0:4816 ; CHECK-LABEL: name: test_sgpr_384_w644817 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 04818 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 14819 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4820 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 1104821 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1114822 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4823 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 224824 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 234825 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4826 undef %0.sub0:sgpr_384 = S_MOV_B32 004827 %0.sub1:sgpr_384 = S_MOV_B32 014828 S_NOP 0, implicit %0.sub0_sub14829 4830 undef %1.sub10:sgpr_384 = S_MOV_B32 1104831 %1.sub11:sgpr_384 = S_MOV_B32 1114832 S_NOP 0, implicit %1.sub10_sub114833 4834 undef %2.sub2:sgpr_384 = S_MOV_B32 224835 %2.sub3:sgpr_384 = S_MOV_B32 234836 S_NOP 0, implicit %2.sub2_sub34837 4838...4839# Skip test_sgpr_384_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_3844840---4841name: test_sgpr_384_w1284842tracksRegLiveness: true4843body: |4844 bb.0:4845 ; CHECK-LABEL: name: test_sgpr_384_w1284846 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 04847 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 14848 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 24849 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 34850 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4851 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 144852 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 154853 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 164854 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 174855 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4856 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 284857 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 294858 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 2104859 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 2114860 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4861 undef %0.sub0:sgpr_384 = S_MOV_B32 004862 %0.sub1:sgpr_384 = S_MOV_B32 014863 %0.sub2:sgpr_384 = S_MOV_B32 024864 %0.sub3:sgpr_384 = S_MOV_B32 034865 S_NOP 0, implicit %0.sub0_sub1_sub2_sub34866 4867 undef %1.sub4:sgpr_384 = S_MOV_B32 144868 %1.sub5:sgpr_384 = S_MOV_B32 154869 %1.sub6:sgpr_384 = S_MOV_B32 164870 %1.sub7:sgpr_384 = S_MOV_B32 174871 S_NOP 0, implicit %1.sub4_sub5_sub6_sub74872 4873 undef %2.sub8:sgpr_384 = S_MOV_B32 284874 %2.sub9:sgpr_384 = S_MOV_B32 294875 %2.sub10:sgpr_384 = S_MOV_B32 2104876 %2.sub11:sgpr_384 = S_MOV_B32 2114877 S_NOP 0, implicit %2.sub8_sub9_sub10_sub114878 4879...4880# Skip test_sgpr_384_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_3844881# Skip test_sgpr_384_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_3844882---4883name: test_sgpr_384_w2564884tracksRegLiveness: true4885body: |4886 bb.0:4887 ; CHECK-LABEL: name: test_sgpr_384_w2564888 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 04889 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 14890 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 24891 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 34892 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 44893 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 54894 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 64895 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 74896 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4897 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 144898 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 154899 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 164900 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 174901 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 184902 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 194903 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 1104904 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 1114905 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4906 undef %0.sub0:sgpr_384 = S_MOV_B32 004907 %0.sub1:sgpr_384 = S_MOV_B32 014908 %0.sub2:sgpr_384 = S_MOV_B32 024909 %0.sub3:sgpr_384 = S_MOV_B32 034910 %0.sub4:sgpr_384 = S_MOV_B32 044911 %0.sub5:sgpr_384 = S_MOV_B32 054912 %0.sub6:sgpr_384 = S_MOV_B32 064913 %0.sub7:sgpr_384 = S_MOV_B32 074914 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub74915 4916 undef %1.sub4:sgpr_384 = S_MOV_B32 144917 %1.sub5:sgpr_384 = S_MOV_B32 154918 %1.sub6:sgpr_384 = S_MOV_B32 164919 %1.sub7:sgpr_384 = S_MOV_B32 174920 %1.sub8:sgpr_384 = S_MOV_B32 184921 %1.sub9:sgpr_384 = S_MOV_B32 194922 %1.sub10:sgpr_384 = S_MOV_B32 1104923 %1.sub11:sgpr_384 = S_MOV_B32 1114924 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub114925 4926...4927---4928name: test_sgpr_512_w324929tracksRegLiveness: true4930body: |4931 bb.0:4932 ; CHECK-LABEL: name: test_sgpr_512_w324933 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 04934 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4935 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 114936 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4937 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 2154938 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4939 undef %0.sub0:sgpr_512 = S_MOV_B32 004940 S_NOP 0, implicit %0.sub04941 4942 undef %1.sub1:sgpr_512 = S_MOV_B32 114943 S_NOP 0, implicit %1.sub14944 4945 undef %2.sub15:sgpr_512 = S_MOV_B32 2154946 S_NOP 0, implicit %2.sub154947 4948...4949---4950name: test_sgpr_512_w644951tracksRegLiveness: true4952body: |4953 bb.0:4954 ; CHECK-LABEL: name: test_sgpr_512_w644955 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 04956 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 14957 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4958 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 1144959 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 1154960 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4961 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 224962 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 234963 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4964 undef %0.sub0:sgpr_512 = S_MOV_B32 004965 %0.sub1:sgpr_512 = S_MOV_B32 014966 S_NOP 0, implicit %0.sub0_sub14967 4968 undef %1.sub14:sgpr_512 = S_MOV_B32 1144969 %1.sub15:sgpr_512 = S_MOV_B32 1154970 S_NOP 0, implicit %1.sub14_sub154971 4972 undef %2.sub2:sgpr_512 = S_MOV_B32 224973 %2.sub3:sgpr_512 = S_MOV_B32 234974 S_NOP 0, implicit %2.sub2_sub34975 4976...4977# Skip test_sgpr_512_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_5124978---4979name: test_sgpr_512_w1284980tracksRegLiveness: true4981body: |4982 bb.0:4983 ; CHECK-LABEL: name: test_sgpr_512_w1284984 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 04985 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 14986 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 24987 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 34988 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]4989 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1124990 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 1134991 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 1144992 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 1154993 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]4994 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 244995 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 254996 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 264997 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 274998 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]4999 undef %0.sub0:sgpr_512 = S_MOV_B32 005000 %0.sub1:sgpr_512 = S_MOV_B32 015001 %0.sub2:sgpr_512 = S_MOV_B32 025002 %0.sub3:sgpr_512 = S_MOV_B32 035003 S_NOP 0, implicit %0.sub0_sub1_sub2_sub35004 5005 undef %1.sub12:sgpr_512 = S_MOV_B32 1125006 %1.sub13:sgpr_512 = S_MOV_B32 1135007 %1.sub14:sgpr_512 = S_MOV_B32 1145008 %1.sub15:sgpr_512 = S_MOV_B32 1155009 S_NOP 0, implicit %1.sub12_sub13_sub14_sub155010 5011 undef %2.sub4:sgpr_512 = S_MOV_B32 245012 %2.sub5:sgpr_512 = S_MOV_B32 255013 %2.sub6:sgpr_512 = S_MOV_B32 265014 %2.sub7:sgpr_512 = S_MOV_B32 275015 S_NOP 0, implicit %2.sub4_sub5_sub6_sub75016 5017...5018# Skip test_sgpr_512_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_5125019# Skip test_sgpr_512_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_5125020---5021name: test_sgpr_512_w2565022tracksRegLiveness: true5023body: |5024 bb.0:5025 ; CHECK-LABEL: name: test_sgpr_512_w2565026 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 05027 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 15028 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 25029 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 35030 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 45031 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 55032 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 65033 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 75034 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]5035 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 145036 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 155037 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 165038 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 175039 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 185040 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 195041 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 1105042 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 1115043 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]5044 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 285045 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 295046 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 2105047 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 2115048 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 2125049 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 2135050 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 2145051 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 2155052 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]5053 undef %0.sub0:sgpr_512 = S_MOV_B32 005054 %0.sub1:sgpr_512 = S_MOV_B32 015055 %0.sub2:sgpr_512 = S_MOV_B32 025056 %0.sub3:sgpr_512 = S_MOV_B32 035057 %0.sub4:sgpr_512 = S_MOV_B32 045058 %0.sub5:sgpr_512 = S_MOV_B32 055059 %0.sub6:sgpr_512 = S_MOV_B32 065060 %0.sub7:sgpr_512 = S_MOV_B32 075061 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub75062 5063 undef %1.sub4:sgpr_512 = S_MOV_B32 145064 %1.sub5:sgpr_512 = S_MOV_B32 155065 %1.sub6:sgpr_512 = S_MOV_B32 165066 %1.sub7:sgpr_512 = S_MOV_B32 175067 %1.sub8:sgpr_512 = S_MOV_B32 185068 %1.sub9:sgpr_512 = S_MOV_B32 195069 %1.sub10:sgpr_512 = S_MOV_B32 1105070 %1.sub11:sgpr_512 = S_MOV_B32 1115071 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub115072 5073 undef %2.sub8:sgpr_512 = S_MOV_B32 285074 %2.sub9:sgpr_512 = S_MOV_B32 295075 %2.sub10:sgpr_512 = S_MOV_B32 2105076 %2.sub11:sgpr_512 = S_MOV_B32 2115077 %2.sub12:sgpr_512 = S_MOV_B32 2125078 %2.sub13:sgpr_512 = S_MOV_B32 2135079 %2.sub14:sgpr_512 = S_MOV_B32 2145080 %2.sub15:sgpr_512 = S_MOV_B32 2155081 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub155082 5083...5084---5085name: test_sgpr_1024_w325086tracksRegLiveness: true5087body: |5088 bb.0:5089 ; CHECK-LABEL: name: test_sgpr_1024_w325090 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 05091 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]5092 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 115093 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]5094 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 2315095 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]5096 undef %0.sub0:sgpr_1024 = S_MOV_B32 005097 S_NOP 0, implicit %0.sub05098 5099 undef %1.sub1:sgpr_1024 = S_MOV_B32 115100 S_NOP 0, implicit %1.sub15101 5102 undef %2.sub31:sgpr_1024 = S_MOV_B32 2315103 S_NOP 0, implicit %2.sub315104 5105...5106---5107name: test_sgpr_1024_w645108tracksRegLiveness: true5109body: |5110 bb.0:5111 ; CHECK-LABEL: name: test_sgpr_1024_w645112 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 05113 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 15114 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]5115 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 125116 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 135117 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]5118 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 2305119 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 2315120 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]5121 undef %0.sub0:sgpr_1024 = S_MOV_B32 005122 %0.sub1:sgpr_1024 = S_MOV_B32 015123 S_NOP 0, implicit %0.sub0_sub15124 5125 undef %1.sub2:sgpr_1024 = S_MOV_B32 125126 %1.sub3:sgpr_1024 = S_MOV_B32 135127 S_NOP 0, implicit %1.sub2_sub35128 5129 undef %2.sub30:sgpr_1024 = S_MOV_B32 2305130 %2.sub31:sgpr_1024 = S_MOV_B32 2315131 S_NOP 0, implicit %2.sub30_sub315132 5133...5134# Skip test_sgpr_1024_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_10245135---5136name: test_sgpr_1024_w1285137tracksRegLiveness: true5138body: |5139 bb.0:5140 ; CHECK-LABEL: name: test_sgpr_1024_w1285141 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 05142 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 15143 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 25144 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 35145 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]5146 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 1285147 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 1295148 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 1305149 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 1315150 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]5151 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 245152 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 255153 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_128 = S_MOV_B32 265154 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_128 = S_MOV_B32 275155 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]5156 undef %0.sub0:sgpr_1024 = S_MOV_B32 005157 %0.sub1:sgpr_1024 = S_MOV_B32 015158 %0.sub2:sgpr_1024 = S_MOV_B32 025159 %0.sub3:sgpr_1024 = S_MOV_B32 035160 S_NOP 0, implicit %0.sub0_sub1_sub2_sub35161 5162 undef %1.sub28:sgpr_1024 = S_MOV_B32 1285163 %1.sub29:sgpr_1024 = S_MOV_B32 1295164 %1.sub30:sgpr_1024 = S_MOV_B32 1305165 %1.sub31:sgpr_1024 = S_MOV_B32 1315166 S_NOP 0, implicit %1.sub28_sub29_sub30_sub315167 5168 undef %2.sub4:sgpr_1024 = S_MOV_B32 245169 %2.sub5:sgpr_1024 = S_MOV_B32 255170 %2.sub6:sgpr_1024 = S_MOV_B32 265171 %2.sub7:sgpr_1024 = S_MOV_B32 275172 S_NOP 0, implicit %2.sub4_sub5_sub6_sub75173 5174...5175# Skip test_sgpr_1024_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_10245176# Skip test_sgpr_1024_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_10245177---5178name: test_sgpr_1024_w2565179tracksRegLiveness: true5180body: |5181 bb.0:5182 ; CHECK-LABEL: name: test_sgpr_1024_w2565183 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 05184 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 15185 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 25186 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 35187 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 45188 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 55189 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 65190 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 75191 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]5192 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 1245193 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 1255194 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 1265195 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 1275196 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 1285197 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 1295198 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 1305199 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 1315200 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]5201 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_256 = S_MOV_B32 245202 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_256 = S_MOV_B32 255203 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_256 = S_MOV_B32 265204 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_256 = S_MOV_B32 275205 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub4:sgpr_256 = S_MOV_B32 285206 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub5:sgpr_256 = S_MOV_B32 295207 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub6:sgpr_256 = S_MOV_B32 2105208 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub7:sgpr_256 = S_MOV_B32 2115209 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]5210 undef %0.sub0:sgpr_1024 = S_MOV_B32 005211 %0.sub1:sgpr_1024 = S_MOV_B32 015212 %0.sub2:sgpr_1024 = S_MOV_B32 025213 %0.sub3:sgpr_1024 = S_MOV_B32 035214 %0.sub4:sgpr_1024 = S_MOV_B32 045215 %0.sub5:sgpr_1024 = S_MOV_B32 055216 %0.sub6:sgpr_1024 = S_MOV_B32 065217 %0.sub7:sgpr_1024 = S_MOV_B32 075218 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub75219 5220 undef %1.sub24:sgpr_1024 = S_MOV_B32 1245221 %1.sub25:sgpr_1024 = S_MOV_B32 1255222 %1.sub26:sgpr_1024 = S_MOV_B32 1265223 %1.sub27:sgpr_1024 = S_MOV_B32 1275224 %1.sub28:sgpr_1024 = S_MOV_B32 1285225 %1.sub29:sgpr_1024 = S_MOV_B32 1295226 %1.sub30:sgpr_1024 = S_MOV_B32 1305227 %1.sub31:sgpr_1024 = S_MOV_B32 1315228 S_NOP 0, implicit %1.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub315229 5230 undef %2.sub4:sgpr_1024 = S_MOV_B32 245231 %2.sub5:sgpr_1024 = S_MOV_B32 255232 %2.sub6:sgpr_1024 = S_MOV_B32 265233 %2.sub7:sgpr_1024 = S_MOV_B32 275234 %2.sub8:sgpr_1024 = S_MOV_B32 285235 %2.sub9:sgpr_1024 = S_MOV_B32 295236 %2.sub10:sgpr_1024 = S_MOV_B32 2105237 %2.sub11:sgpr_1024 = S_MOV_B32 2115238 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub115239 5240...5241---5242name: test_sgpr_1024_w5125243tracksRegLiveness: true5244body: |5245 bb.0:5246 ; CHECK-LABEL: name: test_sgpr_1024_w5125247 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_512 = S_MOV_B32 05248 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_512 = S_MOV_B32 15249 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_512 = S_MOV_B32 25250 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_512 = S_MOV_B32 35251 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub4:sgpr_512 = S_MOV_B32 45252 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub5:sgpr_512 = S_MOV_B32 55253 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub6:sgpr_512 = S_MOV_B32 65254 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub7:sgpr_512 = S_MOV_B32 75255 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub8:sgpr_512 = S_MOV_B32 85256 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub9:sgpr_512 = S_MOV_B32 95257 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub10:sgpr_512 = S_MOV_B32 105258 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub11:sgpr_512 = S_MOV_B32 115259 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub12:sgpr_512 = S_MOV_B32 125260 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub13:sgpr_512 = S_MOV_B32 135261 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub14:sgpr_512 = S_MOV_B32 145262 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub15:sgpr_512 = S_MOV_B32 155263 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]5264 ; CHECK-NEXT: undef [[S_MOV_B32_1:%[0-9]+]].sub0:sgpr_512 = S_MOV_B32 1165265 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub1:sgpr_512 = S_MOV_B32 1175266 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub2:sgpr_512 = S_MOV_B32 1185267 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub3:sgpr_512 = S_MOV_B32 1195268 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub4:sgpr_512 = S_MOV_B32 1205269 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub5:sgpr_512 = S_MOV_B32 1215270 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub6:sgpr_512 = S_MOV_B32 1225271 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub7:sgpr_512 = S_MOV_B32 1235272 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub8:sgpr_512 = S_MOV_B32 1245273 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub9:sgpr_512 = S_MOV_B32 1255274 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub10:sgpr_512 = S_MOV_B32 1265275 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub11:sgpr_512 = S_MOV_B32 1275276 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub12:sgpr_512 = S_MOV_B32 1285277 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub13:sgpr_512 = S_MOV_B32 1295278 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub14:sgpr_512 = S_MOV_B32 1305279 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]].sub15:sgpr_512 = S_MOV_B32 1315280 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]5281 ; CHECK-NEXT: undef [[S_MOV_B32_2:%[0-9]+]].sub0:sgpr_512 = S_MOV_B32 245282 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub1:sgpr_512 = S_MOV_B32 255283 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub2:sgpr_512 = S_MOV_B32 265284 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub3:sgpr_512 = S_MOV_B32 275285 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub4:sgpr_512 = S_MOV_B32 285286 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub5:sgpr_512 = S_MOV_B32 295287 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub6:sgpr_512 = S_MOV_B32 2105288 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub7:sgpr_512 = S_MOV_B32 2115289 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub8:sgpr_512 = S_MOV_B32 2125290 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub9:sgpr_512 = S_MOV_B32 2135291 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub10:sgpr_512 = S_MOV_B32 2145292 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub11:sgpr_512 = S_MOV_B32 2155293 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub12:sgpr_512 = S_MOV_B32 2165294 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub13:sgpr_512 = S_MOV_B32 2175295 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub14:sgpr_512 = S_MOV_B32 2185296 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]].sub15:sgpr_512 = S_MOV_B32 2195297 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]5298 undef %0.sub0:sgpr_1024 = S_MOV_B32 005299 %0.sub1:sgpr_1024 = S_MOV_B32 015300 %0.sub2:sgpr_1024 = S_MOV_B32 025301 %0.sub3:sgpr_1024 = S_MOV_B32 035302 %0.sub4:sgpr_1024 = S_MOV_B32 045303 %0.sub5:sgpr_1024 = S_MOV_B32 055304 %0.sub6:sgpr_1024 = S_MOV_B32 065305 %0.sub7:sgpr_1024 = S_MOV_B32 075306 %0.sub8:sgpr_1024 = S_MOV_B32 085307 %0.sub9:sgpr_1024 = S_MOV_B32 095308 %0.sub10:sgpr_1024 = S_MOV_B32 0105309 %0.sub11:sgpr_1024 = S_MOV_B32 0115310 %0.sub12:sgpr_1024 = S_MOV_B32 0125311 %0.sub13:sgpr_1024 = S_MOV_B32 0135312 %0.sub14:sgpr_1024 = S_MOV_B32 0145313 %0.sub15:sgpr_1024 = S_MOV_B32 0155314 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub155315 5316 undef %1.sub16:sgpr_1024 = S_MOV_B32 1165317 %1.sub17:sgpr_1024 = S_MOV_B32 1175318 %1.sub18:sgpr_1024 = S_MOV_B32 1185319 %1.sub19:sgpr_1024 = S_MOV_B32 1195320 %1.sub20:sgpr_1024 = S_MOV_B32 1205321 %1.sub21:sgpr_1024 = S_MOV_B32 1215322 %1.sub22:sgpr_1024 = S_MOV_B32 1225323 %1.sub23:sgpr_1024 = S_MOV_B32 1235324 %1.sub24:sgpr_1024 = S_MOV_B32 1245325 %1.sub25:sgpr_1024 = S_MOV_B32 1255326 %1.sub26:sgpr_1024 = S_MOV_B32 1265327 %1.sub27:sgpr_1024 = S_MOV_B32 1275328 %1.sub28:sgpr_1024 = S_MOV_B32 1285329 %1.sub29:sgpr_1024 = S_MOV_B32 1295330 %1.sub30:sgpr_1024 = S_MOV_B32 1305331 %1.sub31:sgpr_1024 = S_MOV_B32 1315332 S_NOP 0, implicit %1.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub315333 5334 undef %2.sub4:sgpr_1024 = S_MOV_B32 245335 %2.sub5:sgpr_1024 = S_MOV_B32 255336 %2.sub6:sgpr_1024 = S_MOV_B32 265337 %2.sub7:sgpr_1024 = S_MOV_B32 275338 %2.sub8:sgpr_1024 = S_MOV_B32 285339 %2.sub9:sgpr_1024 = S_MOV_B32 295340 %2.sub10:sgpr_1024 = S_MOV_B32 2105341 %2.sub11:sgpr_1024 = S_MOV_B32 2115342 %2.sub12:sgpr_1024 = S_MOV_B32 2125343 %2.sub13:sgpr_1024 = S_MOV_B32 2135344 %2.sub14:sgpr_1024 = S_MOV_B32 2145345 %2.sub15:sgpr_1024 = S_MOV_B32 2155346 %2.sub16:sgpr_1024 = S_MOV_B32 2165347 %2.sub17:sgpr_1024 = S_MOV_B32 2175348 %2.sub18:sgpr_1024 = S_MOV_B32 2185349 %2.sub19:sgpr_1024 = S_MOV_B32 2195350 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub195351 5352...5353