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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s4---5name: test_subregs_composition_vreg_10246tracksRegLiveness: true7body: |8 bb.0:9 ; CHECK-LABEL: name: test_subregs_composition_vreg_102410 ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec11 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec12 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub113 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1_sub214 ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec15 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec16 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub217 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1_sub2_sub318 ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec19 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec20 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub321 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub1_sub2_sub3_sub422 ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec23 ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec24 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub425 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub1_sub2_sub3_sub4_sub526 ; CHECK-NEXT: undef [[V_MOV_B32_e32_4:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec27 ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec28 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub0_sub1_sub2_sub3_sub4_sub529 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub2_sub3_sub4_sub5_sub6_sub730 undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec31 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec32 S_NOP 0, implicit %0.sub1_sub233 S_NOP 0, implicit %0.sub2_sub334 35 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec36 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec37 S_NOP 0, implicit %1.sub1_sub2_sub338 S_NOP 0, implicit %1.sub2_sub3_sub439 40 undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec41 %2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec42 S_NOP 0, implicit %2.sub1_sub2_sub3_sub443 S_NOP 0, implicit %2.sub2_sub3_sub4_sub544 45 undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec46 %3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec47 S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub548 S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub649 50 undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec51 %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec52 S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub653 S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub854...55---56name: test_subregs_unknown_regclass_from_instructions57tracksRegLiveness: true58body: |59 bb.0:60 ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions61 ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 162 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 263 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B32_]]64 undef %0.sub4:sgpr_1024 = S_MOV_B32 0165 %0.sub5:sgpr_1024 = S_MOV_B32 0266 %1:vreg_64 = COPY %0.sub4_sub567...68---69name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_6470tracksRegLiveness: true71registers:72 - { id: 0, class: sgpr_1024 }73body: |74 bb.0:75 ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_6476 ; CHECK: dead [[COPY:%[0-9]+]]:vreg_64 = COPY undef %2:sgpr_6477 %1:vreg_64 = COPY undef %0.sub4_sub578...79---80name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec81tracksRegLiveness: true82body: |83 bb.0:84 ; CHECK-LABEL: name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec85 ; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sgpr_64 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 086 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]87 undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 088 %2:vreg_64 = COPY %0.sub2_sub3:sgpr_12889...90---91name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both92tracksRegLiveness: true93body: |94 bb.0:95 ; CHECK-LABEL: name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both96 ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = COPY undef %1:sgpr_3297 ; CHECK-NEXT: dead [[V_LSHL_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_ADD_U32_e64 [[COPY]], 2, undef %3:vgpr_32, implicit $exec98 undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_3299 %3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, 2, undef %2:vgpr_32, implicit $exec100...101 102