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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s4 5target triple = "nvptx64-nvidia-cuda"6 7define i32 @test_simple_rotl(i32 %x) {8; SI-LABEL: test_simple_rotl:9; SI: ; %bb.0:10; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; SI-NEXT: v_alignbit_b32 v0, v0, v0, 2512; SI-NEXT: s_setpc_b64 s[30:31]13;14; VI-LABEL: test_simple_rotl:15; VI: ; %bb.0:16; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17; VI-NEXT: v_alignbit_b32 v0, v0, v0, 2518; VI-NEXT: s_setpc_b64 s[30:31]19 %shl = shl i32 %x, 720 %shr = lshr i32 %x, 2521 %add = add i32 %shl, %shr22 ret i32 %add23}24 25define i32 @test_simple_rotr(i32 %x) {26; SI-LABEL: test_simple_rotr:27; SI: ; %bb.0:28; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)29; SI-NEXT: v_alignbit_b32 v0, v0, v0, 730; SI-NEXT: s_setpc_b64 s[30:31]31;32; VI-LABEL: test_simple_rotr:33; VI: ; %bb.0:34; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; VI-NEXT: v_alignbit_b32 v0, v0, v0, 736; VI-NEXT: s_setpc_b64 s[30:31]37 %shr = lshr i32 %x, 738 %shl = shl i32 %x, 2539 %add = add i32 %shr, %shl40 ret i32 %add41}42 43define i32 @test_rotl_var(i32 %x, i32 %y) {44; SI-LABEL: test_rotl_var:45; SI: ; %bb.0:46; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)47; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v148; SI-NEXT: v_alignbit_b32 v0, v0, v0, v149; SI-NEXT: s_setpc_b64 s[30:31]50;51; VI-LABEL: test_rotl_var:52; VI: ; %bb.0:53; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)54; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v155; VI-NEXT: v_alignbit_b32 v0, v0, v0, v156; VI-NEXT: s_setpc_b64 s[30:31]57 %shl = shl i32 %x, %y58 %sub = sub i32 32, %y59 %shr = lshr i32 %x, %sub60 %add = add i32 %shl, %shr61 ret i32 %add62}63 64define i32 @test_rotr_var(i32 %x, i32 %y) {65; SI-LABEL: test_rotr_var:66; SI: ; %bb.0:67; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; SI-NEXT: v_alignbit_b32 v0, v0, v0, v169; SI-NEXT: s_setpc_b64 s[30:31]70;71; VI-LABEL: test_rotr_var:72; VI: ; %bb.0:73; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; VI-NEXT: v_alignbit_b32 v0, v0, v0, v175; VI-NEXT: s_setpc_b64 s[30:31]76 %shr = lshr i32 %x, %y77 %sub = sub i32 32, %y78 %shl = shl i32 %x, %sub79 %add = add i32 %shr, %shl80 ret i32 %add81}82 83define i32 @test_invalid_rotl_var_and(i32 %x, i32 %y) {84; SI-LABEL: test_invalid_rotl_var_and:85; SI: ; %bb.0:86; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; SI-NEXT: v_lshlrev_b32_e32 v2, v1, v088; SI-NEXT: v_sub_i32_e32 v1, vcc, 0, v189; SI-NEXT: v_lshrrev_b32_e32 v0, v1, v090; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v291; SI-NEXT: s_setpc_b64 s[30:31]92;93; VI-LABEL: test_invalid_rotl_var_and:94; VI: ; %bb.0:95; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)96; VI-NEXT: v_lshlrev_b32_e32 v2, v1, v097; VI-NEXT: v_sub_u32_e32 v1, vcc, 0, v198; VI-NEXT: v_lshrrev_b32_e32 v0, v1, v099; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2100; VI-NEXT: s_setpc_b64 s[30:31]101 %shr = shl i32 %x, %y102 %sub = sub nsw i32 0, %y103 %and = and i32 %sub, 31104 %shl = lshr i32 %x, %and105 %add = add i32 %shl, %shr106 ret i32 %add107}108 109define i32 @test_invalid_rotr_var_and(i32 %x, i32 %y) {110; SI-LABEL: test_invalid_rotr_var_and:111; SI: ; %bb.0:112; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; SI-NEXT: v_lshrrev_b32_e32 v2, v1, v0114; SI-NEXT: v_sub_i32_e32 v1, vcc, 0, v1115; SI-NEXT: v_lshlrev_b32_e32 v0, v1, v0116; SI-NEXT: v_add_i32_e32 v0, vcc, v2, v0117; SI-NEXT: s_setpc_b64 s[30:31]118;119; VI-LABEL: test_invalid_rotr_var_and:120; VI: ; %bb.0:121; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; VI-NEXT: v_lshrrev_b32_e32 v2, v1, v0123; VI-NEXT: v_sub_u32_e32 v1, vcc, 0, v1124; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0125; VI-NEXT: v_add_u32_e32 v0, vcc, v2, v0126; VI-NEXT: s_setpc_b64 s[30:31]127 %shr = lshr i32 %x, %y128 %sub = sub nsw i32 0, %y129 %and = and i32 %sub, 31130 %shl = shl i32 %x, %and131 %add = add i32 %shr, %shl132 ret i32 %add133}134 135define i32 @test_fshl_special_case(i32 %x0, i32 %x1, i32 %y) {136; SI-LABEL: test_fshl_special_case:137; SI: ; %bb.0:138; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0140; SI-NEXT: v_lshrrev_b32_e32 v1, 1, v1141; SI-NEXT: v_xor_b32_e32 v2, 31, v2142; SI-NEXT: v_lshrrev_b32_e32 v1, v2, v1143; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1144; SI-NEXT: s_setpc_b64 s[30:31]145;146; VI-LABEL: test_fshl_special_case:147; VI: ; %bb.0:148; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; VI-NEXT: v_lshlrev_b32_e32 v0, v2, v0150; VI-NEXT: v_lshrrev_b32_e32 v1, 1, v1151; VI-NEXT: v_xor_b32_e32 v2, 31, v2152; VI-NEXT: v_lshrrev_b32_e32 v1, v2, v1153; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1154; VI-NEXT: s_setpc_b64 s[30:31]155 %shl = shl i32 %x0, %y156 %srli = lshr i32 %x1, 1157 %x = xor i32 %y, 31158 %srlo = lshr i32 %srli, %x159 %o = add i32 %shl, %srlo160 ret i32 %o161}162 163define i32 @test_fshr_special_case(i32 %x0, i32 %x1, i32 %y) {164; SI-LABEL: test_fshr_special_case:165; SI: ; %bb.0:166; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)167; SI-NEXT: v_alignbit_b32 v0, v0, v1, v2168; SI-NEXT: s_setpc_b64 s[30:31]169;170; VI-LABEL: test_fshr_special_case:171; VI: ; %bb.0:172; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)173; VI-NEXT: v_alignbit_b32 v0, v0, v1, v2174; VI-NEXT: s_setpc_b64 s[30:31]175 %shl = lshr i32 %x1, %y176 %srli = shl i32 %x0, 1177 %x = xor i32 %y, 31178 %srlo = shl i32 %srli, %x179 %o = add i32 %shl, %srlo180 ret i32 %o181}182 183define i64 @test_rotl_udiv_special_case(i64 %i) {184; SI-LABEL: test_rotl_udiv_special_case:185; SI: ; %bb.0:186; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)187; SI-NEXT: s_mov_b32 s4, 0xaaaaaaaa188; SI-NEXT: s_mov_b32 s5, 0xaaaaaaab189; SI-NEXT: v_mul_hi_u32 v2, v0, s4190; SI-NEXT: v_mul_lo_u32 v3, v0, s4191; SI-NEXT: v_mul_hi_u32 v4, v1, s5192; SI-NEXT: v_mul_lo_u32 v5, v1, s5193; SI-NEXT: v_mul_hi_u32 v0, v0, s5194; SI-NEXT: v_mul_hi_u32 v6, v1, s4195; SI-NEXT: v_mul_lo_u32 v1, v1, s4196; SI-NEXT: v_add_i32_e32 v0, vcc, v5, v0197; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc198; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v0199; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc200; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v0201; SI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc202; SI-NEXT: v_add_i32_e32 v2, vcc, v1, v0203; SI-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc204; SI-NEXT: v_lshr_b64 v[0:1], v[2:3], 5205; SI-NEXT: v_lshlrev_b32_e32 v0, 27, v2206; SI-NEXT: v_and_b32_e32 v0, 0xf0000000, v0207; SI-NEXT: v_or_b32_e32 v1, v0, v1208; SI-NEXT: v_alignbit_b32 v0, v3, v2, 5209; SI-NEXT: s_setpc_b64 s[30:31]210;211; VI-LABEL: test_rotl_udiv_special_case:212; VI: ; %bb.0:213; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)214; VI-NEXT: s_mov_b32 s4, 0xaaaaaaab215; VI-NEXT: v_mul_hi_u32 v2, v0, s4216; VI-NEXT: v_mov_b32_e32 v3, 0217; VI-NEXT: s_mov_b32 s6, 0xaaaaaaaa218; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[2:3]219; VI-NEXT: v_mov_b32_e32 v2, v4220; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s6, v[2:3]221; VI-NEXT: v_add_u32_e32 v2, vcc, v5, v3222; VI-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc223; VI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, s6, v[2:3]224; VI-NEXT: v_lshrrev_b64 v[2:3], 5, v[0:1]225; VI-NEXT: v_lshlrev_b32_e32 v2, 27, v0226; VI-NEXT: v_alignbit_b32 v0, v1, v0, 5227; VI-NEXT: v_and_b32_e32 v1, 0xf0000000, v2228; VI-NEXT: v_or_b32_e32 v1, v1, v3229; VI-NEXT: s_setpc_b64 s[30:31]230 %lhs_div = udiv i64 %i, 3231 %rhs_div = udiv i64 %i, 48232 %lhs_shift = shl i64 %lhs_div, 60233 %out = add i64 %lhs_shift, %rhs_div234 ret i64 %out235}236 237define i32 @test_rotl_mul_special_case(i32 %i) {238; SI-LABEL: test_rotl_mul_special_case:239; SI: ; %bb.0:240; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)241; SI-NEXT: v_mul_lo_u32 v0, v0, 9242; SI-NEXT: v_alignbit_b32 v0, v0, v0, 25243; SI-NEXT: s_setpc_b64 s[30:31]244;245; VI-LABEL: test_rotl_mul_special_case:246; VI: ; %bb.0:247; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)248; VI-NEXT: v_mul_lo_u32 v0, v0, 9249; VI-NEXT: v_alignbit_b32 v0, v0, v0, 25250; VI-NEXT: s_setpc_b64 s[30:31]251 %lhs_mul = mul i32 %i, 9252 %rhs_mul = mul i32 %i, 1152253 %lhs_shift = lshr i32 %lhs_mul, 25254 %out = add i32 %lhs_shift, %rhs_mul255 ret i32 %out256}257 258define i64 @test_rotl_mul_with_mask_special_case(i64 %i) {259; SI-LABEL: test_rotl_mul_with_mask_special_case:260; SI: ; %bb.0:261; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)262; SI-NEXT: v_mul_lo_u32 v1, v1, 9263; SI-NEXT: v_mul_hi_u32 v2, v0, 9264; SI-NEXT: v_add_i32_e32 v1, vcc, v2, v1265; SI-NEXT: v_alignbit_b32 v0, v0, v1, 25266; SI-NEXT: v_and_b32_e32 v0, 0xff, v0267; SI-NEXT: v_mov_b32_e32 v1, 0268; SI-NEXT: s_setpc_b64 s[30:31]269;270; VI-LABEL: test_rotl_mul_with_mask_special_case:271; VI: ; %bb.0:272; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)273; VI-NEXT: v_mul_lo_u32 v1, v1, 9274; VI-NEXT: v_mul_hi_u32 v2, v0, 9275; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1276; VI-NEXT: v_alignbit_b32 v0, v0, v1, 25277; VI-NEXT: v_and_b32_e32 v0, 0xff, v0278; VI-NEXT: v_mov_b32_e32 v1, 0279; VI-NEXT: s_setpc_b64 s[30:31]280 %lhs_mul = mul i64 %i, 1152281 %rhs_mul = mul i64 %i, 9282 %lhs_and = and i64 %lhs_mul, 160283 %rhs_shift = lshr i64 %rhs_mul, 57284 %out = add i64 %lhs_and, %rhs_shift285 ret i64 %out286}287 288define i32 @test_fshl_with_mask_special_case(i32 %x) {289; SI-LABEL: test_fshl_with_mask_special_case:290; SI: ; %bb.0:291; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)292; SI-NEXT: v_or_b32_e32 v1, 1, v0293; SI-NEXT: v_alignbit_b32 v0, v1, v0, 27294; SI-NEXT: v_and_b32_e32 v0, 0xffffffe1, v0295; SI-NEXT: s_setpc_b64 s[30:31]296;297; VI-LABEL: test_fshl_with_mask_special_case:298; VI: ; %bb.0:299; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)300; VI-NEXT: v_or_b32_e32 v1, 1, v0301; VI-NEXT: v_alignbit_b32 v0, v1, v0, 27302; VI-NEXT: v_and_b32_e32 v0, 0xffffffe1, v0303; VI-NEXT: s_setpc_b64 s[30:31]304 %or1 = or i32 %x, 1305 %sh1 = shl i32 %or1, 5306 %sh2 = lshr i32 %x, 27307 %1 = and i32 %sh2, 1308 %r = add i32 %sh1, %1309 ret i32 %r310}311