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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s3 4; BOTH-LABEL: {{^}}s_rotl_i64:5; BOTH-DAG: s_lshl_b646; BOTH-DAG: s_sub_i327; BOTH-DAG: s_lshr_b648; BOTH: s_or_b649; BOTH: s_endpgm10define amdgpu_kernel void @s_rotl_i64(ptr addrspace(1) %in, i64 %x, i64 %y) {11entry:12 %0 = shl i64 %x, %y13 %1 = sub i64 64, %y14 %2 = lshr i64 %x, %115 %3 = or i64 %0, %216 store i64 %3, ptr addrspace(1) %in17 ret void18}19 20; BOTH-LABEL: {{^}}v_rotl_i64:21; SI-DAG: v_lshl_b6422; VI-DAG: v_lshlrev_b6423; BOTH-DAG: v_sub_{{[iu]}}3224; SI: v_lshr_b6425; VI: v_lshrrev_b6426; BOTH: v_or_b3227; BOTH: v_or_b3228; BOTH: s_endpgm29define amdgpu_kernel void @v_rotl_i64(ptr addrspace(1) %in, ptr addrspace(1) %xptr, ptr addrspace(1) %yptr) {30entry:31 %x = load i64, ptr addrspace(1) %xptr, align 832 %y = load i64, ptr addrspace(1) %yptr, align 833 %tmp0 = shl i64 %x, %y34 %tmp1 = sub i64 64, %y35 %tmp2 = lshr i64 %x, %tmp136 %tmp3 = or i64 %tmp0, %tmp237 store i64 %tmp3, ptr addrspace(1) %in, align 838 ret void39}40