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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s3; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX8 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define amdgpu_kernel void @rotl_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {10; R600-LABEL: rotl_i32:11; R600: ; %bb.0: ; %entry12; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]13; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 114; R600-NEXT: CF_END15; R600-NEXT: PAD16; R600-NEXT: ALU clause starting at 4:17; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W,18; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)19; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[2].Z, KC0[2].Z, PV.W,20; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,21; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)22;23; SI-LABEL: rotl_i32:24; SI: ; %bb.0: ; %entry25; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x926; SI-NEXT: s_mov_b32 s7, 0xf00027; SI-NEXT: s_waitcnt lgkmcnt(0)28; SI-NEXT: s_sub_i32 s3, 32, s329; SI-NEXT: s_mov_b32 s6, -130; SI-NEXT: s_mov_b32 s4, s031; SI-NEXT: s_mov_b32 s5, s132; SI-NEXT: v_mov_b32_e32 v0, s333; SI-NEXT: v_alignbit_b32 v0, s2, s2, v034; SI-NEXT: buffer_store_dword v0, off, s[4:7], 035; SI-NEXT: s_endpgm36;37; GFX8-LABEL: rotl_i32:38; GFX8: ; %bb.0: ; %entry39; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2440; GFX8-NEXT: s_waitcnt lgkmcnt(0)41; GFX8-NEXT: s_sub_i32 s3, 32, s342; GFX8-NEXT: v_mov_b32_e32 v0, s343; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v044; GFX8-NEXT: v_mov_b32_e32 v0, s045; GFX8-NEXT: v_mov_b32_e32 v1, s146; GFX8-NEXT: flat_store_dword v[0:1], v247; GFX8-NEXT: s_endpgm48;49; GFX10-LABEL: rotl_i32:50; GFX10: ; %bb.0: ; %entry51; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2452; GFX10-NEXT: v_mov_b32_e32 v0, 053; GFX10-NEXT: s_waitcnt lgkmcnt(0)54; GFX10-NEXT: s_sub_i32 s3, 32, s355; GFX10-NEXT: v_alignbit_b32 v1, s2, s2, s356; GFX10-NEXT: global_store_dword v0, v1, s[0:1]57; GFX10-NEXT: s_endpgm58;59; GFX11-LABEL: rotl_i32:60; GFX11: ; %bb.0: ; %entry61; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2462; GFX11-NEXT: v_mov_b32_e32 v0, 063; GFX11-NEXT: s_waitcnt lgkmcnt(0)64; GFX11-NEXT: s_sub_i32 s3, 32, s365; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)66; GFX11-NEXT: v_alignbit_b32 v1, s2, s2, s367; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]68; GFX11-NEXT: s_endpgm69entry:70 %0 = shl i32 %x, %y71 %1 = sub i32 32, %y72 %2 = lshr i32 %x, %173 %3 = or i32 %0, %274 store i32 %3, ptr addrspace(1) %in75 ret void76}77 78define amdgpu_kernel void @rotl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {79; R600-LABEL: rotl_v2i32:80; R600: ; %bb.0: ; %entry81; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]82; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 183; R600-NEXT: CF_END84; R600-NEXT: PAD85; R600-NEXT: ALU clause starting at 4:86; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[3].Z,87; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)88; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].X, PV.W,89; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[3].Y,90; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)91; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[2].W, KC0[2].W, PV.W,92; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,93; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)94;95; SI-LABEL: rotl_v2i32:96; SI: ; %bb.0: ; %entry97; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb98; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x999; SI-NEXT: s_mov_b32 s7, 0xf000100; SI-NEXT: s_mov_b32 s6, -1101; SI-NEXT: s_waitcnt lgkmcnt(0)102; SI-NEXT: s_sub_i32 s3, 32, s3103; SI-NEXT: s_sub_i32 s2, 32, s2104; SI-NEXT: v_mov_b32_e32 v0, s3105; SI-NEXT: v_alignbit_b32 v1, s1, s1, v0106; SI-NEXT: v_mov_b32_e32 v0, s2107; SI-NEXT: v_alignbit_b32 v0, s0, s0, v0108; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0109; SI-NEXT: s_endpgm110;111; GFX8-LABEL: rotl_v2i32:112; GFX8: ; %bb.0: ; %entry113; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c114; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24115; GFX8-NEXT: s_waitcnt lgkmcnt(0)116; GFX8-NEXT: s_sub_i32 s2, 32, s2117; GFX8-NEXT: s_sub_i32 s3, 32, s3118; GFX8-NEXT: v_mov_b32_e32 v0, s3119; GFX8-NEXT: v_mov_b32_e32 v2, s2120; GFX8-NEXT: v_alignbit_b32 v1, s1, s1, v0121; GFX8-NEXT: v_alignbit_b32 v0, s0, s0, v2122; GFX8-NEXT: v_mov_b32_e32 v2, s4123; GFX8-NEXT: v_mov_b32_e32 v3, s5124; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]125; GFX8-NEXT: s_endpgm126;127; GFX10-LABEL: rotl_v2i32:128; GFX10: ; %bb.0: ; %entry129; GFX10-NEXT: s_clause 0x1130; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c131; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24132; GFX10-NEXT: v_mov_b32_e32 v2, 0133; GFX10-NEXT: s_waitcnt lgkmcnt(0)134; GFX10-NEXT: s_sub_i32 s3, 32, s3135; GFX10-NEXT: s_sub_i32 s2, 32, s2136; GFX10-NEXT: v_alignbit_b32 v1, s1, s1, s3137; GFX10-NEXT: v_alignbit_b32 v0, s0, s0, s2138; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]139; GFX10-NEXT: s_endpgm140;141; GFX11-LABEL: rotl_v2i32:142; GFX11: ; %bb.0: ; %entry143; GFX11-NEXT: s_clause 0x1144; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c145; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24146; GFX11-NEXT: v_mov_b32_e32 v2, 0147; GFX11-NEXT: s_waitcnt lgkmcnt(0)148; GFX11-NEXT: s_sub_i32 s3, 32, s3149; GFX11-NEXT: s_sub_i32 s2, 32, s2150; GFX11-NEXT: v_alignbit_b32 v1, s1, s1, s3151; GFX11-NEXT: v_alignbit_b32 v0, s0, s0, s2152; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]153; GFX11-NEXT: s_endpgm154entry:155 %0 = shl <2 x i32> %x, %y156 %1 = sub <2 x i32> <i32 32, i32 32>, %y157 %2 = lshr <2 x i32> %x, %1158 %3 = or <2 x i32> %0, %2159 store <2 x i32> %3, ptr addrspace(1) %in160 ret void161}162 163define amdgpu_kernel void @rotl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {164; R600-LABEL: rotl_v4i32:165; R600: ; %bb.0: ; %entry166; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]167; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1168; R600-NEXT: CF_END169; R600-NEXT: PAD170; R600-NEXT: ALU clause starting at 4:171; R600-NEXT: SUB_INT * T0.W, literal.x, KC0[5].X,172; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)173; R600-NEXT: BIT_ALIGN_INT T0.W, KC0[4].X, KC0[4].X, PV.W,174; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].W,175; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)176; R600-NEXT: BIT_ALIGN_INT T0.Z, KC0[3].W, KC0[3].W, PS,177; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].Z,178; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)179; R600-NEXT: BIT_ALIGN_INT T0.Y, KC0[3].Z, KC0[3].Z, PV.W,180; R600-NEXT: SUB_INT * T1.W, literal.x, KC0[4].Y,181; R600-NEXT: 32(4.484155e-44), 0(0.000000e+00)182; R600-NEXT: BIT_ALIGN_INT T0.X, KC0[3].Y, KC0[3].Y, PV.W,183; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,184; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)185;186; SI-LABEL: rotl_v4i32:187; SI: ; %bb.0: ; %entry188; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd189; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9190; SI-NEXT: s_mov_b32 s3, 0xf000191; SI-NEXT: s_mov_b32 s2, -1192; SI-NEXT: s_waitcnt lgkmcnt(0)193; SI-NEXT: s_sub_i32 s4, 32, s12194; SI-NEXT: s_sub_i32 s5, 32, s13195; SI-NEXT: s_sub_i32 s6, 32, s15196; SI-NEXT: s_sub_i32 s7, 32, s14197; SI-NEXT: v_mov_b32_e32 v0, s6198; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0199; SI-NEXT: v_mov_b32_e32 v0, s7200; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0201; SI-NEXT: v_mov_b32_e32 v0, s5202; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0203; SI-NEXT: v_mov_b32_e32 v0, s4204; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0205; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0206; SI-NEXT: s_endpgm207;208; GFX8-LABEL: rotl_v4i32:209; GFX8: ; %bb.0: ; %entry210; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34211; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24212; GFX8-NEXT: s_waitcnt lgkmcnt(0)213; GFX8-NEXT: s_sub_i32 s5, 32, s15214; GFX8-NEXT: s_sub_i32 s4, 32, s14215; GFX8-NEXT: v_mov_b32_e32 v0, s5216; GFX8-NEXT: s_sub_i32 s3, 32, s13217; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0218; GFX8-NEXT: v_mov_b32_e32 v0, s4219; GFX8-NEXT: s_sub_i32 s2, 32, s12220; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v0221; GFX8-NEXT: v_mov_b32_e32 v0, s3222; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v0223; GFX8-NEXT: v_mov_b32_e32 v0, s2224; GFX8-NEXT: v_mov_b32_e32 v5, s1225; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0226; GFX8-NEXT: v_mov_b32_e32 v4, s0227; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]228; GFX8-NEXT: s_endpgm229;230; GFX10-LABEL: rotl_v4i32:231; GFX10: ; %bb.0: ; %entry232; GFX10-NEXT: s_clause 0x1233; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34234; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24235; GFX10-NEXT: v_mov_b32_e32 v4, 0236; GFX10-NEXT: s_waitcnt lgkmcnt(0)237; GFX10-NEXT: s_sub_i32 s2, 32, s12238; GFX10-NEXT: s_sub_i32 s3, 32, s13239; GFX10-NEXT: s_sub_i32 s4, 32, s15240; GFX10-NEXT: s_sub_i32 s5, 32, s14241; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s4242; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s5243; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s3244; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s2245; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]246; GFX10-NEXT: s_endpgm247;248; GFX11-LABEL: rotl_v4i32:249; GFX11: ; %bb.0: ; %entry250; GFX11-NEXT: s_clause 0x1251; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34252; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24253; GFX11-NEXT: v_mov_b32_e32 v4, 0254; GFX11-NEXT: s_waitcnt lgkmcnt(0)255; GFX11-NEXT: s_sub_i32 s2, 32, s12256; GFX11-NEXT: s_sub_i32 s3, 32, s13257; GFX11-NEXT: s_sub_i32 s4, 32, s15258; GFX11-NEXT: s_sub_i32 s5, 32, s14259; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s4260; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s5261; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s3262; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s2263; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]264; GFX11-NEXT: s_endpgm265entry:266 %0 = shl <4 x i32> %x, %y267 %1 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y268 %2 = lshr <4 x i32> %x, %1269 %3 = or <4 x i32> %0, %2270 store <4 x i32> %3, ptr addrspace(1) %in271 ret void272}273 274declare i16 @llvm.fshl.i16(i16, i16, i16)275 276define void @test_rotl_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr addrspace(1) nocapture readonly %sourceB, ptr addrspace(1) nocapture %destValues) {277; R600-LABEL: test_rotl_i16:278; R600: ; %bb.0: ; %entry279; R600-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]280; R600-NEXT: TEX 0 @8281; R600-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]282; R600-NEXT: TEX 0 @10283; R600-NEXT: ALU 21, @14, KC0[CB0:0-32], KC1[]284; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X285; R600-NEXT: CF_END286; R600-NEXT: PAD287; R600-NEXT: Fetch clause starting at 8:288; R600-NEXT: VTX_READ_16 T0.X, T0.X, 48, #1289; R600-NEXT: Fetch clause starting at 10:290; R600-NEXT: VTX_READ_16 T1.X, T1.X, 32, #1291; R600-NEXT: ALU clause starting at 12:292; R600-NEXT: MOV * T0.X, KC0[2].Z,293; R600-NEXT: ALU clause starting at 13:294; R600-NEXT: MOV * T1.X, KC0[2].Y,295; R600-NEXT: ALU clause starting at 14:296; R600-NEXT: SUB_INT T0.W, 0.0, T0.X,297; R600-NEXT: AND_INT * T1.W, T0.X, literal.x,298; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)299; R600-NEXT: AND_INT * T0.W, PV.W, literal.x,300; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)301; R600-NEXT: LSHR T0.Z, T1.X, PV.W,302; R600-NEXT: LSHL T0.W, T1.X, T1.W,303; R600-NEXT: ADD_INT * T1.W, KC0[2].W, literal.x,304; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)305; R600-NEXT: AND_INT T2.W, PS, literal.x,306; R600-NEXT: OR_INT * T0.W, PV.W, PV.Z,307; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)308; R600-NEXT: AND_INT T0.W, PS, literal.x,309; R600-NEXT: LSHL * T2.W, PV.W, literal.y,310; R600-NEXT: 65535(9.183409e-41), 3(4.203895e-45)311; R600-NEXT: LSHL T0.X, PV.W, PS,312; R600-NEXT: LSHL * T0.W, literal.x, PS,313; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)314; R600-NEXT: MOV T0.Y, 0.0,315; R600-NEXT: MOV * T0.Z, 0.0,316; R600-NEXT: LSHR * T1.X, T1.W, literal.x,317; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)318;319; SI-LABEL: test_rotl_i16:320; SI: ; %bb.0: ; %entry321; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)322; SI-NEXT: s_mov_b32 s6, 0323; SI-NEXT: s_mov_b32 s7, 0xf000324; SI-NEXT: s_mov_b32 s4, s6325; SI-NEXT: s_mov_b32 s5, s6326; SI-NEXT: buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:48327; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:32328; SI-NEXT: s_waitcnt vmcnt(1)329; SI-NEXT: v_and_b32_e32 v1, 15, v2330; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2331; SI-NEXT: s_waitcnt vmcnt(0)332; SI-NEXT: v_lshlrev_b32_e32 v1, v1, v0333; SI-NEXT: v_and_b32_e32 v2, 15, v2334; SI-NEXT: v_lshrrev_b32_e32 v0, v2, v0335; SI-NEXT: v_or_b32_e32 v0, v1, v0336; SI-NEXT: buffer_store_short v0, v[4:5], s[4:7], 0 addr64 offset:8337; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)338; SI-NEXT: s_setpc_b64 s[30:31]339;340; GFX8-LABEL: test_rotl_i16:341; GFX8: ; %bb.0: ; %entry342; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)343; GFX8-NEXT: v_add_u32_e32 v0, vcc, 32, v0344; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc345; GFX8-NEXT: v_add_u32_e32 v2, vcc, 48, v2346; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc347; GFX8-NEXT: flat_load_ushort v2, v[2:3]348; GFX8-NEXT: flat_load_ushort v0, v[0:1]349; GFX8-NEXT: s_waitcnt vmcnt(0)350; GFX8-NEXT: v_lshlrev_b16_e32 v1, v2, v0351; GFX8-NEXT: v_sub_u16_e32 v2, 0, v2352; GFX8-NEXT: v_lshrrev_b16_e32 v0, v2, v0353; GFX8-NEXT: v_or_b32_e32 v2, v1, v0354; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4355; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc356; GFX8-NEXT: flat_store_short v[0:1], v2357; GFX8-NEXT: s_waitcnt vmcnt(0)358; GFX8-NEXT: s_setpc_b64 s[30:31]359;360; GFX10-LABEL: test_rotl_i16:361; GFX10: ; %bb.0: ; %entry362; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)363; GFX10-NEXT: global_load_ushort v6, v[2:3], off offset:48364; GFX10-NEXT: global_load_ushort v7, v[0:1], off offset:32365; GFX10-NEXT: s_waitcnt vmcnt(1)366; GFX10-NEXT: v_sub_nc_u16 v0, 0, v6367; GFX10-NEXT: s_waitcnt vmcnt(0)368; GFX10-NEXT: v_lshlrev_b16 v1, v6, v7369; GFX10-NEXT: v_lshrrev_b16 v0, v0, v7370; GFX10-NEXT: v_or_b32_e32 v0, v1, v0371; GFX10-NEXT: global_store_short v[4:5], v0, off offset:8372; GFX10-NEXT: s_setpc_b64 s[30:31]373;374; GFX11-TRUE16-LABEL: test_rotl_i16:375; GFX11-TRUE16: ; %bb.0: ; %entry376; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)377; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v[2:3], off offset:48378; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off offset:32379; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)380; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.h, 0, v2.l381; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, v2.l, v0.l382; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)383; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, v0.h, v0.l384; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l385; GFX11-TRUE16-NEXT: global_store_b16 v[4:5], v0, off offset:8386; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]387;388; GFX11-FAKE16-LABEL: test_rotl_i16:389; GFX11-FAKE16: ; %bb.0: ; %entry390; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)391; GFX11-FAKE16-NEXT: global_load_u16 v2, v[2:3], off offset:48392; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off offset:32393; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)394; GFX11-FAKE16-NEXT: v_sub_nc_u16 v1, 0, v2395; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)396; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, v2, v0397; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)398; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, v1, v0399; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0400; GFX11-FAKE16-NEXT: global_store_b16 v[4:5], v0, off offset:8401; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]402entry:403 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16404 %a = load i16, ptr addrspace(1) %arrayidx405 %arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %sourceB, i64 24406 %b = load i16, ptr addrspace(1) %arrayidx2407 %c = tail call i16 @llvm.fshl.i16(i16 %a, i16 %a, i16 %b)408 %arrayidx5 = getelementptr inbounds i16, ptr addrspace(1) %destValues, i64 4409 store i16 %c, ptr addrspace(1) %arrayidx5410 ret void411}412