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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s3 4; BOTH-LABEL: {{^}}s_rotr_i64:5; BOTH-DAG: s_sub_i326; BOTH-DAG: s_lshr_b647; BOTH-DAG: s_lshl_b648; BOTH: s_or_b649define amdgpu_kernel void @s_rotr_i64(ptr addrspace(1) %in, i64 %x, i64 %y) {10entry:11 %tmp0 = sub i64 64, %y12 %tmp1 = shl i64 %x, %tmp013 %tmp2 = lshr i64 %x, %y14 %tmp3 = or i64 %tmp1, %tmp215 store i64 %tmp3, ptr addrspace(1) %in16 ret void17}18 19; BOTH-LABEL: {{^}}v_rotr_i64:20; BOTH-DAG: v_sub_{{[iu]}}3221; SI-DAG: v_lshr_b6422; SI-DAG: v_lshl_b6423; VI-DAG: v_lshrrev_b6424; VI-DAG: v_lshlrev_b6425; BOTH: v_or_b3226; BOTH: v_or_b3227define amdgpu_kernel void @v_rotr_i64(ptr addrspace(1) %in, ptr addrspace(1) %xptr, ptr addrspace(1) %yptr) {28entry:29 %x = load i64, ptr addrspace(1) %xptr, align 830 %y = load i64, ptr addrspace(1) %yptr, align 831 %tmp0 = sub i64 64, %y32 %tmp1 = shl i64 %x, %tmp033 %tmp2 = lshr i64 %x, %y34 %tmp3 = or i64 %tmp1, %tmp235 store i64 %tmp3, ptr addrspace(1) %in36 ret void37}38 39; BOTH-LABEL: {{^}}s_rotr_v2i64:40define amdgpu_kernel void @s_rotr_v2i64(ptr addrspace(1) %in, <2 x i64> %x, <2 x i64> %y) {41entry:42 %tmp0 = sub <2 x i64> <i64 64, i64 64>, %y43 %tmp1 = shl <2 x i64> %x, %tmp044 %tmp2 = lshr <2 x i64> %x, %y45 %tmp3 = or <2 x i64> %tmp1, %tmp246 store <2 x i64> %tmp3, ptr addrspace(1) %in47 ret void48}49 50; BOTH-LABEL: {{^}}v_rotr_v2i64:51define amdgpu_kernel void @v_rotr_v2i64(ptr addrspace(1) %in, ptr addrspace(1) %xptr, ptr addrspace(1) %yptr) {52entry:53 %x = load <2 x i64>, ptr addrspace(1) %xptr, align 854 %y = load <2 x i64>, ptr addrspace(1) %yptr, align 855 %tmp0 = sub <2 x i64> <i64 64, i64 64>, %y56 %tmp1 = shl <2 x i64> %x, %tmp057 %tmp2 = lshr <2 x i64> %x, %y58 %tmp3 = or <2 x i64> %tmp1, %tmp259 store <2 x i64> %tmp3, ptr addrspace(1) %in60 ret void61}62