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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s3; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX8 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define amdgpu_kernel void @rotr_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {10; R600-LABEL: rotr_i32:11; R600: ; %bb.0: ; %entry12; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]13; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 114; R600-NEXT: CF_END15; R600-NEXT: PAD16; R600-NEXT: ALU clause starting at 4:17; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,18; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)19; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].Z, KC0[2].W,20;21; SI-LABEL: rotr_i32:22; SI: ; %bb.0: ; %entry23; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x924; SI-NEXT: s_mov_b32 s7, 0xf00025; SI-NEXT: s_mov_b32 s6, -126; SI-NEXT: s_waitcnt lgkmcnt(0)27; SI-NEXT: s_mov_b32 s4, s028; SI-NEXT: s_mov_b32 s5, s129; SI-NEXT: v_mov_b32_e32 v0, s330; SI-NEXT: v_alignbit_b32 v0, s2, s2, v031; SI-NEXT: buffer_store_dword v0, off, s[4:7], 032; SI-NEXT: s_endpgm33;34; GFX8-LABEL: rotr_i32:35; GFX8: ; %bb.0: ; %entry36; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2437; GFX8-NEXT: s_waitcnt lgkmcnt(0)38; GFX8-NEXT: v_mov_b32_e32 v0, s339; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v040; GFX8-NEXT: v_mov_b32_e32 v0, s041; GFX8-NEXT: v_mov_b32_e32 v1, s142; GFX8-NEXT: flat_store_dword v[0:1], v243; GFX8-NEXT: s_endpgm44;45; GFX10-LABEL: rotr_i32:46; GFX10: ; %bb.0: ; %entry47; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2448; GFX10-NEXT: v_mov_b32_e32 v0, 049; GFX10-NEXT: s_waitcnt lgkmcnt(0)50; GFX10-NEXT: v_alignbit_b32 v1, s2, s2, s351; GFX10-NEXT: global_store_dword v0, v1, s[0:1]52; GFX10-NEXT: s_endpgm53;54; GFX11-LABEL: rotr_i32:55; GFX11: ; %bb.0: ; %entry56; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2457; GFX11-NEXT: v_mov_b32_e32 v0, 058; GFX11-NEXT: s_waitcnt lgkmcnt(0)59; GFX11-NEXT: v_alignbit_b32 v1, s2, s2, s360; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]61; GFX11-NEXT: s_endpgm62entry:63 %tmp0 = sub i32 32, %y64 %tmp1 = shl i32 %x, %tmp065 %tmp2 = lshr i32 %x, %y66 %tmp3 = or i32 %tmp1, %tmp267 store i32 %tmp3, ptr addrspace(1) %in68 ret void69}70 71define amdgpu_kernel void @rotr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {72; R600-LABEL: rotr_v2i32:73; R600: ; %bb.0: ; %entry74; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]75; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 176; R600-NEXT: CF_END77; R600-NEXT: PAD78; R600-NEXT: ALU clause starting at 4:79; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].X, KC0[3].Z,80; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[2].W, KC0[3].Y,81; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,82; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)83;84; SI-LABEL: rotr_v2i32:85; SI: ; %bb.0: ; %entry86; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb87; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x988; SI-NEXT: s_mov_b32 s7, 0xf00089; SI-NEXT: s_mov_b32 s6, -190; SI-NEXT: s_waitcnt lgkmcnt(0)91; SI-NEXT: v_mov_b32_e32 v0, s392; SI-NEXT: v_alignbit_b32 v1, s1, s1, v093; SI-NEXT: v_mov_b32_e32 v0, s294; SI-NEXT: v_alignbit_b32 v0, s0, s0, v095; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 096; SI-NEXT: s_endpgm97;98; GFX8-LABEL: rotr_v2i32:99; GFX8: ; %bb.0: ; %entry100; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c101; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24102; GFX8-NEXT: s_waitcnt lgkmcnt(0)103; GFX8-NEXT: v_mov_b32_e32 v0, s3104; GFX8-NEXT: v_mov_b32_e32 v2, s2105; GFX8-NEXT: v_alignbit_b32 v1, s1, s1, v0106; GFX8-NEXT: v_alignbit_b32 v0, s0, s0, v2107; GFX8-NEXT: v_mov_b32_e32 v2, s4108; GFX8-NEXT: v_mov_b32_e32 v3, s5109; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]110; GFX8-NEXT: s_endpgm111;112; GFX10-LABEL: rotr_v2i32:113; GFX10: ; %bb.0: ; %entry114; GFX10-NEXT: s_clause 0x1115; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c116; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24117; GFX10-NEXT: v_mov_b32_e32 v2, 0118; GFX10-NEXT: s_waitcnt lgkmcnt(0)119; GFX10-NEXT: v_alignbit_b32 v1, s1, s1, s3120; GFX10-NEXT: v_alignbit_b32 v0, s0, s0, s2121; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]122; GFX10-NEXT: s_endpgm123;124; GFX11-LABEL: rotr_v2i32:125; GFX11: ; %bb.0: ; %entry126; GFX11-NEXT: s_clause 0x1127; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c128; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24129; GFX11-NEXT: v_mov_b32_e32 v2, 0130; GFX11-NEXT: s_waitcnt lgkmcnt(0)131; GFX11-NEXT: v_alignbit_b32 v1, s1, s1, s3132; GFX11-NEXT: v_alignbit_b32 v0, s0, s0, s2133; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]134; GFX11-NEXT: s_endpgm135entry:136 %tmp0 = sub <2 x i32> <i32 32, i32 32>, %y137 %tmp1 = shl <2 x i32> %x, %tmp0138 %tmp2 = lshr <2 x i32> %x, %y139 %tmp3 = or <2 x i32> %tmp1, %tmp2140 store <2 x i32> %tmp3, ptr addrspace(1) %in141 ret void142}143 144define amdgpu_kernel void @rotr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {145; R600-LABEL: rotr_v4i32:146; R600: ; %bb.0: ; %entry147; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]148; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1149; R600-NEXT: CF_END150; R600-NEXT: PAD151; R600-NEXT: ALU clause starting at 4:152; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[4].X, KC0[5].X,153; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[3].W, KC0[4].W,154; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[3].Z, KC0[4].Z,155; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[3].Y, KC0[4].Y,156; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,157; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)158;159; SI-LABEL: rotr_v4i32:160; SI: ; %bb.0: ; %entry161; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd162; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9163; SI-NEXT: s_mov_b32 s3, 0xf000164; SI-NEXT: s_mov_b32 s2, -1165; SI-NEXT: s_waitcnt lgkmcnt(0)166; SI-NEXT: v_mov_b32_e32 v0, s15167; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0168; SI-NEXT: v_mov_b32_e32 v0, s14169; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0170; SI-NEXT: v_mov_b32_e32 v0, s13171; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0172; SI-NEXT: v_mov_b32_e32 v0, s12173; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0174; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0175; SI-NEXT: s_endpgm176;177; GFX8-LABEL: rotr_v4i32:178; GFX8: ; %bb.0: ; %entry179; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34180; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24181; GFX8-NEXT: s_waitcnt lgkmcnt(0)182; GFX8-NEXT: v_mov_b32_e32 v0, s15183; GFX8-NEXT: v_mov_b32_e32 v1, s14184; GFX8-NEXT: v_mov_b32_e32 v4, s13185; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0186; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v1187; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v4188; GFX8-NEXT: v_mov_b32_e32 v0, s12189; GFX8-NEXT: v_mov_b32_e32 v5, s1190; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0191; GFX8-NEXT: v_mov_b32_e32 v4, s0192; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]193; GFX8-NEXT: s_endpgm194;195; GFX10-LABEL: rotr_v4i32:196; GFX10: ; %bb.0: ; %entry197; GFX10-NEXT: s_clause 0x1198; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34199; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24200; GFX10-NEXT: v_mov_b32_e32 v4, 0201; GFX10-NEXT: s_waitcnt lgkmcnt(0)202; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s15203; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s14204; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s13205; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s12206; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]207; GFX10-NEXT: s_endpgm208;209; GFX11-LABEL: rotr_v4i32:210; GFX11: ; %bb.0: ; %entry211; GFX11-NEXT: s_clause 0x1212; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34213; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24214; GFX11-NEXT: v_mov_b32_e32 v4, 0215; GFX11-NEXT: s_waitcnt lgkmcnt(0)216; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s15217; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s14218; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s13219; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s12220; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]221; GFX11-NEXT: s_endpgm222entry:223 %tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y224 %tmp1 = shl <4 x i32> %x, %tmp0225 %tmp2 = lshr <4 x i32> %x, %y226 %tmp3 = or <4 x i32> %tmp1, %tmp2227 store <4 x i32> %tmp3, ptr addrspace(1) %in228 ret void229}230 231define amdgpu_kernel void @rotr_v8i32(ptr addrspace(1) %in, <8 x i32> %x, <8 x i32> %y) {232; R600-LABEL: rotr_v8i32:233; R600: ; %bb.0: ; %entry234; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]235; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 0236; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1237; R600-NEXT: CF_END238; R600-NEXT: ALU clause starting at 4:239; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[5].X, KC0[5].X, KC0[7].X,240; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[4].W, KC0[4].W, KC0[6].W,241; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[4].Z, KC0[4].Z, KC0[6].Z,242; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[4].Y, KC0[4].Y, KC0[6].Y,243; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,244; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)245; R600-NEXT: BIT_ALIGN_INT * T2.W, KC0[6].X, KC0[6].X, KC0[8].X,246; R600-NEXT: BIT_ALIGN_INT * T2.Z, KC0[5].W, KC0[5].W, KC0[7].W,247; R600-NEXT: BIT_ALIGN_INT * T2.Y, KC0[5].Z, KC0[5].Z, KC0[7].Z,248; R600-NEXT: BIT_ALIGN_INT * T2.X, KC0[5].Y, KC0[5].Y, KC0[7].Y,249; R600-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,250; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)251; R600-NEXT: LSHR * T3.X, PV.W, literal.x,252; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)253;254; SI-LABEL: rotr_v8i32:255; SI: ; %bb.0: ; %entry256; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x11257; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9258; SI-NEXT: s_mov_b32 s3, 0xf000259; SI-NEXT: s_mov_b32 s2, -1260; SI-NEXT: s_waitcnt lgkmcnt(0)261; SI-NEXT: v_mov_b32_e32 v0, s19262; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0263; SI-NEXT: v_mov_b32_e32 v0, s18264; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0265; SI-NEXT: v_mov_b32_e32 v0, s17266; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0267; SI-NEXT: v_mov_b32_e32 v0, s16268; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0269; SI-NEXT: v_mov_b32_e32 v4, s23270; SI-NEXT: v_alignbit_b32 v7, s15, s15, v4271; SI-NEXT: v_mov_b32_e32 v4, s22272; SI-NEXT: v_alignbit_b32 v6, s14, s14, v4273; SI-NEXT: v_mov_b32_e32 v4, s21274; SI-NEXT: v_alignbit_b32 v5, s13, s13, v4275; SI-NEXT: v_mov_b32_e32 v4, s20276; SI-NEXT: v_alignbit_b32 v4, s12, s12, v4277; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16278; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0279; SI-NEXT: s_endpgm280;281; GFX8-LABEL: rotr_v8i32:282; GFX8: ; %bb.0: ; %entry283; GFX8-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44284; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24285; GFX8-NEXT: s_waitcnt lgkmcnt(0)286; GFX8-NEXT: v_mov_b32_e32 v1, s18287; GFX8-NEXT: v_mov_b32_e32 v4, s17288; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v1289; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v4290; GFX8-NEXT: v_mov_b32_e32 v4, s23291; GFX8-NEXT: v_alignbit_b32 v7, s15, s15, v4292; GFX8-NEXT: v_mov_b32_e32 v4, s22293; GFX8-NEXT: s_add_u32 s2, s0, 16294; GFX8-NEXT: v_alignbit_b32 v6, s14, s14, v4295; GFX8-NEXT: v_mov_b32_e32 v4, s21296; GFX8-NEXT: s_addc_u32 s3, s1, 0297; GFX8-NEXT: v_alignbit_b32 v5, s13, s13, v4298; GFX8-NEXT: v_mov_b32_e32 v4, s20299; GFX8-NEXT: v_mov_b32_e32 v9, s3300; GFX8-NEXT: v_mov_b32_e32 v0, s19301; GFX8-NEXT: v_alignbit_b32 v4, s12, s12, v4302; GFX8-NEXT: v_mov_b32_e32 v8, s2303; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0304; GFX8-NEXT: v_mov_b32_e32 v0, s16305; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]306; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0307; GFX8-NEXT: v_mov_b32_e32 v5, s1308; GFX8-NEXT: v_mov_b32_e32 v4, s0309; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]310; GFX8-NEXT: s_endpgm311;312; GFX10-LABEL: rotr_v8i32:313; GFX10: ; %bb.0: ; %entry314; GFX10-NEXT: s_clause 0x1315; GFX10-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44316; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24317; GFX10-NEXT: v_mov_b32_e32 v8, 0318; GFX10-NEXT: s_waitcnt lgkmcnt(0)319; GFX10-NEXT: v_alignbit_b32 v7, s15, s15, s23320; GFX10-NEXT: v_alignbit_b32 v6, s14, s14, s22321; GFX10-NEXT: v_alignbit_b32 v5, s13, s13, s21322; GFX10-NEXT: v_alignbit_b32 v4, s12, s12, s20323; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s19324; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s18325; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s17326; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s16327; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16328; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]329; GFX10-NEXT: s_endpgm330;331; GFX11-LABEL: rotr_v8i32:332; GFX11: ; %bb.0: ; %entry333; GFX11-NEXT: s_clause 0x1334; GFX11-NEXT: s_load_b512 s[8:23], s[4:5], 0x44335; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24336; GFX11-NEXT: v_mov_b32_e32 v8, 0337; GFX11-NEXT: s_waitcnt lgkmcnt(0)338; GFX11-NEXT: v_alignbit_b32 v7, s15, s15, s23339; GFX11-NEXT: v_alignbit_b32 v6, s14, s14, s22340; GFX11-NEXT: v_alignbit_b32 v5, s13, s13, s21341; GFX11-NEXT: v_alignbit_b32 v4, s12, s12, s20342; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s19343; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s18344; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s17345; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s16346; GFX11-NEXT: s_clause 0x1347; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16348; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1]349; GFX11-NEXT: s_endpgm350entry:351 %tmp0 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, %y352 %tmp1 = shl <8 x i32> %x, %tmp0353 %tmp2 = lshr <8 x i32> %x, %y354 %tmp3 = or <8 x i32> %tmp1, %tmp2355 store <8 x i32> %tmp3, ptr addrspace(1) %in356 ret void357}358 359declare i16 @llvm.fshr.i16(i16, i16, i16)360 361define void @test_rotr_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr addrspace(1) nocapture readonly %sourceB, ptr addrspace(1) nocapture %destValues) {362; R600-LABEL: test_rotr_i16:363; R600: ; %bb.0: ; %entry364; R600-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]365; R600-NEXT: TEX 0 @8366; R600-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]367; R600-NEXT: TEX 0 @10368; R600-NEXT: ALU 21, @14, KC0[CB0:0-32], KC1[]369; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X370; R600-NEXT: CF_END371; R600-NEXT: PAD372; R600-NEXT: Fetch clause starting at 8:373; R600-NEXT: VTX_READ_16 T0.X, T0.X, 48, #1374; R600-NEXT: Fetch clause starting at 10:375; R600-NEXT: VTX_READ_16 T1.X, T1.X, 32, #1376; R600-NEXT: ALU clause starting at 12:377; R600-NEXT: MOV * T0.X, KC0[2].Z,378; R600-NEXT: ALU clause starting at 13:379; R600-NEXT: MOV * T1.X, KC0[2].Y,380; R600-NEXT: ALU clause starting at 14:381; R600-NEXT: SUB_INT T0.W, 0.0, T0.X,382; R600-NEXT: AND_INT * T1.W, T0.X, literal.x,383; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)384; R600-NEXT: AND_INT * T0.W, PV.W, literal.x,385; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)386; R600-NEXT: LSHL T0.Z, T1.X, PV.W,387; R600-NEXT: LSHR T0.W, T1.X, T1.W,388; R600-NEXT: ADD_INT * T1.W, KC0[2].W, literal.x,389; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)390; R600-NEXT: AND_INT T2.W, PS, literal.x,391; R600-NEXT: OR_INT * T0.W, PV.W, PV.Z,392; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)393; R600-NEXT: AND_INT T0.W, PS, literal.x,394; R600-NEXT: LSHL * T2.W, PV.W, literal.y,395; R600-NEXT: 65535(9.183409e-41), 3(4.203895e-45)396; R600-NEXT: LSHL T0.X, PV.W, PS,397; R600-NEXT: LSHL * T0.W, literal.x, PS,398; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)399; R600-NEXT: MOV T0.Y, 0.0,400; R600-NEXT: MOV * T0.Z, 0.0,401; R600-NEXT: LSHR * T1.X, T1.W, literal.x,402; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)403;404; SI-LABEL: test_rotr_i16:405; SI: ; %bb.0: ; %entry406; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)407; SI-NEXT: s_mov_b32 s6, 0408; SI-NEXT: s_mov_b32 s7, 0xf000409; SI-NEXT: s_mov_b32 s4, s6410; SI-NEXT: s_mov_b32 s5, s6411; SI-NEXT: buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:48412; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:32413; SI-NEXT: s_waitcnt vmcnt(1)414; SI-NEXT: v_and_b32_e32 v1, 15, v2415; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2416; SI-NEXT: s_waitcnt vmcnt(0)417; SI-NEXT: v_lshrrev_b32_e32 v1, v1, v0418; SI-NEXT: v_and_b32_e32 v2, 15, v2419; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0420; SI-NEXT: v_or_b32_e32 v0, v1, v0421; SI-NEXT: buffer_store_short v0, v[4:5], s[4:7], 0 addr64 offset:8422; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)423; SI-NEXT: s_setpc_b64 s[30:31]424;425; GFX8-LABEL: test_rotr_i16:426; GFX8: ; %bb.0: ; %entry427; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)428; GFX8-NEXT: v_add_u32_e32 v0, vcc, 32, v0429; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc430; GFX8-NEXT: v_add_u32_e32 v2, vcc, 48, v2431; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc432; GFX8-NEXT: flat_load_ushort v2, v[2:3]433; GFX8-NEXT: flat_load_ushort v0, v[0:1]434; GFX8-NEXT: s_waitcnt vmcnt(0)435; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v0436; GFX8-NEXT: v_sub_u16_e32 v2, 0, v2437; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0438; GFX8-NEXT: v_or_b32_e32 v2, v1, v0439; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4440; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc441; GFX8-NEXT: flat_store_short v[0:1], v2442; GFX8-NEXT: s_waitcnt vmcnt(0)443; GFX8-NEXT: s_setpc_b64 s[30:31]444;445; GFX10-LABEL: test_rotr_i16:446; GFX10: ; %bb.0: ; %entry447; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)448; GFX10-NEXT: global_load_ushort v6, v[2:3], off offset:48449; GFX10-NEXT: global_load_ushort v7, v[0:1], off offset:32450; GFX10-NEXT: s_waitcnt vmcnt(1)451; GFX10-NEXT: v_sub_nc_u16 v0, 0, v6452; GFX10-NEXT: s_waitcnt vmcnt(0)453; GFX10-NEXT: v_lshrrev_b16 v1, v6, v7454; GFX10-NEXT: v_lshlrev_b16 v0, v0, v7455; GFX10-NEXT: v_or_b32_e32 v0, v1, v0456; GFX10-NEXT: global_store_short v[4:5], v0, off offset:8457; GFX10-NEXT: s_setpc_b64 s[30:31]458;459; GFX11-TRUE16-LABEL: test_rotr_i16:460; GFX11-TRUE16: ; %bb.0: ; %entry461; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)462; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v[2:3], off offset:48463; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off offset:32464; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)465; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.h, 0, v2.l466; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v2.l, v0.l467; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)468; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l469; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l470; GFX11-TRUE16-NEXT: global_store_b16 v[4:5], v0, off offset:8471; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]472;473; GFX11-FAKE16-LABEL: test_rotr_i16:474; GFX11-FAKE16: ; %bb.0: ; %entry475; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)476; GFX11-FAKE16-NEXT: global_load_u16 v2, v[2:3], off offset:48477; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off offset:32478; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)479; GFX11-FAKE16-NEXT: v_sub_nc_u16 v1, 0, v2480; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)481; GFX11-FAKE16-NEXT: v_lshrrev_b16 v2, v2, v0482; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)483; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v1, v0484; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0485; GFX11-FAKE16-NEXT: global_store_b16 v[4:5], v0, off offset:8486; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]487entry:488 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16489 %a = load i16, ptr addrspace(1) %arrayidx490 %arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %sourceB, i64 24491 %b = load i16, ptr addrspace(1) %arrayidx2492 %c = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)493 %arrayidx5 = getelementptr inbounds i16, ptr addrspace(1) %destValues, i64 4494 store i16 %c, ptr addrspace(1) %arrayidx5495 ret void496}497