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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32 3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-SAFE,SI-DAZ-SAFE %s4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-SAFE,SI-IEEE-SAFE %s5 6; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-SAFE,CI-DAZ-SAFE %s7; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-SAFE,CI-IEEE-SAFE %s8 9 10declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone11declare float @llvm.sqrt.f32(float) nounwind readnone12declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) nounwind readnone13 14define amdgpu_kernel void @rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {15; GCN-DAZ-SAFE-LABEL: rsq_f32:16; GCN-DAZ-SAFE: ; %bb.0:17; GCN-DAZ-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x918; GCN-DAZ-SAFE-NEXT: s_mov_b32 s7, 0xf00019; GCN-DAZ-SAFE-NEXT: s_mov_b32 s6, -120; GCN-DAZ-SAFE-NEXT: s_mov_b32 s10, s621; GCN-DAZ-SAFE-NEXT: s_mov_b32 s11, s722; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)23; GCN-DAZ-SAFE-NEXT: s_mov_b32 s8, s224; GCN-DAZ-SAFE-NEXT: s_mov_b32 s9, s325; GCN-DAZ-SAFE-NEXT: buffer_load_dword v0, off, s[8:11], 026; GCN-DAZ-SAFE-NEXT: s_mov_b32 s2, 0xf80000027; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, 0x26028; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, s029; GCN-DAZ-SAFE-NEXT: s_mov_b32 s5, s130; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)31; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v032; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s2, v033; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc34; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v1, v035; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v0, v136; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0.5, v137; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v1, v3, 0.538; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v339; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v1, v4, v140; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v3, v3, v041; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v4, v1, v342; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v143; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc44; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v245; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc46; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v0, v047; GCN-DAZ-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 048; GCN-DAZ-SAFE-NEXT: s_endpgm49;50; SI-IEEE-SAFE-LABEL: rsq_f32:51; SI-IEEE-SAFE: ; %bb.0:52; SI-IEEE-SAFE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x953; SI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf00054; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, -155; SI-IEEE-SAFE-NEXT: s_mov_b32 s2, s656; SI-IEEE-SAFE-NEXT: s_mov_b32 s3, s757; SI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)58; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, s1059; SI-IEEE-SAFE-NEXT: s_mov_b32 s1, s1160; SI-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[0:3], 061; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0xf80000062; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x26063; SI-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x7f80000064; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, s865; SI-IEEE-SAFE-NEXT: s_mov_b32 s5, s966; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)67; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v068; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v069; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]70; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v071; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, -1, v272; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v4, vcc, 1, v273; SI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v3, v2, v074; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v4, v2, v075; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v576; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc77; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v678; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc79; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v280; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]81; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v182; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc83; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v084; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s285; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc86; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v187; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v088; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v089; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v090; SI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 091; SI-IEEE-SAFE-NEXT: s_endpgm92;93; CI-IEEE-SAFE-LABEL: rsq_f32:94; CI-IEEE-SAFE: ; %bb.0:95; CI-IEEE-SAFE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x996; CI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf00097; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, -198; CI-IEEE-SAFE-NEXT: s_mov_b32 s2, s699; CI-IEEE-SAFE-NEXT: s_mov_b32 s3, s7100; CI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)101; CI-IEEE-SAFE-NEXT: s_mov_b32 s0, s10102; CI-IEEE-SAFE-NEXT: s_mov_b32 s1, s11103; CI-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[0:3], 0104; CI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0xf800000105; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x260106; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, s8107; CI-IEEE-SAFE-NEXT: s_mov_b32 s5, s9108; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)109; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0110; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v0111; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]112; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0113; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, -1, v2114; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v4, vcc, 1, v2115; CI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v3, v2, v0116; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v4, v2, v0117; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v5118; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc119; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v6120; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc121; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2122; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]123; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v1124; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc125; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0126; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1127; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0128; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0129; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0130; CI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0131; CI-IEEE-SAFE-NEXT: s_endpgm132 %val = load float, ptr addrspace(1) %in, align 4133 %sqrt = call contract float @llvm.sqrt.f32(float %val) nounwind readnone134 %div = fdiv contract float 1.0, %sqrt, !fpmath !0135 store float %div, ptr addrspace(1) %out, align 4136 ret void137}138 139define amdgpu_kernel void @rsq_f32_sgpr(ptr addrspace(1) noalias %out, float %val) {140; GCN-DAZ-SAFE-LABEL: rsq_f32_sgpr:141; GCN-DAZ-SAFE: ; %bb.0:142; GCN-DAZ-SAFE-NEXT: s_load_dword s0, s[4:5], 0xb143; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v0, 0xf800000144; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v1, 0x4f800000145; GCN-DAZ-SAFE-NEXT: s_mov_b32 s3, 0xf000146; GCN-DAZ-SAFE-NEXT: s_mov_b32 s2, -1147; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)148; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, s0, v1149; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, s0150; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0151; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc152; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v1, v0153; GCN-DAZ-SAFE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9154; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v0, v1155; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0.5, v1156; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, -v1, v2, 0.5157; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v3, v2158; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v1, v3, v1159; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, -v2, v2, v0160; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v3, v1, v2161; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1162; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc163; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, 0x260164; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2165; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc166; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v0, v0167; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)168; GCN-DAZ-SAFE-NEXT: buffer_store_dword v0, off, s[0:3], 0169; GCN-DAZ-SAFE-NEXT: s_endpgm170;171; SI-IEEE-SAFE-LABEL: rsq_f32_sgpr:172; SI-IEEE-SAFE: ; %bb.0:173; SI-IEEE-SAFE-NEXT: s_load_dword s0, s[4:5], 0xb174; SI-IEEE-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9175; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v0, 0xf800000176; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x4f800000177; SI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000178; SI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)179; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, s0, v1180; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, s0181; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0182; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]183; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0184; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, -1185; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v2, vcc, -1, v1186; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0187; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v3188; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc189; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, 1, v1190; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0191; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1192; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc193; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1194; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]195; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260196; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2197; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc198; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0x7f800000199; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0200; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s0201; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc202; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1203; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0204; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0205; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0206; SI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0207; SI-IEEE-SAFE-NEXT: s_endpgm208;209; CI-IEEE-SAFE-LABEL: rsq_f32_sgpr:210; CI-IEEE-SAFE: ; %bb.0:211; CI-IEEE-SAFE-NEXT: s_load_dword s0, s[4:5], 0xb212; CI-IEEE-SAFE-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9213; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v0, 0xf800000214; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x4f800000215; CI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000216; CI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)217; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, s0, v1218; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, s0219; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0220; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1]221; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0222; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, -1223; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v2, vcc, -1, v1224; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0225; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v3226; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc227; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, 1, v1228; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0229; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v1230; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc231; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1232; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]233; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260234; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2235; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc236; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0237; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1238; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0239; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0240; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0241; CI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0242; CI-IEEE-SAFE-NEXT: s_endpgm243 %sqrt = call contract float @llvm.sqrt.f32(float %val) nounwind readnone244 %div = fdiv contract float 1.0, %sqrt, !fpmath !0245 store float %div, ptr addrspace(1) %out, align 4246 ret void247}248 249; Recognize that this is rsqrt(a) * rcp(b) * c,250; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.251 252; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare.253define amdgpu_kernel void @rsqrt_fmul(ptr addrspace(1) %out, ptr addrspace(1) %in) {254; GCN-DAZ-SAFE-LABEL: rsqrt_fmul:255; GCN-DAZ-SAFE: ; %bb.0:256; GCN-DAZ-SAFE-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9257; GCN-DAZ-SAFE-NEXT: s_mov_b32 s3, 0xf000258; GCN-DAZ-SAFE-NEXT: s_mov_b32 s2, 0259; GCN-DAZ-SAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0260; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v1, 0261; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)262; GCN-DAZ-SAFE-NEXT: s_mov_b64 s[8:9], s[6:7]263; GCN-DAZ-SAFE-NEXT: s_mov_b64 s[10:11], s[2:3]264; GCN-DAZ-SAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc265; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)266; GCN-DAZ-SAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc267; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)268; GCN-DAZ-SAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc269; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)270; GCN-DAZ-SAFE-NEXT: s_mov_b32 s0, 0xf800000271; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v6, 0x260272; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x4f800000, v2273; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2274; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc275; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v5, v2276; GCN-DAZ-SAFE-NEXT: s_mov_b64 s[0:1], s[4:5]277; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v7, v2, v5278; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0.5, v5279; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v5, v7, 0.5280; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, v7, v8, v7281; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v8, v5282; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v7, v7, v2283; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v8, v5, v7284; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v7, 0x37800000, v5285; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc286; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v2, v6287; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc288; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v2, v3289; GCN-DAZ-SAFE-NEXT: v_div_scale_f32 v3, s[4:5], v2, v2, v4290; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v5, v3291; GCN-DAZ-SAFE-NEXT: v_div_scale_f32 v6, vcc, v4, v2, v4292; GCN-DAZ-SAFE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3293; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v3, v5, 1.0294; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v7, v5, v5295; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v7, v6, v5296; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v3, v7, v6297; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, v8, v5, v7298; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, -v3, v7, v6299; GCN-DAZ-SAFE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0300; GCN-DAZ-SAFE-NEXT: v_div_fmas_f32 v3, v3, v5, v7301; GCN-DAZ-SAFE-NEXT: v_div_fixup_f32 v2, v3, v2, v4302; GCN-DAZ-SAFE-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64303; GCN-DAZ-SAFE-NEXT: s_endpgm304;305; GCN-IEEE-SAFE-LABEL: rsqrt_fmul:306; GCN-IEEE-SAFE: ; %bb.0:307; GCN-IEEE-SAFE-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9308; GCN-IEEE-SAFE-NEXT: s_mov_b32 s3, 0xf000309; GCN-IEEE-SAFE-NEXT: s_mov_b32 s2, 0310; GCN-IEEE-SAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0311; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0312; GCN-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)313; GCN-IEEE-SAFE-NEXT: s_mov_b64 s[8:9], s[6:7]314; GCN-IEEE-SAFE-NEXT: s_mov_b64 s[10:11], s[2:3]315; GCN-IEEE-SAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc316; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)317; GCN-IEEE-SAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc318; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)319; GCN-IEEE-SAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc320; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)321; GCN-IEEE-SAFE-NEXT: s_mov_b32 s0, 0xf800000322; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v6, 0x260323; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x4f800000, v2324; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s0, v2325; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc326; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v5, v2327; GCN-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[0:1], -1, v5328; GCN-IEEE-SAFE-NEXT: v_add_i32_e64 v8, s[0:1], 1, v5329; GCN-IEEE-SAFE-NEXT: v_fma_f32 v9, -v7, v5, v2330; GCN-IEEE-SAFE-NEXT: v_fma_f32 v10, -v8, v5, v2331; GCN-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[0:1], 0, v9332; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[0:1]333; GCN-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], 0, v10334; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[0:1]335; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v7, 0x37800000, v5336; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc337; GCN-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v2, v6338; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc339; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, v2, v3340; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v3, s[0:1], v2, v2, v4341; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v5, v3342; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v6, vcc, v4, v2, v4343; GCN-IEEE-SAFE-NEXT: s_mov_b64 s[0:1], s[4:5]344; GCN-IEEE-SAFE-NEXT: v_fma_f32 v7, -v3, v5, 1.0345; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, v7, v5, v5346; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v7, v6, v5347; GCN-IEEE-SAFE-NEXT: v_fma_f32 v8, -v3, v7, v6348; GCN-IEEE-SAFE-NEXT: v_fma_f32 v7, v8, v5, v7349; GCN-IEEE-SAFE-NEXT: v_fma_f32 v3, -v3, v7, v6350; GCN-IEEE-SAFE-NEXT: v_div_fmas_f32 v3, v3, v5, v7351; GCN-IEEE-SAFE-NEXT: v_div_fixup_f32 v2, v3, v2, v4352; GCN-IEEE-SAFE-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64353; GCN-IEEE-SAFE-NEXT: s_endpgm354 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone355 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid356 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid357 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1358 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2359 360 %a = load volatile float, ptr addrspace(1) %gep.0361 %b = load volatile float, ptr addrspace(1) %gep.1362 %c = load volatile float, ptr addrspace(1) %gep.2363 364 %x = call contract float @llvm.sqrt.f32(float %a)365 %y = fmul contract float %x, %b366 %z = fdiv contract float %c, %y367 store float %z, ptr addrspace(1) %out.gep368 ret void369}370 371define amdgpu_kernel void @neg_rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {372; GCN-DAZ-SAFE-LABEL: neg_rsq_f32:373; GCN-DAZ-SAFE: ; %bb.0:374; GCN-DAZ-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9375; GCN-DAZ-SAFE-NEXT: s_mov_b32 s7, 0xf000376; GCN-DAZ-SAFE-NEXT: s_mov_b32 s6, -1377; GCN-DAZ-SAFE-NEXT: s_mov_b32 s10, s6378; GCN-DAZ-SAFE-NEXT: s_mov_b32 s11, s7379; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)380; GCN-DAZ-SAFE-NEXT: s_mov_b32 s8, s2381; GCN-DAZ-SAFE-NEXT: s_mov_b32 s9, s3382; GCN-DAZ-SAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0383; GCN-DAZ-SAFE-NEXT: s_mov_b32 s2, 0xf800000384; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, 0x260385; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, s0386; GCN-DAZ-SAFE-NEXT: s_mov_b32 s5, s1387; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)388; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0389; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s2, v0390; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc391; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v1, v0392; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v0, v1393; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0.5, v1394; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v1, v3, 0.5395; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v3396; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v1, v4, v1397; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v3, v3, v0398; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v4, v1, v3399; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v1400; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc401; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2402; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc403; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0404; GCN-DAZ-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0405; GCN-DAZ-SAFE-NEXT: s_endpgm406;407; SI-IEEE-SAFE-LABEL: neg_rsq_f32:408; SI-IEEE-SAFE: ; %bb.0:409; SI-IEEE-SAFE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9410; SI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000411; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, -1412; SI-IEEE-SAFE-NEXT: s_mov_b32 s2, s6413; SI-IEEE-SAFE-NEXT: s_mov_b32 s3, s7414; SI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)415; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, s10416; SI-IEEE-SAFE-NEXT: s_mov_b32 s1, s11417; SI-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[0:3], 0418; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0xf800000419; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x260420; SI-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x7f800000421; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, s8422; SI-IEEE-SAFE-NEXT: s_mov_b32 s5, s9423; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)424; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0425; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v0426; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]427; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0428; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, -1, v2429; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v4, vcc, 1, v2430; SI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v3, v2, v0431; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v4, v2, v0432; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v5433; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc434; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v6435; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc436; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2437; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]438; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v1439; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc440; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v0441; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, s2442; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v0, v1, s[0:1]443; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1444; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0445; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0446; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0447; SI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0448; SI-IEEE-SAFE-NEXT: s_endpgm449;450; CI-IEEE-SAFE-LABEL: neg_rsq_f32:451; CI-IEEE-SAFE: ; %bb.0:452; CI-IEEE-SAFE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9453; CI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000454; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, -1455; CI-IEEE-SAFE-NEXT: s_mov_b32 s2, s6456; CI-IEEE-SAFE-NEXT: s_mov_b32 s3, s7457; CI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)458; CI-IEEE-SAFE-NEXT: s_mov_b32 s0, s10459; CI-IEEE-SAFE-NEXT: s_mov_b32 s1, s11460; CI-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[0:3], 0461; CI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0xf800000462; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x260463; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, s8464; CI-IEEE-SAFE-NEXT: s_mov_b32 s5, s9465; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)466; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v0467; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 s[0:1], s0, v0468; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]469; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0470; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, -1, v2471; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v4, vcc, 1, v2472; CI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v3, v2, v0473; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v4, v2, v0474; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v5475; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc476; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v6477; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc478; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2479; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]480; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v1481; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc482; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v0483; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1484; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0485; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0486; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0487; CI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0488; CI-IEEE-SAFE-NEXT: s_endpgm489 %val = load float, ptr addrspace(1) %in, align 4490 %sqrt = call contract float @llvm.sqrt.f32(float %val)491 %div = fdiv contract float -1.0, %sqrt, !fpmath !0492 store float %div, ptr addrspace(1) %out, align 4493 ret void494}495 496define amdgpu_kernel void @neg_rsq_neg_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {497; GCN-DAZ-SAFE-LABEL: neg_rsq_neg_f32:498; GCN-DAZ-SAFE: ; %bb.0:499; GCN-DAZ-SAFE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9500; GCN-DAZ-SAFE-NEXT: s_mov_b32 s7, 0xf000501; GCN-DAZ-SAFE-NEXT: s_mov_b32 s6, -1502; GCN-DAZ-SAFE-NEXT: s_mov_b32 s10, s6503; GCN-DAZ-SAFE-NEXT: s_mov_b32 s11, s7504; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)505; GCN-DAZ-SAFE-NEXT: s_mov_b32 s8, s2506; GCN-DAZ-SAFE-NEXT: s_mov_b32 s9, s3507; GCN-DAZ-SAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0508; GCN-DAZ-SAFE-NEXT: s_mov_b32 s2, 0x8f800000509; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, 0x260510; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, s0511; GCN-DAZ-SAFE-NEXT: s_mov_b32 s5, s1512; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)513; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0xcf800000, v0514; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0515; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc516; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v1, v0517; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v0, v1518; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0.5, v1519; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v1, v3, 0.5520; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v3521; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v1, v4, v1522; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v3, v3, v0523; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v4, v1, v3524; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v1525; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc526; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2527; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc528; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0529; GCN-DAZ-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0530; GCN-DAZ-SAFE-NEXT: s_endpgm531;532; SI-IEEE-SAFE-LABEL: neg_rsq_neg_f32:533; SI-IEEE-SAFE: ; %bb.0:534; SI-IEEE-SAFE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9535; SI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000536; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, -1537; SI-IEEE-SAFE-NEXT: s_mov_b32 s2, s6538; SI-IEEE-SAFE-NEXT: s_mov_b32 s3, s7539; SI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)540; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, s10541; SI-IEEE-SAFE-NEXT: s_mov_b32 s1, s11542; SI-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[0:3], 0543; SI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0x8f800000544; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x260545; SI-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x7f800000546; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, s8547; SI-IEEE-SAFE-NEXT: s_mov_b32 s5, s9548; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)549; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0xcf800000, v0550; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0551; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v2, s[0:1]552; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0553; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, -1, v2554; SI-IEEE-SAFE-NEXT: v_add_i32_e32 v4, vcc, 1, v2555; SI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v3, v2, v0556; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v4, v2, v0557; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v5558; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc559; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v6560; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc561; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2562; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]563; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v1564; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc565; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v0566; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, s2567; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v0, v1, s[0:1]568; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1569; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0570; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0571; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0572; SI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0573; SI-IEEE-SAFE-NEXT: s_endpgm574;575; CI-IEEE-SAFE-LABEL: neg_rsq_neg_f32:576; CI-IEEE-SAFE: ; %bb.0:577; CI-IEEE-SAFE-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9578; CI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000579; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, -1580; CI-IEEE-SAFE-NEXT: s_mov_b32 s2, s6581; CI-IEEE-SAFE-NEXT: s_mov_b32 s3, s7582; CI-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)583; CI-IEEE-SAFE-NEXT: s_mov_b32 s0, s10584; CI-IEEE-SAFE-NEXT: s_mov_b32 s1, s11585; CI-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[0:3], 0586; CI-IEEE-SAFE-NEXT: s_mov_b32 s0, 0x8f800000587; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x260588; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, s8589; CI-IEEE-SAFE-NEXT: s_mov_b32 s5, s9590; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)591; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0xcf800000, v0592; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, v0593; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v2, s[0:1]594; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0595; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v3, vcc, -1, v2596; CI-IEEE-SAFE-NEXT: v_add_i32_e32 v4, vcc, 1, v2597; CI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v3, v2, v0598; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v4, v2, v0599; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e32 vcc, 0, v5600; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc601; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, 0, v6602; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc603; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2604; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]605; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v1606; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc607; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v0608; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1609; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0610; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0611; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0612; CI-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0613; CI-IEEE-SAFE-NEXT: s_endpgm614 %val = load float, ptr addrspace(1) %in, align 4615 %val.fneg = fneg float %val616 %sqrt = call contract float @llvm.sqrt.f32(float %val.fneg)617 %div = fdiv contract float -1.0, %sqrt, !fpmath !0618 store float %div, ptr addrspace(1) %out, align 4619 ret void620}621 622define float @v_neg_rsq_neg_f32(float %val) {623; GCN-DAZ-SAFE-LABEL: v_neg_rsq_neg_f32:624; GCN-DAZ-SAFE: ; %bb.0:625; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)626; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0x8f800000627; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0xcf800000, v0628; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0629; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc630; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v1, v0631; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v0, v1632; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0.5, v1633; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, -v1, v2, 0.5634; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v3, v2635; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v2, v2, v0636; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v1, v3, v1637; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v4, v1, v2638; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1639; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc640; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, 0x260641; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2642; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc643; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0644; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]645;646; SI-IEEE-SAFE-LABEL: v_neg_rsq_neg_f32:647; SI-IEEE-SAFE: ; %bb.0:648; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)649; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8f800000650; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0xcf800000, v0651; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0652; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc653; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0654; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1655; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0656; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3657; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]658; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1659; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0660; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1661; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]662; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1663; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc664; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260665; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2666; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc667; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f800000668; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v0669; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4670; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v0, v1, s[4:5]671; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1672; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0673; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0674; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0675; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]676;677; CI-IEEE-SAFE-LABEL: v_neg_rsq_neg_f32:678; CI-IEEE-SAFE: ; %bb.0:679; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)680; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8f800000681; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0xcf800000, v0682; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0683; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v1, vcc684; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0685; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1686; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0687; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3688; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]689; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1690; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0691; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1692; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]693; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1694; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc695; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260696; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2697; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc698; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v0699; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1700; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0701; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0702; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0703; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]704 %val.fneg = fneg float %val705 %sqrt = call contract float @llvm.sqrt.f32(float %val.fneg)706 %div = fdiv contract float -1.0, %sqrt, !fpmath !0707 ret float %div708}709 710define <2 x float> @v_neg_rsq_neg_v2f32(<2 x float> %val) {711; GCN-DAZ-SAFE-LABEL: v_neg_rsq_neg_v2f32:712; GCN-DAZ-SAFE: ; %bb.0:713; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)714; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0x8f800000715; GCN-DAZ-SAFE-NEXT: s_mov_b32 s5, 0x4f800000716; GCN-DAZ-SAFE-NEXT: v_mul_f32_e64 v2, -v1, s5717; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1718; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, -v1, v2, vcc719; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v2, v1720; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v1, v2721; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0.5, v2722; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v2, v3, 0.5723; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v3724; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, -v3, v3, v1725; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v4, v2726; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v5, v2, v3727; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2728; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc729; GCN-DAZ-SAFE-NEXT: v_mul_f32_e64 v3, -v0, s5730; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0731; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v3, vcc732; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v3, v0733; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v4, 0x260734; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v4735; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]736; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v0, v3737; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0.5, v3738; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, -v3, v2, 0.5739; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v5, v2740; GCN-DAZ-SAFE-NEXT: v_fma_f32 v6, -v2, v2, v0741; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v5, v3742; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v6, v3, v2743; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2744; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc745; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v4746; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc747; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0748; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v1, -v1749; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]750;751; SI-IEEE-SAFE-LABEL: v_neg_rsq_neg_v2f32:752; SI-IEEE-SAFE: ; %bb.0:753; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)754; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x8f800000755; SI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0x4f800000756; SI-IEEE-SAFE-NEXT: v_mul_f32_e64 v2, -v1, s7757; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1758; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v1, v2, vcc759; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v1760; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v2761; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v1762; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v4763; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]764; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v2765; SI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v1766; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v2767; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]768; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2769; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc770; SI-IEEE-SAFE-NEXT: v_mul_f32_e64 v4, -v0, s7771; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0772; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v4, vcc773; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v0774; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x260775; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v3776; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]777; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v4778; SI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v4, v0779; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v5780; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]781; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], 1, v4782; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v5, v4, v0783; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v4784; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]785; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x37800000, v2786; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc787; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3788; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc789; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x7f800000790; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v0791; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6792; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, -v0, v2, s[4:5]793; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v2794; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0795; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0796; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v0797; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v1798; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6799; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, -v1, v2, s[4:5]800; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v2801; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1802; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v1803; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v2, v1804; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]805;806; CI-IEEE-SAFE-LABEL: v_neg_rsq_neg_v2f32:807; CI-IEEE-SAFE: ; %bb.0:808; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)809; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x8f800000810; CI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0x4f800000811; CI-IEEE-SAFE-NEXT: v_mul_f32_e64 v2, -v1, s7812; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v1813; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v1, v2, vcc814; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v1815; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v2816; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v1817; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v4818; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]819; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v2820; CI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v1821; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v2822; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]823; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2824; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc825; CI-IEEE-SAFE-NEXT: v_mul_f32_e64 v4, -v0, s7826; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0827; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v4, vcc828; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v0829; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x260830; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v3831; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]832; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v4833; CI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v4, v0834; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v5835; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]836; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], 1, v4837; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v5, v4, v0838; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v4839; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]840; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x37800000, v2841; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc842; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3843; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc844; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v0845; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v2846; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0847; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0848; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v0849; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v1850; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v2851; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1852; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v1853; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v2, v1854; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]855 %val.fneg = fneg <2 x float> %val856 %sqrt = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val.fneg)857 %div = fdiv contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0858 ret <2 x float> %div859}860 861define float @v_neg_rsq_neg_f32_foldable_user(float %val0, float %val1) {862; GCN-DAZ-SAFE-LABEL: v_neg_rsq_neg_f32_foldable_user:863; GCN-DAZ-SAFE: ; %bb.0:864; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)865; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0x8f800000866; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0xcf800000, v0867; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0868; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc869; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v2, v0870; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v0, v2871; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0.5, v2872; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v2, v3, 0.5873; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v3874; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, -v3, v3, v0875; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v4, v2876; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v5, v2, v3877; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2878; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc879; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v3, 0x260880; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3881; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc882; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0883; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1884; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]885;886; SI-IEEE-SAFE-LABEL: v_neg_rsq_neg_f32_foldable_user:887; SI-IEEE-SAFE: ; %bb.0:888; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)889; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8f800000890; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0xcf800000, v0891; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0892; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc893; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0894; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v2895; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v0896; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v4897; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]898; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v2899; SI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v0900; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v2901; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]902; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2903; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc904; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x260905; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3906; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc907; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f800000908; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v0909; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4910; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, -v0, v2, s[4:5]911; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v2912; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0913; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0914; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v0915; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1916; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]917;918; CI-IEEE-SAFE-LABEL: v_neg_rsq_neg_f32_foldable_user:919; CI-IEEE-SAFE: ; %bb.0:920; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)921; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8f800000922; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0xcf800000, v0923; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0924; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v2, vcc925; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v0926; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v2927; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v0928; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v4929; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]930; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v2931; CI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v0932; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v2933; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]934; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v2935; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc936; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x260937; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v3938; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc939; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v0940; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v2941; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0942; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0943; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v0944; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1945; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]946 %val0.neg = fneg float %val0947 %sqrt = call contract float @llvm.sqrt.f32(float %val0.neg)948 %div = fdiv contract float -1.0, %sqrt, !fpmath !0949 %user = fmul contract float %div, %val1950 ret float %user951}952 953define <2 x float> @v_neg_rsq_neg_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {954; GCN-DAZ-SAFE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:955; GCN-DAZ-SAFE: ; %bb.0:956; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)957; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0x8f800000958; GCN-DAZ-SAFE-NEXT: s_mov_b32 s5, 0x4f800000959; GCN-DAZ-SAFE-NEXT: v_mul_f32_e64 v4, -v1, s5960; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1961; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, -v1, v4, vcc962; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v4, v1963; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, v1, v4964; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, 0.5, v4965; GCN-DAZ-SAFE-NEXT: v_fma_f32 v6, -v4, v5, 0.5966; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v6, v5967; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v5, v5, v1968; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v4, v6, v4969; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v7, v4, v5970; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v4971; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc972; GCN-DAZ-SAFE-NEXT: v_mul_f32_e64 v5, -v0, s5973; GCN-DAZ-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0974; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v5, vcc975; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v5, v0976; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v6, 0x260977; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v6978; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]979; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, v0, v5980; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0.5, v5981; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v5, v4, 0.5982; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v4, v7, v4983; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v4, v4, v0984; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v7, v5985; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v8, v5, v4986; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v4987; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc988; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v6989; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc990; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0991; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v1, -v1992; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2993; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3994; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]995;996; SI-IEEE-SAFE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:997; SI-IEEE-SAFE: ; %bb.0:998; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)999; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x8f8000001000; SI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0x4f8000001001; SI-IEEE-SAFE-NEXT: v_mul_f32_e64 v4, -v1, s71002; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v11003; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v1, v4, vcc1004; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v11005; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], -1, v41006; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v5, v4, v11007; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v61008; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[4:5]1009; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v6, s[4:5], 1, v41010; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v6, v4, v11011; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v41012; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v5, v6, s[4:5]1013; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v41014; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1015; SI-IEEE-SAFE-NEXT: v_mul_f32_e64 v6, -v0, s71016; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v01017; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v6, vcc1018; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v6, v01019; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v5, 0x2601020; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v51021; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1022; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], -1, v61023; SI-IEEE-SAFE-NEXT: v_fma_f32 v7, -v4, v6, v01024; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v71025; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]1026; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[4:5], 1, v61027; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v7, v6, v01028; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v61029; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]1030; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x37800000, v41031; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc1032; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v51033; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1034; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x7f8000001035; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v01036; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s61037; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, -v0, v4, s[4:5]1038; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41039; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01040; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01041; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v4, v01042; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v11043; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s61044; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, -v1, v4, s[4:5]1045; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41046; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11047; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11048; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v4, v11049; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v21050; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v31051; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1052;1053; CI-IEEE-SAFE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:1054; CI-IEEE-SAFE: ; %bb.0:1055; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1056; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x8f8000001057; CI-IEEE-SAFE-NEXT: s_mov_b32 s7, 0x4f8000001058; CI-IEEE-SAFE-NEXT: v_mul_f32_e64 v4, -v1, s71059; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v11060; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v1, v4, vcc1061; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v11062; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], -1, v41063; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v5, v4, v11064; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v61065; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[4:5]1066; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v6, s[4:5], 1, v41067; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v6, v4, v11068; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v41069; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v5, v6, s[4:5]1070; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v41071; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1072; CI-IEEE-SAFE-NEXT: v_mul_f32_e64 v6, -v0, s71073; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e32 vcc, s6, v01074; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v0, -v0, v6, vcc1075; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v6, v01076; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v5, 0x2601077; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v51078; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1079; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], -1, v61080; CI-IEEE-SAFE-NEXT: v_fma_f32 v7, -v4, v6, v01081; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v71082; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]1083; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[4:5], 1, v61084; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v7, v6, v01085; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v61086; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]1087; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x37800000, v41088; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc1089; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v51090; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1091; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v01092; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41093; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01094; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01095; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v4, v01096; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v11097; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41098; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11099; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11100; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v4, v11101; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v21102; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v31103; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1104 %val0.fneg = fneg <2 x float> %val01105 %sqrt = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0.fneg)1106 %div = fdiv contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !01107 %user = fmul contract <2 x float> %div, %val11108 ret <2 x float> %user1109}1110 1111define float @v_neg_rsq_f32(float %val) {1112; GCN-DAZ-SAFE-LABEL: v_neg_rsq_f32:1113; GCN-DAZ-SAFE: ; %bb.0:1114; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1115; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0xf8000001116; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01117; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01118; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1119; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v1, v01120; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v0, v11121; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, 0.5, v11122; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, -v1, v2, 0.51123; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v3, v21124; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v2, v2, v01125; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v1, v3, v11126; GCN-DAZ-SAFE-NEXT: v_fma_f32 v1, v4, v1, v21127; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11128; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1129; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601130; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21131; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1132; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v01133; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1134;1135; SI-IEEE-SAFE-LABEL: v_neg_rsq_f32:1136; SI-IEEE-SAFE: ; %bb.0:1137; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1138; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001139; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01140; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01141; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1142; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01143; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11144; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01145; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31146; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1147; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11148; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01149; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11150; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1151; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11152; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1153; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601154; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21155; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1156; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f8000001157; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v01158; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s41159; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, -v0, v1, s[4:5]1160; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11161; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01162; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01163; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v01164; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1165;1166; CI-IEEE-SAFE-LABEL: v_neg_rsq_f32:1167; CI-IEEE-SAFE: ; %bb.0:1168; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1169; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001170; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01171; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01172; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1173; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01174; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11175; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01176; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31177; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1178; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11179; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01180; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11181; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1182; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11183; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1184; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601185; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21186; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1187; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v1, -v01188; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11189; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01190; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01191; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v01192; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1193 %sqrt = call contract float @llvm.sqrt.f32(float %val)1194 %div = fdiv contract float -1.0, %sqrt, !fpmath !01195 ret float %div1196}1197 1198define <2 x float> @v_neg_rsq_v2f32(<2 x float> %val) {1199; GCN-DAZ-SAFE-LABEL: v_neg_rsq_v2f32:1200; GCN-DAZ-SAFE: ; %bb.0:1201; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1202; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0xf8000001203; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v11204; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v11205; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1206; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v2, v11207; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v1, v21208; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0.5, v21209; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v2, v3, 0.51210; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v31211; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, -v3, v3, v11212; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v4, v21213; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v5, v2, v31214; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21215; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1216; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x4f800000, v01217; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01218; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc1219; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v3, v01220; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v4, 0x2601221; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v41222; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]1223; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v0, v31224; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0.5, v31225; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, -v3, v2, 0.51226; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v5, v21227; GCN-DAZ-SAFE-NEXT: v_fma_f32 v6, -v2, v2, v01228; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v5, v31229; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v6, v3, v21230; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21231; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1232; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v41233; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1234; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v01235; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v1, -v11236; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1237;1238; SI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32:1239; SI-IEEE-SAFE: ; %bb.0:1240; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1241; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0xf8000001242; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v11243; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v11244; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1245; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v11246; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v21247; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v11248; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v41249; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]1250; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v21251; SI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v11252; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v21253; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]1254; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21255; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1256; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v01257; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v01258; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc1259; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v01260; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x2601261; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v31262; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]1263; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v41264; SI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v4, v01265; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v51266; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]1267; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], 1, v41268; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v5, v4, v01269; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v41270; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]1271; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x37800000, v21272; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc1273; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v31274; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1275; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x7f8000001276; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v01277; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s61278; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, -v0, v2, s[4:5]1279; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v21280; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01281; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01282; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v01283; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v11284; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s61285; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, -v1, v2, s[4:5]1286; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v21287; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11288; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11289; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v2, v11290; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1291;1292; CI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32:1293; CI-IEEE-SAFE: ; %bb.0:1294; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1295; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0xf8000001296; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v11297; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v11298; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1299; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v11300; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v21301; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v11302; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v41303; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]1304; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v21305; CI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v11306; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v21307; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]1308; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21309; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1310; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v01311; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v01312; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc1313; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v01314; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x2601315; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v31316; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[4:5]1317; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v41318; CI-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v4, v01319; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v51320; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]1321; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], 1, v41322; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v5, v4, v01323; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v41324; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]1325; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x37800000, v21326; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc1327; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v31328; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1329; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v01330; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v21331; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01332; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01333; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v01334; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v11335; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v21336; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11337; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11338; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v2, v11339; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1340 %sqrt = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val)1341 %div = fdiv contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !01342 ret <2 x float> %div1343}1344 1345define float @v_neg_rsq_f32_foldable_user(float %val0, float %val1) {1346; GCN-DAZ-SAFE-LABEL: v_neg_rsq_f32_foldable_user:1347; GCN-DAZ-SAFE: ; %bb.0:1348; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1349; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0xf8000001350; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01351; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01352; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1353; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v2, v01354; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, v0, v21355; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, 0.5, v21356; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, -v2, v3, 0.51357; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, v3, v4, v31358; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, -v3, v3, v01359; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v2, v4, v21360; GCN-DAZ-SAFE-NEXT: v_fma_f32 v2, v5, v2, v31361; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21362; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1363; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v3, 0x2601364; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v31365; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1366; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v01367; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v0, v0, v11368; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1369;1370; SI-IEEE-SAFE-LABEL: v_neg_rsq_f32_foldable_user:1371; SI-IEEE-SAFE: ; %bb.0:1372; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1373; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001374; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01375; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01376; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1377; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v01378; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v21379; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v01380; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v41381; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]1382; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v21383; SI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v01384; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v21385; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]1386; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21387; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1388; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x2601389; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v31390; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1391; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f8000001392; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v01393; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s41394; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, -v0, v2, s[4:5]1395; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v21396; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01397; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01398; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v01399; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v11400; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1401;1402; CI-IEEE-SAFE-LABEL: v_neg_rsq_f32_foldable_user:1403; CI-IEEE-SAFE: ; %bb.0:1404; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1405; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001406; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x4f800000, v01407; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01408; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1409; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v01410; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], -1, v21411; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v3, v2, v01412; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v41413; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v3, v2, v3, s[4:5]1414; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], 1, v21415; CI-IEEE-SAFE-NEXT: v_fma_f32 v2, -v4, v2, v01416; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v21417; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[4:5]1418; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v3, 0x37800000, v21419; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc1420; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v3, 0x2601421; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v31422; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1423; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v2, -v01424; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v21425; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01426; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01427; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v2, v01428; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v11429; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1430 %sqrt = call contract float @llvm.sqrt.f32(float %val0)1431 %div = fdiv contract float -1.0, %sqrt, !fpmath !01432 %user = fmul contract float %div, %val11433 ret float %user1434}1435 1436define <2 x float> @v_neg_rsq_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {1437; GCN-DAZ-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:1438; GCN-DAZ-SAFE: ; %bb.0:1439; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1440; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0xf8000001441; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v11442; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v11443; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc1444; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v4, v11445; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, v1, v41446; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, 0.5, v41447; GCN-DAZ-SAFE-NEXT: v_fma_f32 v6, -v4, v5, 0.51448; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v6, v51449; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v5, v5, v11450; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v4, v6, v41451; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v7, v4, v51452; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v41453; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1454; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x4f800000, v01455; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01456; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc1457; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v5, v01458; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v6, 0x2601459; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v61460; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1461; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, v0, v51462; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0.5, v51463; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v5, v4, 0.51464; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v4, v7, v41465; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v4, v4, v01466; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v7, v51467; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v8, v5, v41468; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v41469; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1470; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v61471; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1472; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v01473; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v1, -v11474; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v0, v0, v21475; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, v1, v31476; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1477;1478; SI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:1479; SI-IEEE-SAFE: ; %bb.0:1480; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1481; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0xf8000001482; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v11483; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v11484; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc1485; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v11486; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], -1, v41487; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v5, v4, v11488; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v61489; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[4:5]1490; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v6, s[4:5], 1, v41491; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v6, v4, v11492; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v41493; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v5, v6, s[4:5]1494; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v41495; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1496; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x4f800000, v01497; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v01498; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc1499; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v6, v01500; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v5, 0x2601501; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v51502; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1503; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], -1, v61504; SI-IEEE-SAFE-NEXT: v_fma_f32 v7, -v4, v6, v01505; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v71506; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]1507; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[4:5], 1, v61508; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v7, v6, v01509; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v61510; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]1511; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x37800000, v41512; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc1513; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v51514; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1515; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x7f8000001516; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v01517; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s61518; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, -v0, v4, s[4:5]1519; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41520; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01521; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01522; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v4, v01523; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v11524; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s61525; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, -v1, v4, s[4:5]1526; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41527; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11528; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11529; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v4, v11530; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v21531; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v31532; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1533;1534; CI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:1535; CI-IEEE-SAFE: ; %bb.0:1536; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1537; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0xf8000001538; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v11539; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v11540; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc1541; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v11542; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], -1, v41543; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v5, v4, v11544; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v61545; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[4:5]1546; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v6, s[4:5], 1, v41547; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v6, v4, v11548; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v41549; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v5, v6, s[4:5]1550; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v41551; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1552; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x4f800000, v01553; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v01554; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc1555; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v6, v01556; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v5, 0x2601557; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v51558; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]1559; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], -1, v61560; CI-IEEE-SAFE-NEXT: v_fma_f32 v7, -v4, v6, v01561; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v71562; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]1563; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[4:5], 1, v61564; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v7, v6, v01565; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v61566; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]1567; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x37800000, v41568; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc1569; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v51570; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1571; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v01572; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41573; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01574; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01575; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v4, v01576; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v11577; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v41578; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v11579; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v11580; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v4, v11581; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v21582; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v31583; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1584 %sqrt = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0)1585 %div = fdiv contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !01586 %user = fmul contract <2 x float> %div, %val11587 ret <2 x float> %user1588}1589 1590define float @v_rsq_f32(float %val) {1591; GCN-DAZ-LABEL: v_rsq_f32:1592; GCN-DAZ: ; %bb.0:1593; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1594; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v01595; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]1596;1597; GCN-IEEE-SAFE-LABEL: v_rsq_f32:1598; GCN-IEEE-SAFE: ; %bb.0:1599; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1600; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8000001601; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01602; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc1603; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v11604; GCN-IEEE-SAFE-NEXT: v_rsq_f32_e32 v0, v01605; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc1606; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v11607; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1608 %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !11609 %div = fdiv contract float 1.0, %sqrt, !fpmath !11610 ret float %div1611}1612 1613define { float, float } @v_rsq_f32_multi_use(float %val) {1614; GCN-DAZ-SAFE-LABEL: v_rsq_f32_multi_use:1615; GCN-DAZ-SAFE: ; %bb.0:1616; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1617; GCN-DAZ-SAFE-NEXT: v_sqrt_f32_e32 v0, v01618; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v1, v01619; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1620;1621; SI-IEEE-SAFE-LABEL: v_rsq_f32_multi_use:1622; SI-IEEE-SAFE: ; %bb.0:1623; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1624; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001625; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01626; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01627; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1628; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01629; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11630; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01631; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31632; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1633; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11634; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01635; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11636; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1637; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11638; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1639; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601640; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21641; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1642; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f8000001643; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v01644; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s41645; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc1646; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11647; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v2, v01648; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v2, vcc, 0, v21649; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v1, v21650; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1651;1652; CI-IEEE-SAFE-LABEL: v_rsq_f32_multi_use:1653; CI-IEEE-SAFE: ; %bb.0:1654; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1655; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001656; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01657; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01658; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1659; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01660; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11661; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01662; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31663; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1664; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11665; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01666; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11667; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1668; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11669; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1670; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601671; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21672; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1673; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v01674; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11675; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v2, v01676; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v2, vcc, 0, v21677; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v1, v21678; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1679 %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !11680 %insert.0 = insertvalue { float, float } poison, float %sqrt, 01681 %div = fdiv contract float 1.0, %sqrt, !fpmath !11682 %insert.1 = insertvalue { float, float } %insert.0, float %div, 11683 ret { float, float } %insert.11684}1685 1686define float @v_rsq_f32_missing_contract0(float %val) {1687; GCN-DAZ-SAFE-LABEL: v_rsq_f32_missing_contract0:1688; GCN-DAZ-SAFE: ; %bb.0:1689; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1690; GCN-DAZ-SAFE-NEXT: v_sqrt_f32_e32 v0, v01691; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v0, v01692; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1693;1694; SI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract0:1695; SI-IEEE-SAFE: ; %bb.0:1696; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1697; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001698; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01699; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01700; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1701; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01702; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11703; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01704; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31705; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1706; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11707; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01708; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11709; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1710; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11711; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1712; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601713; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21714; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1715; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f8000001716; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v01717; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s41718; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc1719; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11720; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01721; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01722; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v01723; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1724;1725; CI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract0:1726; CI-IEEE-SAFE: ; %bb.0:1727; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1728; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001729; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01730; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01731; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1732; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01733; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11734; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01735; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31736; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1737; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11738; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01739; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11740; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1741; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11742; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1743; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601744; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21745; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1746; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v01747; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11748; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01749; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01750; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v01751; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1752 %sqrt = call float @llvm.sqrt.f32(float %val), !fpmath !11753 %div = fdiv contract float 1.0, %sqrt, !fpmath !11754 ret float %div1755}1756 1757define float @v_rsq_f32_missing_contract1(float %val) {1758; GCN-DAZ-SAFE-LABEL: v_rsq_f32_missing_contract1:1759; GCN-DAZ-SAFE: ; %bb.0:1760; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1761; GCN-DAZ-SAFE-NEXT: v_sqrt_f32_e32 v0, v01762; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v0, v01763; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]1764;1765; SI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract1:1766; SI-IEEE-SAFE: ; %bb.0:1767; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1768; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001769; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01770; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01771; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1772; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01773; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11774; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01775; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31776; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1777; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11778; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01779; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11780; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1781; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11782; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1783; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601784; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21785; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1786; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f8000001787; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v01788; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s41789; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc1790; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11791; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01792; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01793; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v01794; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1795;1796; CI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract1:1797; CI-IEEE-SAFE: ; %bb.0:1798; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1799; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf8000001800; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v01801; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01802; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1803; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v01804; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v11805; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v01806; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v31807; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]1808; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v11809; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v01810; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v11811; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]1812; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v11813; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc1814; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2601815; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v21816; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc1817; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v01818; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v11819; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v01820; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v01821; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v01822; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1823 %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !11824 %div = fdiv float 1.0, %sqrt, !fpmath !11825 ret float %div1826}1827 1828; Test that we contract into FMA for an fadd user after introducing1829; the fmul.1830define float @v_rsq_f32_contractable_user(float %val0, float %val1) {1831; GCN-DAZ-LABEL: v_rsq_f32_contractable_user:1832; GCN-DAZ: ; %bb.0:1833; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1834; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v01835; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v11836; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]1837;1838; GCN-IEEE-SAFE-LABEL: v_rsq_f32_contractable_user:1839; GCN-IEEE-SAFE: ; %bb.0:1840; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1841; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8000001842; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01843; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 24, vcc1844; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v21845; GCN-IEEE-SAFE-NEXT: v_rsq_f32_e32 v0, v01846; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x458000001847; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc1848; GCN-IEEE-SAFE-NEXT: v_fma_f32 v0, v0, v2, v11849; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1850 %sqrt = call contract float @llvm.sqrt.f32(float %val0), !fpmath !11851 %div = fdiv contract float 1.0, %sqrt, !fpmath !11852 %add = fadd contract float %div, %val11853 ret float %add1854}1855 1856; Missing contract on the fdiv1857define float @v_rsq_f32_contractable_user_missing_contract0(float %val0, float %val1) {1858; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract0:1859; GCN-DAZ: ; %bb.0:1860; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1861; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v01862; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v11863; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]1864;1865; GCN-IEEE-SAFE-LABEL: v_rsq_f32_contractable_user_missing_contract0:1866; GCN-IEEE-SAFE: ; %bb.0:1867; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1868; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8000001869; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01870; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 24, vcc1871; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v21872; GCN-IEEE-SAFE-NEXT: v_rsq_f32_e32 v0, v01873; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x458000001874; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc1875; GCN-IEEE-SAFE-NEXT: v_fma_f32 v0, v0, v2, v11876; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1877 %sqrt = call contract float @llvm.sqrt.f32(float %val0), !fpmath !11878 %div = fdiv contract float 1.0, %sqrt, !fpmath !11879 %add = fadd contract float %div, %val11880 ret float %add1881}1882 1883; Missing contract on the fadd1884define float @v_rsq_f32_contractable_user_missing_contract1(float %val0, float %val1) {1885; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract1:1886; GCN-DAZ: ; %bb.0:1887; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1888; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v01889; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v11890; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]1891;1892; GCN-IEEE-SAFE-LABEL: v_rsq_f32_contractable_user_missing_contract1:1893; GCN-IEEE-SAFE: ; %bb.0:1894; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1895; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8000001896; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01897; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 24, vcc1898; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v21899; GCN-IEEE-SAFE-NEXT: v_rsq_f32_e32 v0, v01900; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 12, vcc1901; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v21902; GCN-IEEE-SAFE-NEXT: v_add_f32_e32 v0, v0, v11903; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1904 %sqrt = call contract float @llvm.sqrt.f32(float %val0), !fpmath !11905 %div = fdiv contract float 1.0, %sqrt, !fpmath !11906 %add = fadd float %div, %val11907 ret float %add1908}1909 1910define float @v_rsq_f32_known_never_denormal(float nofpclass(sub) %val) {1911; GCN-DAZ-LABEL: v_rsq_f32_known_never_denormal:1912; GCN-DAZ: ; %bb.0:1913; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1914; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v01915; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]1916;1917; GCN-IEEE-LABEL: v_rsq_f32_known_never_denormal:1918; GCN-IEEE: ; %bb.0:1919; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1920; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v01921; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]1922 %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !11923 %div = fdiv contract float 1.0, %sqrt, !fpmath !11924 ret float %div1925}1926 1927define float @v_rsq_f32_known_never_posdenormal(float nofpclass(psub) %val) {1928; GCN-DAZ-LABEL: v_rsq_f32_known_never_posdenormal:1929; GCN-DAZ: ; %bb.0:1930; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1931; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v01932; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]1933;1934; GCN-IEEE-SAFE-LABEL: v_rsq_f32_known_never_posdenormal:1935; GCN-IEEE-SAFE: ; %bb.0:1936; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1937; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x8000001938; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v01939; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc1940; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v11941; GCN-IEEE-SAFE-NEXT: v_rsq_f32_e32 v0, v01942; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc1943; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v11944; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]1945 %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !11946 %div = fdiv contract float 1.0, %sqrt, !fpmath !11947 ret float %div1948}1949 1950!0 = !{float 2.500000e+00}1951!1 = !{float 1.000000e+00}1952 1953attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }1954;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1955; CI-DAZ-SAFE: {{.*}}1956; SI-DAZ-SAFE: {{.*}}1957