972 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-UNSAFE,SI-DAZ-UNSAFE %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-UNSAFE,SI-IEEE-UNSAFE %s4 5 6; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-UNSAFE,CI-DAZ-UNSAFE %s7; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=hawaii -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-UNSAFE,CI-IEEE-UNSAFE %s8 9 10declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone11declare float @llvm.sqrt.f32(float) nounwind readnone12declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) nounwind readnone13 14define amdgpu_kernel void @rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {15; GCN-DAZ-LABEL: rsq_f32:16; GCN-DAZ: ; %bb.0:17; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x918; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf00019; GCN-DAZ-NEXT: s_mov_b32 s6, -120; GCN-DAZ-NEXT: s_mov_b32 s10, s621; GCN-DAZ-NEXT: s_mov_b32 s11, s722; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)23; GCN-DAZ-NEXT: s_mov_b32 s8, s224; GCN-DAZ-NEXT: s_mov_b32 s9, s325; GCN-DAZ-NEXT: buffer_load_dword v0, off, s[8:11], 026; GCN-DAZ-NEXT: s_mov_b32 s4, s027; GCN-DAZ-NEXT: s_mov_b32 s5, s128; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)29; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v030; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[4:7], 031; GCN-DAZ-NEXT: s_endpgm32;33; GCN-IEEE-LABEL: rsq_f32:34; GCN-IEEE: ; %bb.0:35; GCN-IEEE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x936; GCN-IEEE-NEXT: s_mov_b32 s7, 0xf00037; GCN-IEEE-NEXT: s_mov_b32 s6, -138; GCN-IEEE-NEXT: s_mov_b32 s10, s639; GCN-IEEE-NEXT: s_mov_b32 s11, s740; GCN-IEEE-NEXT: s_waitcnt lgkmcnt(0)41; GCN-IEEE-NEXT: s_mov_b32 s8, s242; GCN-IEEE-NEXT: s_mov_b32 s9, s343; GCN-IEEE-NEXT: buffer_load_dword v0, off, s[8:11], 044; GCN-IEEE-NEXT: s_mov_b32 s4, s045; GCN-IEEE-NEXT: s_mov_b32 s5, s146; GCN-IEEE-NEXT: s_waitcnt vmcnt(0)47; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v048; GCN-IEEE-NEXT: buffer_store_dword v0, off, s[4:7], 049; GCN-IEEE-NEXT: s_endpgm50; GCN-UNSAFE-LABEL: rsq_f32:51; GCN-UNSAFE: ; %bb.0:52; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x953; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf00054; GCN-UNSAFE-NEXT: s_mov_b32 s6, -155; GCN-UNSAFE-NEXT: s_mov_b32 s10, s656; GCN-UNSAFE-NEXT: s_mov_b32 s11, s757; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)58; GCN-UNSAFE-NEXT: s_mov_b32 s8, s259; GCN-UNSAFE-NEXT: s_mov_b32 s9, s360; GCN-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 061; GCN-UNSAFE-NEXT: s_mov_b32 s4, s062; GCN-UNSAFE-NEXT: s_mov_b32 s5, s163; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)64; GCN-UNSAFE-NEXT: v_rsq_f32_e32 v0, v065; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 066; GCN-UNSAFE-NEXT: s_endpgm67 %val = load float, ptr addrspace(1) %in, align 468 %sqrt = call afn contract float @llvm.sqrt.f32(float %val) nounwind readnone69 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !070 store float %div, ptr addrspace(1) %out, align 471 ret void72}73 74define amdgpu_kernel void @rsq_f32_sgpr(ptr addrspace(1) noalias %out, float %val) {75; GCN-DAZ-LABEL: rsq_f32_sgpr:76; GCN-DAZ: ; %bb.0:77; GCN-DAZ-NEXT: s_load_dword s2, s[4:5], 0xb78; GCN-DAZ-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x979; GCN-DAZ-NEXT: s_mov_b32 s3, 0xf00080; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)81; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, s282; GCN-DAZ-NEXT: s_mov_b32 s2, -183; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[0:3], 084; GCN-DAZ-NEXT: s_endpgm85;86; GCN-IEEE-LABEL: rsq_f32_sgpr:87; GCN-IEEE: ; %bb.0:88; GCN-IEEE-NEXT: s_load_dword s2, s[4:5], 0xb89; GCN-IEEE-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x990; GCN-IEEE-NEXT: s_mov_b32 s3, 0xf00091; GCN-IEEE-NEXT: s_waitcnt lgkmcnt(0)92; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, s293; GCN-IEEE-NEXT: s_mov_b32 s2, -194; GCN-IEEE-NEXT: buffer_store_dword v0, off, s[0:3], 095; GCN-IEEE-NEXT: s_endpgm96; GCN-UNSAFE-LABEL: rsq_f32_sgpr:97; GCN-UNSAFE: ; %bb.0:98; GCN-UNSAFE-NEXT: s_load_dword s2, s[0:1], 0xb99; GCN-UNSAFE-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9100; GCN-UNSAFE-NEXT: s_mov_b32 s3, 0xf000101; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)102; GCN-UNSAFE-NEXT: v_rsq_f32_e32 v0, s2103; GCN-UNSAFE-NEXT: s_mov_b32 s2, -1104; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[0:3], 0105; GCN-UNSAFE-NEXT: s_endpgm106 %sqrt = call afn contract float @llvm.sqrt.f32(float %val) nounwind readnone107 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !0108 store float %div, ptr addrspace(1) %out, align 4109 ret void110}111 112; Recognize that this is rsqrt(a) * rcp(b) * c,113; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.114 115; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare.116define amdgpu_kernel void @rsqrt_fmul(ptr addrspace(1) %out, ptr addrspace(1) %in) {117; GCN-UNSAFE-LABEL: rsqrt_fmul:118; GCN-UNSAFE: ; %bb.0:119; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9120; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000121; GCN-UNSAFE-NEXT: s_mov_b32 s6, 0122; GCN-UNSAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0123; GCN-UNSAFE-NEXT: v_mov_b32_e32 v1, 0124; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)125; GCN-UNSAFE-NEXT: s_mov_b64 s[8:9], s[2:3]126; GCN-UNSAFE-NEXT: s_mov_b64 s[10:11], s[6:7]127; GCN-UNSAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc128; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)129; GCN-UNSAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc130; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)131; GCN-UNSAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc132; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)133; GCN-UNSAFE-NEXT: s_mov_b64 s[4:5], s[0:1]134; GCN-UNSAFE-NEXT: v_sqrt_f32_e32 v2, v2135; GCN-UNSAFE-NEXT: v_mul_f32_e32 v2, v2, v3136; GCN-UNSAFE-NEXT: v_rcp_f32_e32 v2, v2137; GCN-UNSAFE-NEXT: v_mul_f32_e32 v2, v4, v2138; GCN-UNSAFE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64139; GCN-UNSAFE-NEXT: s_endpgm140; GCN-DAZ-LABEL: rsqrt_fmul:141; GCN-DAZ: ; %bb.0:142; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9143; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf000144; GCN-DAZ-NEXT: s_mov_b32 s6, 0145; GCN-DAZ-NEXT: v_lshlrev_b32_e32 v0, 2, v0146; GCN-DAZ-NEXT: v_mov_b32_e32 v1, 0147; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)148; GCN-DAZ-NEXT: s_mov_b64 s[8:9], s[2:3]149; GCN-DAZ-NEXT: s_mov_b64 s[10:11], s[6:7]150; GCN-DAZ-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc151; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)152; GCN-DAZ-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc153; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)154; GCN-DAZ-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc155; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)156; GCN-DAZ-NEXT: s_mov_b64 s[4:5], s[0:1]157; GCN-DAZ-NEXT: v_rsq_f32_e32 v2, v2158; GCN-DAZ-NEXT: v_rcp_f32_e32 v3, v3159; GCN-DAZ-NEXT: v_mul_f32_e32 v2, v2, v3160; GCN-DAZ-NEXT: v_mul_f32_e32 v2, v4, v2161; GCN-DAZ-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64162; GCN-DAZ-NEXT: s_endpgm163;164; GCN-IEEE-LABEL: rsqrt_fmul:165; GCN-IEEE: ; %bb.0:166; GCN-IEEE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9167; GCN-IEEE-NEXT: s_mov_b32 s7, 0xf000168; GCN-IEEE-NEXT: s_mov_b32 s6, 0169; GCN-IEEE-NEXT: v_lshlrev_b32_e32 v0, 2, v0170; GCN-IEEE-NEXT: v_mov_b32_e32 v1, 0171; GCN-IEEE-NEXT: s_waitcnt lgkmcnt(0)172; GCN-IEEE-NEXT: s_mov_b64 s[8:9], s[2:3]173; GCN-IEEE-NEXT: s_mov_b64 s[10:11], s[6:7]174; GCN-IEEE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc175; GCN-IEEE-NEXT: s_waitcnt vmcnt(0)176; GCN-IEEE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc177; GCN-IEEE-NEXT: s_waitcnt vmcnt(0)178; GCN-IEEE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc179; GCN-IEEE-NEXT: s_waitcnt vmcnt(0)180; GCN-IEEE-NEXT: s_mov_b64 s[4:5], s[0:1]181; GCN-IEEE-NEXT: v_rsq_f32_e32 v2, v2182; GCN-IEEE-NEXT: v_rcp_f32_e32 v3, v3183; GCN-IEEE-NEXT: v_mul_f32_e32 v2, v2, v3184; GCN-IEEE-NEXT: v_mul_f32_e32 v2, v4, v2185; GCN-IEEE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64186; GCN-IEEE-NEXT: s_endpgm187 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone188 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid189 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid190 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1191 %gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2192 193 %a = load volatile float, ptr addrspace(1) %gep.0194 %b = load volatile float, ptr addrspace(1) %gep.1195 %c = load volatile float, ptr addrspace(1) %gep.2196 197 %x = call contract float @llvm.sqrt.f32(float %a)198 %y = fmul contract float %x, %b199 %z = fdiv arcp afn contract float %c, %y200 store float %z, ptr addrspace(1) %out.gep201 ret void202}203 204define amdgpu_kernel void @neg_rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {205; GCN-DAZ-LABEL: neg_rsq_f32:206; GCN-DAZ: ; %bb.0:207; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9208; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf000209; GCN-DAZ-NEXT: s_mov_b32 s6, -1210; GCN-DAZ-NEXT: s_mov_b32 s10, s6211; GCN-DAZ-NEXT: s_mov_b32 s11, s7212; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)213; GCN-DAZ-NEXT: s_mov_b32 s8, s2214; GCN-DAZ-NEXT: s_mov_b32 s9, s3215; GCN-DAZ-NEXT: buffer_load_dword v0, off, s[8:11], 0216; GCN-DAZ-NEXT: s_mov_b32 s4, s0217; GCN-DAZ-NEXT: s_mov_b32 s5, s1218; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)219; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0220; GCN-DAZ-NEXT: v_xor_b32_e32 v0, 0x80000000, v0221; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[4:7], 0222; GCN-DAZ-NEXT: s_endpgm223;224; GCN-IEEE-LABEL: neg_rsq_f32:225; GCN-IEEE: ; %bb.0:226; GCN-IEEE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9227; GCN-IEEE-NEXT: s_mov_b32 s7, 0xf000228; GCN-IEEE-NEXT: s_mov_b32 s6, -1229; GCN-IEEE-NEXT: s_mov_b32 s10, s6230; GCN-IEEE-NEXT: s_mov_b32 s11, s7231; GCN-IEEE-NEXT: s_waitcnt lgkmcnt(0)232; GCN-IEEE-NEXT: s_mov_b32 s8, s2233; GCN-IEEE-NEXT: s_mov_b32 s9, s3234; GCN-IEEE-NEXT: buffer_load_dword v0, off, s[8:11], 0235; GCN-IEEE-NEXT: s_mov_b32 s4, s0236; GCN-IEEE-NEXT: s_mov_b32 s5, s1237; GCN-IEEE-NEXT: s_waitcnt vmcnt(0)238; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0239; GCN-IEEE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0240; GCN-IEEE-NEXT: buffer_store_dword v0, off, s[4:7], 0241; GCN-IEEE-NEXT: s_endpgm242; GCN-UNSAFE-LABEL: neg_rsq_f32:243; GCN-UNSAFE: ; %bb.0:244; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9245; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000246; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1247; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6248; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7249; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)250; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2251; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3252; GCN-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0253; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0254; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1255; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)256; GCN-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0257; GCN-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0258; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0259; GCN-UNSAFE-NEXT: s_endpgm260 %val = load float, ptr addrspace(1) %in, align 4261 %sqrt = call afn contract float @llvm.sqrt.f32(float %val)262 %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0263 store float %div, ptr addrspace(1) %out, align 4264 ret void265}266 267define amdgpu_kernel void @neg_rsq_neg_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {268; GCN-DAZ-LABEL: neg_rsq_neg_f32:269; GCN-DAZ: ; %bb.0:270; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9271; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf000272; GCN-DAZ-NEXT: s_mov_b32 s6, -1273; GCN-DAZ-NEXT: s_mov_b32 s10, s6274; GCN-DAZ-NEXT: s_mov_b32 s11, s7275; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)276; GCN-DAZ-NEXT: s_mov_b32 s8, s2277; GCN-DAZ-NEXT: s_mov_b32 s9, s3278; GCN-DAZ-NEXT: buffer_load_dword v0, off, s[8:11], 0279; GCN-DAZ-NEXT: s_mov_b32 s4, s0280; GCN-DAZ-NEXT: s_mov_b32 s5, s1281; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)282; GCN-DAZ-NEXT: v_rsq_f32_e64 v0, -v0283; GCN-DAZ-NEXT: v_xor_b32_e32 v0, 0x80000000, v0284; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[4:7], 0285; GCN-DAZ-NEXT: s_endpgm286;287; GCN-IEEE-LABEL: neg_rsq_neg_f32:288; GCN-IEEE: ; %bb.0:289; GCN-IEEE-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9290; GCN-IEEE-NEXT: s_mov_b32 s7, 0xf000291; GCN-IEEE-NEXT: s_mov_b32 s6, -1292; GCN-IEEE-NEXT: s_mov_b32 s10, s6293; GCN-IEEE-NEXT: s_mov_b32 s11, s7294; GCN-IEEE-NEXT: s_waitcnt lgkmcnt(0)295; GCN-IEEE-NEXT: s_mov_b32 s8, s2296; GCN-IEEE-NEXT: s_mov_b32 s9, s3297; GCN-IEEE-NEXT: buffer_load_dword v0, off, s[8:11], 0298; GCN-IEEE-NEXT: s_mov_b32 s4, s0299; GCN-IEEE-NEXT: s_mov_b32 s5, s1300; GCN-IEEE-NEXT: s_waitcnt vmcnt(0)301; GCN-IEEE-NEXT: v_rsq_f32_e64 v0, -v0302; GCN-IEEE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0303; GCN-IEEE-NEXT: buffer_store_dword v0, off, s[4:7], 0304; GCN-IEEE-NEXT: s_endpgm305; GCN-UNSAFE-LABEL: neg_rsq_neg_f32:306; GCN-UNSAFE: ; %bb.0:307; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9308; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000309; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1310; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6311; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7312; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)313; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2314; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3315; GCN-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0316; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0317; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1318; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)319; GCN-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0320; GCN-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0321; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0322; GCN-UNSAFE-NEXT: s_endpgm323 %val = load float, ptr addrspace(1) %in, align 4324 %val.fneg = fneg float %val325 %sqrt = call afn contract float @llvm.sqrt.f32(float %val.fneg)326 %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0327 store float %div, ptr addrspace(1) %out, align 4328 ret void329}330 331define float @v_neg_rsq_neg_f32(float %val) {332; GCN-DAZ-LABEL: v_neg_rsq_neg_f32:333; GCN-DAZ: ; %bb.0:334; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)335; GCN-DAZ-NEXT: v_rsq_f32_e64 v0, -v0336; GCN-DAZ-NEXT: v_xor_b32_e32 v0, 0x80000000, v0337; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]338;339; GCN-IEEE-LABEL: v_neg_rsq_neg_f32:340; GCN-IEEE: ; %bb.0:341; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)342; GCN-IEEE-NEXT: v_rsq_f32_e64 v0, -v0343; GCN-IEEE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0344; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]345 %val.fneg = fneg float %val346 %sqrt = call afn contract float @llvm.sqrt.f32(float %val.fneg)347 %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0348 ret float %div349}350 351define <2 x float> @v_neg_rsq_neg_v2f32(<2 x float> %val) {352; GCN-DAZ-LABEL: v_neg_rsq_neg_v2f32:353; GCN-DAZ: ; %bb.0:354; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)355; GCN-DAZ-NEXT: v_rsq_f32_e64 v0, -v0356; GCN-DAZ-NEXT: v_rsq_f32_e64 v1, -v1357; GCN-DAZ-NEXT: v_xor_b32_e32 v0, 0x80000000, v0358; GCN-DAZ-NEXT: v_xor_b32_e32 v1, 0x80000000, v1359; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]360;361; GCN-IEEE-LABEL: v_neg_rsq_neg_v2f32:362; GCN-IEEE: ; %bb.0:363; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)364; GCN-IEEE-NEXT: v_rsq_f32_e64 v0, -v0365; GCN-IEEE-NEXT: v_rsq_f32_e64 v1, -v1366; GCN-IEEE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0367; GCN-IEEE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1368; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]369 %val.fneg = fneg <2 x float> %val370 %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val.fneg)371 %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0372 ret <2 x float> %div373}374 375define float @v_neg_rsq_neg_f32_foldable_user(float %val0, float %val1) {376; GCN-DAZ-LABEL: v_neg_rsq_neg_f32_foldable_user:377; GCN-DAZ: ; %bb.0:378; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)379; GCN-DAZ-NEXT: v_rsq_f32_e64 v0, -v0380; GCN-DAZ-NEXT: v_mul_f32_e64 v0, -v0, v1381; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]382;383; GCN-IEEE-LABEL: v_neg_rsq_neg_f32_foldable_user:384; GCN-IEEE: ; %bb.0:385; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)386; GCN-IEEE-NEXT: v_rsq_f32_e64 v0, -v0387; GCN-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v1388; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]389 %val0.neg = fneg float %val0390 %sqrt = call afn contract float @llvm.sqrt.f32(float %val0.neg)391 %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0392 %user = fmul contract float %div, %val1393 ret float %user394}395 396define <2 x float> @v_neg_rsq_neg_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {397; GCN-DAZ-LABEL: v_neg_rsq_neg_v2f32_foldable_user:398; GCN-DAZ: ; %bb.0:399; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)400; GCN-DAZ-NEXT: v_rsq_f32_e64 v0, -v0401; GCN-DAZ-NEXT: v_rsq_f32_e64 v1, -v1402; GCN-DAZ-NEXT: v_mul_f32_e64 v0, -v0, v2403; GCN-DAZ-NEXT: v_mul_f32_e64 v1, -v1, v3404; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]405;406; GCN-IEEE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:407; GCN-IEEE: ; %bb.0:408; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)409; GCN-IEEE-NEXT: v_rsq_f32_e64 v0, -v0410; GCN-IEEE-NEXT: v_rsq_f32_e64 v1, -v1411; GCN-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v2412; GCN-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v3413; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]414 %val0.fneg = fneg <2 x float> %val0415 %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0.fneg)416 %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0417 %user = fmul contract <2 x float> %div, %val1418 ret <2 x float> %user419}420 421define float @v_neg_rsq_f32(float %val) {422; GCN-DAZ-LABEL: v_neg_rsq_f32:423; GCN-DAZ: ; %bb.0:424; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)425; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0426; GCN-DAZ-NEXT: v_xor_b32_e32 v0, 0x80000000, v0427; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]428;429; GCN-IEEE-LABEL: v_neg_rsq_f32:430; GCN-IEEE: ; %bb.0:431; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0433; GCN-IEEE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0434; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]435 %sqrt = call afn contract float @llvm.sqrt.f32(float %val)436 %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0437 ret float %div438}439 440define <2 x float> @v_neg_rsq_v2f32(<2 x float> %val) {441; GCN-DAZ-LABEL: v_neg_rsq_v2f32:442; GCN-DAZ: ; %bb.0:443; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)444; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0445; GCN-DAZ-NEXT: v_rsq_f32_e32 v1, v1446; GCN-DAZ-NEXT: v_xor_b32_e32 v0, 0x80000000, v0447; GCN-DAZ-NEXT: v_xor_b32_e32 v1, 0x80000000, v1448; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]449;450; GCN-IEEE-LABEL: v_neg_rsq_v2f32:451; GCN-IEEE: ; %bb.0:452; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)453; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0454; GCN-IEEE-NEXT: v_rsq_f32_e32 v1, v1455; GCN-IEEE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0456; GCN-IEEE-NEXT: v_xor_b32_e32 v1, 0x80000000, v1457; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]458 %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val)459 %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0460 ret <2 x float> %div461}462 463define float @v_neg_rsq_f32_foldable_user(float %val0, float %val1) {464; GCN-DAZ-LABEL: v_neg_rsq_f32_foldable_user:465; GCN-DAZ: ; %bb.0:466; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)467; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0468; GCN-DAZ-NEXT: v_mul_f32_e64 v0, -v0, v1469; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]470;471; GCN-IEEE-LABEL: v_neg_rsq_f32_foldable_user:472; GCN-IEEE: ; %bb.0:473; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)474; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0475; GCN-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v1476; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]477 %sqrt = call afn contract float @llvm.sqrt.f32(float %val0)478 %div = fdiv afn contract float -1.0, %sqrt, !fpmath !0479 %user = fmul contract float %div, %val1480 ret float %user481}482 483define <2 x float> @v_neg_rsq_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {484; GCN-DAZ-LABEL: v_neg_rsq_v2f32_foldable_user:485; GCN-DAZ: ; %bb.0:486; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)487; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0488; GCN-DAZ-NEXT: v_rsq_f32_e32 v1, v1489; GCN-DAZ-NEXT: v_mul_f32_e64 v0, -v0, v2490; GCN-DAZ-NEXT: v_mul_f32_e64 v1, -v1, v3491; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]492;493; GCN-IEEE-LABEL: v_neg_rsq_v2f32_foldable_user:494; GCN-IEEE: ; %bb.0:495; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)496; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0497; GCN-IEEE-NEXT: v_rsq_f32_e32 v1, v1498; GCN-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v2499; GCN-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v3500; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]501; GCN-DAZ-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:502; GCN-DAZ-SAFE: ; %bb.0:503; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)504; GCN-DAZ-SAFE-NEXT: s_mov_b32 s4, 0xf800000505; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v1506; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1507; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc508; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v4, v1509; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, v1, v4510; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, 0.5, v4511; GCN-DAZ-SAFE-NEXT: v_fma_f32 v6, -v4, v5, 0.5512; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v6, v5513; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v5, v5, v1514; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v4, v6, v4515; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v7, v4, v5516; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v4517; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc518; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x4f800000, v0519; GCN-DAZ-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0520; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc521; GCN-DAZ-SAFE-NEXT: v_rsq_f32_e32 v5, v0522; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v6, 0x260523; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v6524; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]525; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v4, v0, v5526; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0.5, v5527; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v5, v4, 0.5528; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v4, v7, v4529; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v4, v4, v0530; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v5, v7, v5531; GCN-DAZ-SAFE-NEXT: v_fma_f32 v4, v8, v5, v4532; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v4533; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc534; GCN-DAZ-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v6535; GCN-DAZ-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc536; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v0, -v0537; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e64 v1, -v1538; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2539; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3540; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]541; SI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:542; SI-IEEE-SAFE: ; %bb.0:543; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)544; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0xf800000545; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v1546; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v1547; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc548; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v1549; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], -1, v4550; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v5, v4, v1551; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v6552; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[4:5]553; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v6, s[4:5], 1, v4554; SI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v6, v4, v1555; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v4556; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v5, v6, s[4:5]557; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v4558; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc559; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x4f800000, v0560; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v0561; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc562; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v6, v0563; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v5, 0x260564; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v5565; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]566; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], -1, v6567; SI-IEEE-SAFE-NEXT: v_fma_f32 v7, -v4, v6, v0568; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v7569; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]570; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[4:5], 1, v6571; SI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v7, v6, v0572; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v6573; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]574; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x37800000, v4575; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc576; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v5577; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc578; SI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0x7f800000579; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v0580; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s6581; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, -v0, v4, s[4:5]582; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v4583; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0584; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0585; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v4, v0586; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v1587; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, s6588; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, -v1, v4, s[4:5]589; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v4590; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1591; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v1592; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v4, v1593; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2594; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3595; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]596; CI-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:597; CI-IEEE-SAFE: ; %bb.0:598; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)599; CI-IEEE-SAFE-NEXT: s_mov_b32 s6, 0xf800000600; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, 0x4f800000, v1601; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v1602; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc603; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v4, v1604; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v5, s[4:5], -1, v4605; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v5, v4, v1606; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v6607; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[4:5]608; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v6, s[4:5], 1, v4609; CI-IEEE-SAFE-NEXT: v_fma_f32 v4, -v6, v4, v1610; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v4611; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v5, v6, s[4:5]612; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, 0x37800000, v4613; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc614; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x4f800000, v0615; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s6, v0616; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc617; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v6, v0618; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v5, 0x260619; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e64 s[4:5], v1, v5620; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]621; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v4, s[4:5], -1, v6622; CI-IEEE-SAFE-NEXT: v_fma_f32 v7, -v4, v6, v0623; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v7624; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[4:5]625; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v7, s[4:5], 1, v6626; CI-IEEE-SAFE-NEXT: v_fma_f32 v6, -v7, v6, v0627; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v6628; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]629; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v6, 0x37800000, v4630; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc631; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v5632; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc633; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v0634; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v4635; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0636; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0637; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v4, v0638; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e64 v4, -v1639; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v4, v4640; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v1, v1641; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v1, vcc, 0, v1642; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v4, v1643; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2644; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3645; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]646 %sqrt = call afn contract <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0)647 %div = fdiv afn contract <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0648 %user = fmul contract <2 x float> %div, %val1649 ret <2 x float> %user650}651 652define float @v_rsq_f32(float %val) {653; GCN-DAZ-LABEL: v_rsq_f32:654; GCN-DAZ: ; %bb.0:655; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)656; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0657; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]658;659; GCN-IEEE-LABEL: v_rsq_f32:660; GCN-IEEE: ; %bb.0:661; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)662; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0663; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]664; GCN-IEEE-SAFE-LABEL: v_rsq_f32:665; GCN-IEEE-SAFE: ; %bb.0:666; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x800000668; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0669; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc670; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v1671; GCN-IEEE-SAFE-NEXT: v_rsq_f32_e32 v0, v0672; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc673; GCN-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v0, v1674; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]675 %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1676 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1677 ret float %div678}679 680define { float, float } @v_rsq_f32_multi_use(float %val) {681; GCN-DAZ-LABEL: v_rsq_f32_multi_use:682; GCN-DAZ: ; %bb.0:683; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)684; GCN-DAZ-NEXT: v_sqrt_f32_e32 v2, v0685; GCN-DAZ-NEXT: v_rsq_f32_e32 v1, v0686; GCN-DAZ-NEXT: v_mov_b32_e32 v0, v2687; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]688;689; GCN-IEEE-LABEL: v_rsq_f32_multi_use:690; GCN-IEEE: ; %bb.0:691; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)692; GCN-IEEE-NEXT: v_sqrt_f32_e32 v2, v0693; GCN-IEEE-NEXT: v_rsq_f32_e32 v1, v0694; GCN-IEEE-NEXT: v_mov_b32_e32 v0, v2695; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]696; GCN-DAZ-SAFE-LABEL: v_rsq_f32_multi_use:697; GCN-DAZ-SAFE: ; %bb.0:698; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)699; GCN-DAZ-SAFE-NEXT: v_sqrt_f32_e32 v0, v0700; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v1, v0701; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]702; SI-IEEE-SAFE-LABEL: v_rsq_f32_multi_use:703; SI-IEEE-SAFE: ; %bb.0:704; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)705; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf800000706; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0707; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0708; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc709; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0710; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1711; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0712; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3713; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]714; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1715; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0716; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1717; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]718; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1719; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc720; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260721; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2722; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc723; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f800000724; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0725; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4726; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc727; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1728; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v2, v0729; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v2, vcc, 0, v2730; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v1, v2731; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]732; CI-IEEE-SAFE-LABEL: v_rsq_f32_multi_use:733; CI-IEEE-SAFE: ; %bb.0:734; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)735; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf800000736; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0737; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0738; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc739; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0740; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1741; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0742; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3743; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]744; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1745; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0746; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1747; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]748; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1749; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc750; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260751; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2752; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc753; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0754; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1755; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v2, v0756; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v2, vcc, 0, v2757; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v1, v1, v2758; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]759 %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1760 %insert.0 = insertvalue { float, float } poison, float %sqrt, 0761 %div = fdiv arcp afn contract float 1.0, %sqrt, !fpmath !1762 %insert.1 = insertvalue { float, float } %insert.0, float %div, 1763 ret { float, float } %insert.1764}765 766define float @v_rsq_f32_missing_contract0(float %val) {767; GCN-DAZ-LABEL: v_rsq_f32_missing_contract0:768; GCN-DAZ: ; %bb.0:769; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)770; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0771; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]772;773; GCN-IEEE-LABEL: v_rsq_f32_missing_contract0:774; GCN-IEEE: ; %bb.0:775; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)776; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0777; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]778; GCN-DAZ-SAFE-LABEL: v_rsq_f32_missing_contract0:779; GCN-DAZ-SAFE: ; %bb.0:780; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)781; GCN-DAZ-SAFE-NEXT: v_sqrt_f32_e32 v0, v0782; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v0, v0783; GCN-DAZ-SAFE-NEXT: s_setpc_b64 s[30:31]784; SI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract0:785; SI-IEEE-SAFE: ; %bb.0:786; SI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)787; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf800000788; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0789; SI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0790; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc791; SI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0792; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1793; SI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0794; SI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3795; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]796; SI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1797; SI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0798; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1799; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]800; SI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1801; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc802; SI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260803; SI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2804; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc805; SI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x7f800000806; SI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0807; SI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4808; SI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc809; SI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1810; SI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0811; SI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0812; SI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0813; SI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]814; CI-IEEE-SAFE-LABEL: v_rsq_f32_missing_contract0:815; CI-IEEE-SAFE: ; %bb.0:816; CI-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)817; CI-IEEE-SAFE-NEXT: s_mov_b32 s4, 0xf800000818; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, 0x4f800000, v0819; CI-IEEE-SAFE-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0820; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc821; CI-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v0822; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v2, s[4:5], -1, v1823; CI-IEEE-SAFE-NEXT: v_fma_f32 v3, -v2, v1, v0824; CI-IEEE-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], 0, v3825; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v2, v1, v2, s[4:5]826; CI-IEEE-SAFE-NEXT: v_add_i32_e64 v3, s[4:5], 1, v1827; CI-IEEE-SAFE-NEXT: v_fma_f32 v1, -v3, v1, v0828; CI-IEEE-SAFE-NEXT: v_cmp_lt_f32_e64 s[4:5], 0, v1829; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[4:5]830; CI-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, 0x37800000, v1831; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc832; CI-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x260833; CI-IEEE-SAFE-NEXT: v_cmp_class_f32_e32 vcc, v0, v2834; CI-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc835; CI-IEEE-SAFE-NEXT: v_frexp_mant_f32_e32 v1, v0836; CI-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1837; CI-IEEE-SAFE-NEXT: v_frexp_exp_i32_f32_e32 v0, v0838; CI-IEEE-SAFE-NEXT: v_sub_i32_e32 v0, vcc, 0, v0839; CI-IEEE-SAFE-NEXT: v_ldexp_f32_e32 v0, v1, v0840; CI-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]841 %sqrt = call afn float @llvm.sqrt.f32(float %val), !fpmath !1842 %div = fdiv arcp afn contract float 1.0, %sqrt, !fpmath !1843 ret float %div844}845 846define float @v_rsq_f32_missing_contract1(float %val) {847; GCN-DAZ-LABEL: v_rsq_f32_missing_contract1:848; GCN-DAZ: ; %bb.0:849; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)850; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0851; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]852;853; GCN-IEEE-LABEL: v_rsq_f32_missing_contract1:854; GCN-IEEE: ; %bb.0:855; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)856; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0857; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]858 %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1859 %div = fdiv arcp afn float 1.0, %sqrt, !fpmath !1860 ret float %div861}862 863; Test that we contract into FMA for an fadd user after introducing864; the fmul.865define float @v_rsq_f32_contractable_user(float %val0, float %val1) {866; GCN-DAZ-LABEL: v_rsq_f32_contractable_user:867; GCN-DAZ: ; %bb.0:868; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)869; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0870; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v1871; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]872;873; GCN-IEEE-LABEL: v_rsq_f32_contractable_user:874; GCN-IEEE: ; %bb.0:875; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)876; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0877; GCN-IEEE-NEXT: v_add_f32_e32 v0, v0, v1878; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]879 %sqrt = call afn contract float @llvm.sqrt.f32(float %val0), !fpmath !1880 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1881 %add = fadd contract float %div, %val1882 ret float %add883}884 885; Missing contract on the fdiv886define float @v_rsq_f32_contractable_user_missing_contract0(float %val0, float %val1) {887; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract0:888; GCN-DAZ: ; %bb.0:889; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)890; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0891; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v1892; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]893;894; GCN-IEEE-LABEL: v_rsq_f32_contractable_user_missing_contract0:895; GCN-IEEE: ; %bb.0:896; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)897; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0898; GCN-IEEE-NEXT: v_add_f32_e32 v0, v0, v1899; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]900 %sqrt = call afn contract float @llvm.sqrt.f32(float %val0), !fpmath !1901 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1902 %add = fadd contract float %div, %val1903 ret float %add904}905 906; Missing contract on the fadd907define float @v_rsq_f32_contractable_user_missing_contract1(float %val0, float %val1) {908; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract1:909; GCN-DAZ: ; %bb.0:910; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)911; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0912; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v1913; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]914;915; GCN-IEEE-LABEL: v_rsq_f32_contractable_user_missing_contract1:916; GCN-IEEE: ; %bb.0:917; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)918; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0919; GCN-IEEE-NEXT: v_add_f32_e32 v0, v0, v1920; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]921 %sqrt = call afn contract float @llvm.sqrt.f32(float %val0), !fpmath !1922 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1923 %add = fadd float %div, %val1924 ret float %add925}926 927define float @v_rsq_f32_known_never_denormal(float nofpclass(sub) %val) {928; GCN-DAZ-LABEL: v_rsq_f32_known_never_denormal:929; GCN-DAZ: ; %bb.0:930; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)931; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0932; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]933;934; GCN-IEEE-LABEL: v_rsq_f32_known_never_denormal:935; GCN-IEEE: ; %bb.0:936; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)937; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0938; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]939 %sqrt = call contract float @llvm.sqrt.f32(float %val), !fpmath !1940 %div = fdiv contract float 1.0, %sqrt, !fpmath !1941 ret float %div942}943 944define float @v_rsq_f32_known_never_posdenormal(float nofpclass(psub) %val) {945; GCN-DAZ-LABEL: v_rsq_f32_known_never_posdenormal:946; GCN-DAZ: ; %bb.0:947; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)948; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0949; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]950;951; GCN-IEEE-LABEL: v_rsq_f32_known_never_posdenormal:952; GCN-IEEE: ; %bb.0:953; GCN-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)954; GCN-IEEE-NEXT: v_rsq_f32_e32 v0, v0955; GCN-IEEE-NEXT: s_setpc_b64 s[30:31]956 %sqrt = call afn contract float @llvm.sqrt.f32(float %val), !fpmath !1957 %div = fdiv afn contract float 1.0, %sqrt, !fpmath !1958 ret float %div959}960 961!0 = !{float 2.500000e+00}962!1 = !{float 1.000000e+00}963 964attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }965;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:966; CI-DAZ-UNSAFE: {{.*}}967; CI-IEEE-UNSAFE: {{.*}}968; GCN-DAZ-UNSAFE: {{.*}}969; GCN-IEEE-UNSAFE: {{.*}}970; SI-DAZ-UNSAFE: {{.*}}971; SI-IEEE-UNSAFE: {{.*}}972