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1; RUN: llc < %s -mtriple=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s2 3; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]4define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {5bb:6 %tmp = extractelement <4 x float> %reg1, i32 07 %tmp1 = extractelement <4 x float> %reg1, i32 18 %tmp2 = extractelement <4 x float> %reg1, i32 29 %tmp3 = extractelement <4 x float> %reg1, i32 310 %tmp4 = insertelement <4 x float> poison, float %tmp, i32 011 %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 112 %tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 213 %tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 314 %tmp8 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>15 %tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1)16 %tmp10 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>17 %tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 1, i32 1)18 %tmp12 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>19 %tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1, i32 1, i32 1, i32 1)20 %tmp14 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>21 %tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1, i32 1, i32 1, i32 1)22 %tmp16 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>23 %tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i32 1, i32 1, i32 1, i32 1)24 %tmp18 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>25 %tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i32 1, i32 1, i32 1, i32 1)26 %tmp20 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>27 %tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i32 1, i32 1, i32 1, i32 1)28 %tmp22 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>29 %tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i32 1, i32 1, i32 1, i32 1)30 %tmp24 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>31 %tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i32 1, i32 1, i32 1, i32 1)32 %tmp26 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>33 %tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 9, i32 0, i32 1, i32 1, i32 1, i32 1)34 %tmp28 = fadd <4 x float> %tmp9, %tmp1135 %tmp29 = fadd <4 x float> %tmp28, %tmp1336 %tmp30 = fadd <4 x float> %tmp29, %tmp1537 %tmp31 = fadd <4 x float> %tmp30, %tmp1738 %tmp32 = fadd <4 x float> %tmp31, %tmp1939 %tmp33 = fadd <4 x float> %tmp32, %tmp2140 %tmp34 = fadd <4 x float> %tmp33, %tmp2341 %tmp35 = fadd <4 x float> %tmp34, %tmp2542 %tmp36 = fadd <4 x float> %tmp35, %tmp2743 call void @llvm.r600.store.swizzle(<4 x float> %tmp36, i32 0, i32 2)44 ret void45}46 47declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)48 49; Function Attrs: nounwind readnone50declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #051 52attributes #0 = { nounwind readnone }53