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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s3; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX12,GFX12-ISEL %s4 5define amdgpu_kernel void @kernel1() #0 {6; GFX12-LABEL: kernel1:7; GFX12: ; %bb.0:8; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GFX12-NEXT: s_cmp_eq_u32 0, 010; GFX12-NEXT: s_barrier_signal_isfirst -111; GFX12-NEXT: s_barrier_wait -112; GFX12-NEXT: s_cselect_b32 s0, -1, 013; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)14; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s015; GFX12-NEXT: s_cbranch_vccnz .LBB0_216; GFX12-NEXT: ; %bb.1:17; GFX12-NEXT: s_barrier_signal -318; GFX12-NEXT: .LBB0_2:19; GFX12-NEXT: s_barrier_wait -320; GFX12-NEXT: s_get_barrier_state s0, -321; GFX12-NEXT: s_endpgm22 call void @llvm.amdgcn.s.cluster.barrier()23 %state3 = call i32 @llvm.amdgcn.s.get.barrier.state(i32 -3)24 ret void25}26 27declare void @llvm.amdgcn.s.cluster.barrier() #128declare i32 @llvm.amdgcn.s.get.barrier.state(i32) #129 30attributes #0 = { nounwind }31attributes #1 = { convergent nounwind }32attributes #2 = { nounwind readnone }33;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:34; GFX12-ISEL: {{.*}}35; GFX12-SDAG: {{.*}}36