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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s3 4declare i32 @llvm.ctpop.i32(i32)5declare i64 @llvm.ctpop.i64(i64)6declare i32 @llvm.amdgcn.s.quadmask.i32(i32)7declare i64 @llvm.amdgcn.s.quadmask.i64(i64)8 9define amdgpu_ps i32 @shl32(i32 inreg %val0, i32 inreg %val1) {10; CHECK-LABEL: shl32:11; CHECK: ; %bb.0:12; CHECK-NEXT: s_lshl_b32 s0, s0, s113; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 014; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]15; CHECK-NEXT: v_readfirstlane_b32 s0, v016; CHECK-NEXT: ; return to shader part epilog17 %result = shl i32 %val0, %val118 %cmp = icmp ne i32 %result, 019 %zext = zext i1 %cmp to i3220 ret i32 %zext21}22 23define amdgpu_ps i32 @shl64(i64 inreg %val0, i64 inreg %val1) {24; CHECK-LABEL: shl64:25; CHECK: ; %bb.0:26; CHECK-NEXT: s_lshl_b64 s[0:1], s[0:1], s227; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 028; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]29; CHECK-NEXT: v_readfirstlane_b32 s0, v030; CHECK-NEXT: ; return to shader part epilog31 %result = shl i64 %val0, %val132 %cmp = icmp ne i64 %result, 033 %zext = zext i1 %cmp to i3234 ret i32 %zext35}36 37define amdgpu_ps i32 @lshr32(i32 inreg %val0, i32 inreg %val1) {38; CHECK-LABEL: lshr32:39; CHECK: ; %bb.0:40; CHECK-NEXT: s_lshr_b32 s0, s0, s141; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 042; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]43; CHECK-NEXT: v_readfirstlane_b32 s0, v044; CHECK-NEXT: ; return to shader part epilog45 %result = lshr i32 %val0, %val146 %cmp = icmp ne i32 %result, 047 %zext = zext i1 %cmp to i3248 ret i32 %zext49}50 51define amdgpu_ps i32 @lshr64(i64 inreg %val0, i64 inreg %val1) {52; CHECK-LABEL: lshr64:53; CHECK: ; %bb.0:54; CHECK-NEXT: s_lshr_b64 s[0:1], s[0:1], s255; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 056; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]57; CHECK-NEXT: v_readfirstlane_b32 s0, v058; CHECK-NEXT: ; return to shader part epilog59 %result = lshr i64 %val0, %val160 %cmp = icmp ne i64 %result, 061 %zext = zext i1 %cmp to i3262 ret i32 %zext63}64 65define amdgpu_ps i32 @ashr32(i32 inreg %val0, i32 inreg %val1) {66; CHECK-LABEL: ashr32:67; CHECK: ; %bb.0:68; CHECK-NEXT: s_ashr_i32 s0, s0, s169; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 070; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]71; CHECK-NEXT: v_readfirstlane_b32 s0, v072; CHECK-NEXT: ; return to shader part epilog73 %result = ashr i32 %val0, %val174 %cmp = icmp ne i32 %result, 075 %zext = zext i1 %cmp to i3276 ret i32 %zext77}78 79define amdgpu_ps i32 @ashr64(i64 inreg %val0, i64 inreg %val1) {80; CHECK-LABEL: ashr64:81; CHECK: ; %bb.0:82; CHECK-NEXT: s_ashr_i64 s[0:1], s[0:1], s283; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 084; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]85; CHECK-NEXT: v_readfirstlane_b32 s0, v086; CHECK-NEXT: ; return to shader part epilog87 %result = ashr i64 %val0, %val188 %cmp = icmp ne i64 %result, 089 %zext = zext i1 %cmp to i3290 ret i32 %zext91}92 93define amdgpu_ps i32 @abs32(i32 inreg %val0) {94; CHECK-LABEL: abs32:95; CHECK: ; %bb.0:96; CHECK-NEXT: s_abs_i32 s0, s097; CHECK-NEXT: ;;#ASMSTART98; CHECK-NEXT: ; use s099; CHECK-NEXT: ;;#ASMEND100; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0101; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]102; CHECK-NEXT: v_readfirstlane_b32 s0, v0103; CHECK-NEXT: ; return to shader part epilog104 %neg = sub i32 0, %val0105 %cond = icmp sgt i32 %val0, %neg106 %result = select i1 %cond, i32 %val0, i32 %neg107 call void asm "; use $0", "s"(i32 %result)108 %cmp = icmp ne i32 %result, 0109 %zext = zext i1 %cmp to i32110 ret i32 %zext111}112 113define amdgpu_ps i32 @absdiff32(i32 inreg %val0, i32 inreg %val1) {114; CHECK-LABEL: absdiff32:115; CHECK: ; %bb.0:116; CHECK-NEXT: s_absdiff_i32 s0, s0, s1117; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0118; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]119; CHECK-NEXT: v_readfirstlane_b32 s0, v0120; CHECK-NEXT: ; return to shader part epilog121 %diff = sub i32 %val0, %val1122 %result = call i32 @llvm.abs.i32(i32 %diff, i1 false)123 %cmp = icmp ne i32 %result, 0124 %zext = zext i1 %cmp to i32125 ret i32 %zext126}127 128define amdgpu_ps i32 @and32(i32 inreg %val0, i32 inreg %val1) {129; CHECK-LABEL: and32:130; CHECK: ; %bb.0:131; CHECK-NEXT: s_and_b32 s0, s0, s1132; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0133; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]134; CHECK-NEXT: v_readfirstlane_b32 s0, v0135; CHECK-NEXT: ; return to shader part epilog136 %result = and i32 %val0, %val1137 %cmp = icmp ne i32 %result, 0138 %zext = zext i1 %cmp to i32139 ret i32 %zext140}141 142define amdgpu_ps i32 @and64(i64 inreg %val0, i64 inreg %val1) {143; CHECK-LABEL: and64:144; CHECK: ; %bb.0:145; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]146; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0147; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]148; CHECK-NEXT: v_readfirstlane_b32 s0, v0149; CHECK-NEXT: ; return to shader part epilog150 %result = and i64 %val0, %val1151 %cmp = icmp ne i64 %result, 0152 %zext = zext i1 %cmp to i32153 ret i32 %zext154}155 156define amdgpu_ps i32 @and32_clear_one_bit(i32 inreg %val0) {157; CHECK-LABEL: and32_clear_one_bit:158; CHECK: ; %bb.0:159; CHECK-NEXT: s_and_b32 s0, s0, 0x7fffffff160; CHECK-NEXT: ;;#ASMSTART161; CHECK-NEXT: ; use s0162; CHECK-NEXT: ;;#ASMEND163; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0164; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]165; CHECK-NEXT: v_readfirstlane_b32 s0, v0166; CHECK-NEXT: ; return to shader part epilog167 %result = and i32 %val0, 2147483647168 call void asm "; use $0", "s"(i32 %result)169 %cmp = icmp ne i32 %result, 0170 %zext = zext i1 %cmp to i32171 ret i32 %zext172}173 174define amdgpu_ps i32 @and64_clear_one_bit(i64 inreg %val0) {175; CHECK-LABEL: and64_clear_one_bit:176; CHECK: ; %bb.0:177; CHECK-NEXT: s_bitset0_b32 s0, 31178; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0179; CHECK-NEXT: ;;#ASMSTART180; CHECK-NEXT: ; use s[0:1]181; CHECK-NEXT: ;;#ASMEND182; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0183; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]184; CHECK-NEXT: v_readfirstlane_b32 s0, v0185; CHECK-NEXT: ; return to shader part epilog186 %result = and i64 %val0, -2147483649187 call void asm "; use $0", "s"(i64 %result)188 %cmp = icmp ne i64 %result, 0189 %zext = zext i1 %cmp to i32190 ret i32 %zext191}192 193define amdgpu_ps i32 @or32(i32 inreg %val0, i32 inreg %val1) {194; CHECK-LABEL: or32:195; CHECK: ; %bb.0:196; CHECK-NEXT: s_or_b32 s0, s0, s1197; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0198; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]199; CHECK-NEXT: v_readfirstlane_b32 s0, v0200; CHECK-NEXT: ; return to shader part epilog201 %result = or i32 %val0, %val1202 %cmp = icmp ne i32 %result, 0203 %zext = zext i1 %cmp to i32204 ret i32 %zext205}206 207define amdgpu_ps i32 @or64(i64 inreg %val0, i64 inreg %val1) {208; CHECK-LABEL: or64:209; CHECK: ; %bb.0:210; CHECK-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]211; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0212; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]213; CHECK-NEXT: v_readfirstlane_b32 s0, v0214; CHECK-NEXT: ; return to shader part epilog215 %result = or i64 %val0, %val1216 %cmp = icmp ne i64 %result, 0217 %zext = zext i1 %cmp to i32218 ret i32 %zext219}220 221define amdgpu_ps i32 @xor32(i32 inreg %val0, i32 inreg %val1) {222; CHECK-LABEL: xor32:223; CHECK: ; %bb.0:224; CHECK-NEXT: s_xor_b32 s0, s0, s1225; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0226; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]227; CHECK-NEXT: v_readfirstlane_b32 s0, v0228; CHECK-NEXT: ; return to shader part epilog229 %result = xor i32 %val0, %val1230 %cmp = icmp ne i32 %result, 0231 %zext = zext i1 %cmp to i32232 ret i32 %zext233}234 235define amdgpu_ps i32 @xor64(i64 inreg %val0, i64 inreg %val1) {236; CHECK-LABEL: xor64:237; CHECK: ; %bb.0:238; CHECK-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]239; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0240; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]241; CHECK-NEXT: v_readfirstlane_b32 s0, v0242; CHECK-NEXT: ; return to shader part epilog243 %result = xor i64 %val0, %val1244 %cmp = icmp ne i64 %result, 0245 %zext = zext i1 %cmp to i32246 ret i32 %zext247}248 249define amdgpu_ps i32 @nand32(i32 inreg %val0, i32 inreg %val1) {250; CHECK-LABEL: nand32:251; CHECK: ; %bb.0:252; CHECK-NEXT: s_nand_b32 s0, s0, s1253; CHECK-NEXT: ;;#ASMSTART254; CHECK-NEXT: ; use s0255; CHECK-NEXT: ;;#ASMEND256; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0257; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]258; CHECK-NEXT: v_readfirstlane_b32 s0, v0259; CHECK-NEXT: ; return to shader part epilog260 %result = and i32 %val0, %val1261 %result2 = xor i32 %result, -1262 call void asm "; use $0", "s"(i32 %result2)263 %cmp = icmp ne i32 %result2, 0264 %zext = zext i1 %cmp to i32265 ret i32 %zext266}267 268define amdgpu_ps i32 @nand64(i64 inreg %val0, i64 inreg %val1) {269; CHECK-LABEL: nand64:270; CHECK: ; %bb.0:271; CHECK-NEXT: s_nand_b64 s[0:1], s[0:1], s[2:3]272; CHECK-NEXT: ;;#ASMSTART273; CHECK-NEXT: ; use s[0:1]274; CHECK-NEXT: ;;#ASMEND275; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0276; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]277; CHECK-NEXT: v_readfirstlane_b32 s0, v0278; CHECK-NEXT: ; return to shader part epilog279 %result = and i64 %val0, %val1280 %result2 = xor i64 %result, -1281 call void asm "; use $0", "s"(i64 %result2)282 %cmp = icmp ne i64 %result2, 0283 %zext = zext i1 %cmp to i32284 ret i32 %zext285}286 287define amdgpu_ps i32 @nor32(i32 inreg %val0, i32 inreg %val1) {288; CHECK-LABEL: nor32:289; CHECK: ; %bb.0:290; CHECK-NEXT: s_nor_b32 s0, s0, s1291; CHECK-NEXT: ;;#ASMSTART292; CHECK-NEXT: ; use s0293; CHECK-NEXT: ;;#ASMEND294; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0295; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]296; CHECK-NEXT: v_readfirstlane_b32 s0, v0297; CHECK-NEXT: ; return to shader part epilog298 %result = or i32 %val0, %val1299 %result2 = xor i32 %result, -1300 call void asm "; use $0", "s"(i32 %result2)301 %cmp = icmp ne i32 %result2, 0302 %zext = zext i1 %cmp to i32303 ret i32 %zext304}305 306define amdgpu_ps i32 @nor64(i64 inreg %val0, i64 inreg %val1) {307; CHECK-LABEL: nor64:308; CHECK: ; %bb.0:309; CHECK-NEXT: s_nor_b64 s[0:1], s[0:1], s[2:3]310; CHECK-NEXT: ;;#ASMSTART311; CHECK-NEXT: ; use s[0:1]312; CHECK-NEXT: ;;#ASMEND313; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0314; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]315; CHECK-NEXT: v_readfirstlane_b32 s0, v0316; CHECK-NEXT: ; return to shader part epilog317 %result = or i64 %val0, %val1318 %result2 = xor i64 %result, -1319 call void asm "; use $0", "s"(i64 %result2)320 %cmp = icmp ne i64 %result2, 0321 %zext = zext i1 %cmp to i32322 ret i32 %zext323}324 325define amdgpu_ps i32 @xnor32(i32 inreg %val0, i32 inreg %val1) {326; CHECK-LABEL: xnor32:327; CHECK: ; %bb.0:328; CHECK-NEXT: s_xnor_b32 s0, s0, s1329; CHECK-NEXT: ;;#ASMSTART330; CHECK-NEXT: ; use s0331; CHECK-NEXT: ;;#ASMEND332; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0333; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]334; CHECK-NEXT: v_readfirstlane_b32 s0, v0335; CHECK-NEXT: ; return to shader part epilog336 %result = xor i32 %val0, %val1337 %result2 = xor i32 %result, -1338 call void asm "; use $0", "s"(i32 %result2)339 %cmp = icmp ne i32 %result2, 0340 %zext = zext i1 %cmp to i32341 ret i32 %zext342}343 344define amdgpu_ps i32 @xnor64(i64 inreg %val0, i64 inreg %val1) {345; CHECK-LABEL: xnor64:346; CHECK: ; %bb.0:347; CHECK-NEXT: s_xnor_b64 s[0:1], s[0:1], s[2:3]348; CHECK-NEXT: ;;#ASMSTART349; CHECK-NEXT: ; use s[0:1]350; CHECK-NEXT: ;;#ASMEND351; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0352; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]353; CHECK-NEXT: v_readfirstlane_b32 s0, v0354; CHECK-NEXT: ; return to shader part epilog355 %result = xor i64 %val0, %val1356 %result2 = xor i64 %result, -1357 call void asm "; use $0", "s"(i64 %result2)358 %cmp = icmp ne i64 %result2, 0359 %zext = zext i1 %cmp to i32360 ret i32 %zext361}362 363define amdgpu_ps i32 @andn232(i32 inreg %val0, i32 inreg %val1) {364; CHECK-LABEL: andn232:365; CHECK: ; %bb.0:366; CHECK-NEXT: s_andn2_b32 s0, s0, s1367; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0368; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]369; CHECK-NEXT: v_readfirstlane_b32 s0, v0370; CHECK-NEXT: ; return to shader part epilog371 %nval1 = xor i32 %val1, -1372 %result = and i32 %val0, %nval1373 %cmp = icmp ne i32 %result, 0374 %zext = zext i1 %cmp to i32375 ret i32 %zext376}377 378define amdgpu_ps i32 @nandn264(i64 inreg %val0, i64 inreg %val1) {379; CHECK-LABEL: nandn264:380; CHECK: ; %bb.0:381; CHECK-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]382; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0383; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]384; CHECK-NEXT: v_readfirstlane_b32 s0, v0385; CHECK-NEXT: ; return to shader part epilog386 %nval1 = xor i64 %val1, -1387 %result = and i64 %val0, %nval1388 %cmp = icmp ne i64 %result, 0389 %zext = zext i1 %cmp to i32390 ret i32 %zext391}392 393define amdgpu_ps i32 @orn232(i32 inreg %val0, i32 inreg %val1) {394; CHECK-LABEL: orn232:395; CHECK: ; %bb.0:396; CHECK-NEXT: s_orn2_b32 s0, s0, s1397; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0398; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]399; CHECK-NEXT: v_readfirstlane_b32 s0, v0400; CHECK-NEXT: ; return to shader part epilog401 %nval1 = xor i32 %val1, -1402 %result = or i32 %val0, %nval1403 %cmp = icmp ne i32 %result, 0404 %zext = zext i1 %cmp to i32405 ret i32 %zext406}407 408define amdgpu_ps i32 @orn264(i64 inreg %val0, i64 inreg %val1) {409; CHECK-LABEL: orn264:410; CHECK: ; %bb.0:411; CHECK-NEXT: s_orn2_b64 s[0:1], s[0:1], s[2:3]412; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0413; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]414; CHECK-NEXT: v_readfirstlane_b32 s0, v0415; CHECK-NEXT: ; return to shader part epilog416 %nval1 = xor i64 %val1, -1417 %result = or i64 %val0, %nval1418 %cmp = icmp ne i64 %result, 0419 %zext = zext i1 %cmp to i32420 ret i32 %zext421}422 423define amdgpu_ps i32 @bfe_i32(i32 inreg %val0) {424; CHECK-LABEL: bfe_i32:425; CHECK: ; %bb.0:426; CHECK-NEXT: s_bfe_i32 s0, s0, 0x80010427; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0428; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]429; CHECK-NEXT: v_readfirstlane_b32 s0, v0430; CHECK-NEXT: ; return to shader part epilog431 %shl = shl i32 %val0, 8432 %result = ashr i32 %shl, 24433 %cmp = icmp ne i32 %result, 0434 %zext = zext i1 %cmp to i32435 ret i32 %zext436}437 438define amdgpu_ps i32 @bfe_i64(i64 inreg %val0) {439; CHECK-LABEL: bfe_i64:440; CHECK: ; %bb.0:441; CHECK-NEXT: s_bfe_i64 s[2:3], s[0:1], 0x80000442; CHECK-NEXT: s_and_b32 s0, s0, 0xff443; CHECK-NEXT: s_mov_b32 s1, 0444; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0445; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0446; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]447; CHECK-NEXT: v_readfirstlane_b32 s0, v0448; CHECK-NEXT: ;;#ASMSTART449; CHECK-NEXT: ; use s[2:3]450; CHECK-NEXT: ;;#ASMEND451; CHECK-NEXT: ; return to shader part epilog452 %shl = shl i64 %val0, 56453 %result = ashr i64 %shl, 56454 call void asm "; use $0", "s"(i64 %result)455 %cmp = icmp ne i64 %result, 0456 %zext = zext i1 %cmp to i32457 ret i32 %zext458}459 460define amdgpu_ps i32 @bfe_u32(i32 inreg %val0) {461; CHECK-LABEL: bfe_u32:462; CHECK: ; %bb.0:463; CHECK-NEXT: s_bfe_u32 s0, s0, 0x80010464; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0465; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]466; CHECK-NEXT: v_readfirstlane_b32 s0, v0467; CHECK-NEXT: ; return to shader part epilog468 %shl = shl i32 %val0, 8469 %result = lshr i32 %shl, 24470 %cmp = icmp ne i32 %result, 0471 %zext = zext i1 %cmp to i32472 ret i32 %zext473}474 475define amdgpu_ps i32 @bfe_u64(i64 inreg %val0) {476; CHECK-LABEL: bfe_u64:477; CHECK: ; %bb.0:478; CHECK-NEXT: s_and_b32 s0, s0, 0xff479; CHECK-NEXT: s_mov_b32 s1, 0480; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0481; CHECK-NEXT: ;;#ASMSTART482; CHECK-NEXT: ; use s[0:1]483; CHECK-NEXT: ;;#ASMEND484; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0485; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]486; CHECK-NEXT: v_readfirstlane_b32 s0, v0487; CHECK-NEXT: ; return to shader part epilog488 %shl = shl i64 %val0, 56489 %result = lshr i64 %shl, 56490 call void asm "; use $0", "s"(i64 %result)491 %cmp = icmp ne i64 %result, 0492 %zext = zext i1 %cmp to i32493 ret i32 %zext494}495 496define amdgpu_ps i32 @bcnt032(i32 inreg %val0) {497; CHECK-LABEL: bcnt032:498; CHECK: ; %bb.0:499; CHECK-NEXT: s_bcnt1_i32_b32 s0, s0500; CHECK-NEXT: s_sub_i32 s0, 32, s0501; CHECK-NEXT: s_cmp_lg_u32 s0, 0502; CHECK-NEXT: ;;#ASMSTART503; CHECK-NEXT: ; use s0504; CHECK-NEXT: ;;#ASMEND505; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0506; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]507; CHECK-NEXT: v_readfirstlane_b32 s0, v0508; CHECK-NEXT: ; return to shader part epilog509 %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone510 %result2 = sub i32 32, %result511 call void asm "; use $0", "s"(i32 %result2)512 %cmp = icmp ne i32 %result2, 0513 %zext = zext i1 %cmp to i32514 ret i32 %zext515}516 517define amdgpu_ps i32 @bcnt064(i64 inreg %val0) {518; CHECK-LABEL: bcnt064:519; CHECK: ; %bb.0:520; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1]521; CHECK-NEXT: s_sub_u32 s0, 64, s0522; CHECK-NEXT: s_subb_u32 s1, 0, 0523; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0524; CHECK-NEXT: ;;#ASMSTART525; CHECK-NEXT: ; use s[0:1]526; CHECK-NEXT: ;;#ASMEND527; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0528; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]529; CHECK-NEXT: v_readfirstlane_b32 s0, v0530; CHECK-NEXT: ; return to shader part epilog531 %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone532 %result2 = sub i64 64, %result533 call void asm "; use $0", "s"(i64 %result2)534 %cmp = icmp ne i64 %result2, 0535 %zext = zext i1 %cmp to i32536 ret i32 %zext537}538 539define amdgpu_ps i32 @bcnt132(i32 inreg %val0) {540; CHECK-LABEL: bcnt132:541; CHECK: ; %bb.0:542; CHECK-NEXT: s_bcnt1_i32_b32 s0, s0543; CHECK-NEXT: ;;#ASMSTART544; CHECK-NEXT: ; use s0545; CHECK-NEXT: ;;#ASMEND546; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0547; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]548; CHECK-NEXT: v_readfirstlane_b32 s0, v0549; CHECK-NEXT: ; return to shader part epilog550 %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone551 call void asm "; use $0", "s"(i32 %result)552 %cmp = icmp ne i32 %result, 0553 %zext = zext i1 %cmp to i32554 ret i32 %zext555}556 557define amdgpu_ps i32 @bcnt164(i64 inreg %val0) {558; CHECK-LABEL: bcnt164:559; CHECK: ; %bb.0:560; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1]561; CHECK-NEXT: s_mov_b32 s1, 0562; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0563; CHECK-NEXT: ;;#ASMSTART564; CHECK-NEXT: ; use s[0:1]565; CHECK-NEXT: ;;#ASMEND566; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0567; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]568; CHECK-NEXT: v_readfirstlane_b32 s0, v0569; CHECK-NEXT: ; return to shader part epilog570 %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone571 call void asm "; use $0", "s"(i64 %result)572 %cmp = icmp ne i64 %result, 0573 %zext = zext i1 %cmp to i32574 ret i32 %zext575}576 577define amdgpu_ps i32 @quadmask32(i32 inreg %val0) {578; CHECK-LABEL: quadmask32:579; CHECK: ; %bb.0:580; CHECK-NEXT: s_quadmask_b32 s0, s0581; CHECK-NEXT: ;;#ASMSTART582; CHECK-NEXT: ; use s0583; CHECK-NEXT: ;;#ASMEND584; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0585; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]586; CHECK-NEXT: v_readfirstlane_b32 s0, v0587; CHECK-NEXT: ; return to shader part epilog588 %result = call i32 @llvm.amdgcn.s.quadmask.i32(i32 %val0) nounwind readnone589 call void asm "; use $0", "s"(i32 %result)590 %cmp = icmp ne i32 %result, 0591 %zext = zext i1 %cmp to i32592 ret i32 %zext593}594 595define amdgpu_ps i32 @quadmask64(i64 inreg %val0) {596; CHECK-LABEL: quadmask64:597; CHECK: ; %bb.0:598; CHECK-NEXT: s_quadmask_b64 s[0:1], s[0:1]599; CHECK-NEXT: ;;#ASMSTART600; CHECK-NEXT: ; use s[0:1]601; CHECK-NEXT: ;;#ASMEND602; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0603; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]604; CHECK-NEXT: v_readfirstlane_b32 s0, v0605; CHECK-NEXT: ; return to shader part epilog606 %result = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %val0) nounwind readnone607 call void asm "; use $0", "s"(i64 %result)608 %cmp = icmp ne i64 %result, 0609 %zext = zext i1 %cmp to i32610 ret i32 %zext611}612 613define amdgpu_ps i32 @not32(i32 inreg %val0) {614; CHECK-LABEL: not32:615; CHECK: ; %bb.0:616; CHECK-NEXT: s_not_b32 s0, s0617; CHECK-NEXT: ;;#ASMSTART618; CHECK-NEXT: ; use s0619; CHECK-NEXT: ;;#ASMEND620; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0621; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]622; CHECK-NEXT: v_readfirstlane_b32 s0, v0623; CHECK-NEXT: ; return to shader part epilog624 %result = xor i32 %val0, -1625 call void asm "; use $0", "s"(i32 %result)626 %cmp = icmp ne i32 %result, 0627 %zext = zext i1 %cmp to i32628 ret i32 %zext629}630 631define amdgpu_ps i32 @not64(i64 inreg %val0) {632; CHECK-LABEL: not64:633; CHECK: ; %bb.0:634; CHECK-NEXT: s_not_b64 s[0:1], s[0:1]635; CHECK-NEXT: ;;#ASMSTART636; CHECK-NEXT: ; use s[0:1]637; CHECK-NEXT: ;;#ASMEND638; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0639; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]640; CHECK-NEXT: v_readfirstlane_b32 s0, v0641; CHECK-NEXT: ; return to shader part epilog642 %result = xor i64 %val0, -1643 call void asm "; use $0", "s"(i64 %result)644 %cmp = icmp ne i64 %result, 0645 %zext = zext i1 %cmp to i32646 ret i32 %zext647}648 649 650; --------------------------------------------------------------------------------651; Negative tests652; --------------------------------------------------------------------------------653 654@1 = extern_weak dso_local addrspace(4) constant i32655 656define amdgpu_ps i32 @si_pc_add_rel_offset_must_not_optimize() {657; CHECK-LABEL: si_pc_add_rel_offset_must_not_optimize:658; CHECK: ; %bb.0:659; CHECK-NEXT: s_getpc_b64 s[0:1]660; CHECK-NEXT: s_add_u32 s0, s0, __unnamed_1@rel32@lo+4661; CHECK-NEXT: s_addc_u32 s1, s1, __unnamed_1@rel32@hi+12662; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0663; CHECK-NEXT: s_cbranch_scc0 .LBB38_2664; CHECK-NEXT: ; %bb.1: ; %endif665; CHECK-NEXT: s_mov_b32 s0, 1666; CHECK-NEXT: s_branch .LBB38_3667; CHECK-NEXT: .LBB38_2: ; %if668; CHECK-NEXT: s_mov_b32 s0, 0669; CHECK-NEXT: s_branch .LBB38_3670; CHECK-NEXT: .LBB38_3:671 %cmp = icmp ne ptr addrspace(4) @1, null672 br i1 %cmp, label %endif, label %if673 674if:675 ret i32 0676 677endif:678 ret i32 1679}680