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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global,-xnack < %s | FileCheck -check-prefix=GFX8 %s4 5define amdgpu_kernel void @s_mulk_i32_k0(ptr addrspace(1) %out, i32 %b) {6; GFX6-LABEL: s_mulk_i32_k0:7; GFX6: ; %bb.0:8; GFX6-NEXT: s_load_dword s6, s[4:5], 0x29; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x010; GFX6-NEXT: s_mov_b32 s3, 0xf00011; GFX6-NEXT: s_mov_b32 s2, -112; GFX6-NEXT: s_waitcnt lgkmcnt(0)13; GFX6-NEXT: s_mul_i32 s4, s6, 0x4114; GFX6-NEXT: v_mov_b32_e32 v0, s415; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 016; GFX6-NEXT: s_endpgm17;18; GFX8-LABEL: s_mulk_i32_k0:19; GFX8: ; %bb.0:20; GFX8-NEXT: s_load_dword s6, s[4:5], 0x821; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x022; GFX8-NEXT: s_mov_b32 s3, 0xf00023; GFX8-NEXT: s_mov_b32 s2, -124; GFX8-NEXT: s_waitcnt lgkmcnt(0)25; GFX8-NEXT: s_mul_i32 s4, s6, 0x4126; GFX8-NEXT: v_mov_b32_e32 v0, s427; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 028; GFX8-NEXT: s_endpgm29 %mul = mul i32 %b, 6530 store i32 %mul, ptr addrspace(1) %out31 ret void32}33 34define amdgpu_kernel void @s_mulk_i32_k1(ptr addrspace(1) %out, i32 %b) {35; GFX6-LABEL: s_mulk_i32_k1:36; GFX6: ; %bb.0:37; GFX6-NEXT: s_load_dword s6, s[4:5], 0x238; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x039; GFX6-NEXT: s_mov_b32 s3, 0xf00040; GFX6-NEXT: s_mov_b32 s2, -141; GFX6-NEXT: s_waitcnt lgkmcnt(0)42; GFX6-NEXT: s_mul_i32 s4, s6, 0x7fff43; GFX6-NEXT: v_mov_b32_e32 v0, s444; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 045; GFX6-NEXT: s_endpgm46;47; GFX8-LABEL: s_mulk_i32_k1:48; GFX8: ; %bb.0:49; GFX8-NEXT: s_load_dword s6, s[4:5], 0x850; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x051; GFX8-NEXT: s_mov_b32 s3, 0xf00052; GFX8-NEXT: s_mov_b32 s2, -153; GFX8-NEXT: s_waitcnt lgkmcnt(0)54; GFX8-NEXT: s_mul_i32 s4, s6, 0x7fff55; GFX8-NEXT: v_mov_b32_e32 v0, s456; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 057; GFX8-NEXT: s_endpgm58 %mul = mul i32 %b, 32767 ; (1 << 15) - 159 store i32 %mul, ptr addrspace(1) %out60 ret void61}62 63define amdgpu_kernel void @s_mulk_i32_k2(ptr addrspace(1) %out, i32 %b) {64; GFX6-LABEL: s_mulk_i32_k2:65; GFX6: ; %bb.0:66; GFX6-NEXT: s_load_dword s6, s[4:5], 0x267; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x068; GFX6-NEXT: s_mov_b32 s3, 0xf00069; GFX6-NEXT: s_mov_b32 s2, -170; GFX6-NEXT: s_waitcnt lgkmcnt(0)71; GFX6-NEXT: s_mul_i32 s4, s6, 0xffffffef72; GFX6-NEXT: v_mov_b32_e32 v0, s473; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 074; GFX6-NEXT: s_endpgm75;76; GFX8-LABEL: s_mulk_i32_k2:77; GFX8: ; %bb.0:78; GFX8-NEXT: s_load_dword s6, s[4:5], 0x879; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x080; GFX8-NEXT: s_mov_b32 s3, 0xf00081; GFX8-NEXT: s_mov_b32 s2, -182; GFX8-NEXT: s_waitcnt lgkmcnt(0)83; GFX8-NEXT: s_mul_i32 s4, s6, 0xffffffef84; GFX8-NEXT: v_mov_b32_e32 v0, s485; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 086; GFX8-NEXT: s_endpgm87 %mul = mul i32 %b, -1788 store i32 %mul, ptr addrspace(1) %out89 ret void90}91 92define amdgpu_kernel void @no_s_mulk_i32_k0(ptr addrspace(1) %out, i32 %b) {93; GFX6-LABEL: no_s_mulk_i32_k0:94; GFX6: ; %bb.0:95; GFX6-NEXT: s_load_dword s6, s[4:5], 0x296; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x097; GFX6-NEXT: s_mov_b32 s3, 0xf00098; GFX6-NEXT: s_mov_b32 s2, -199; GFX6-NEXT: s_waitcnt lgkmcnt(0)100; GFX6-NEXT: s_mul_i32 s4, s6, 0x8001101; GFX6-NEXT: v_mov_b32_e32 v0, s4102; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0103; GFX6-NEXT: s_endpgm104;105; GFX8-LABEL: no_s_mulk_i32_k0:106; GFX8: ; %bb.0:107; GFX8-NEXT: s_load_dword s6, s[4:5], 0x8108; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0109; GFX8-NEXT: s_mov_b32 s3, 0xf000110; GFX8-NEXT: s_mov_b32 s2, -1111; GFX8-NEXT: s_waitcnt lgkmcnt(0)112; GFX8-NEXT: s_mul_i32 s4, s6, 0x8001113; GFX8-NEXT: v_mov_b32_e32 v0, s4114; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0115; GFX8-NEXT: s_endpgm116 %mul = mul i32 %b, 32769 ; 1 << 15 + 1117 store i32 %mul, ptr addrspace(1) %out118 ret void119}120 121@lds = addrspace(3) global [512 x i32] poison, align 4122 123define amdgpu_kernel void @commute_s_mulk_i32(ptr addrspace(1) %out, i32 %b) #0 {124; GFX6-LABEL: commute_s_mulk_i32:125; GFX6: ; %bb.0:126; GFX6-NEXT: s_load_dword s0, s[4:5], 0x2127; GFX6-NEXT: v_mov_b32_e32 v0, 0128; GFX6-NEXT: s_waitcnt lgkmcnt(0)129; GFX6-NEXT: s_mulk_i32 s0, 0x800130; GFX6-NEXT: ;;#ASMSTART131; GFX6-NEXT: ; foo v0, s0132; GFX6-NEXT: ;;#ASMEND133; GFX6-NEXT: s_endpgm134;135; GFX8-LABEL: commute_s_mulk_i32:136; GFX8: ; %bb.0:137; GFX8-NEXT: s_load_dword s0, s[4:5], 0x8138; GFX8-NEXT: v_mov_b32_e32 v0, 0139; GFX8-NEXT: s_waitcnt lgkmcnt(0)140; GFX8-NEXT: s_mulk_i32 s0, 0x800141; GFX8-NEXT: ;;#ASMSTART142; GFX8-NEXT: ; foo v0, s0143; GFX8-NEXT: ;;#ASMEND144; GFX8-NEXT: s_endpgm145 %size = call i32 @llvm.amdgcn.groupstaticsize()146 %add = mul i32 %size, %b147 call void asm sideeffect "; foo $0, $1", "v,s"(ptr addrspace(3) @lds, i32 %add)148 ret void149}150 151declare i32 @llvm.amdgcn.groupstaticsize() #1152 153attributes #0 = { nounwind }154attributes #1 = { nounwind readnone }155