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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -earlycse-debug-hash < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @v_sad_u32_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {5; GCN-LABEL: v_sad_u32_pat1:6; GCN: ; %bb.0:7; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x28; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x09; GCN-NEXT: s_add_i32 s12, s12, s1710; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1311; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 812; GCN-NEXT: s_waitcnt lgkmcnt(0)13; GCN-NEXT: v_mov_b32_e32 v0, s114; GCN-NEXT: v_mov_b32_e32 v1, s215; GCN-NEXT: v_sad_u32 v2, s0, v0, v116; GCN-NEXT: v_mov_b32_e32 v0, s417; GCN-NEXT: v_mov_b32_e32 v1, s518; GCN-NEXT: flat_store_dword v[0:1], v219; GCN-NEXT: s_endpgm20 %icmp0 = icmp ugt i32 %a, %b21 %t0 = select i1 %icmp0, i32 %a, i32 %b22 23 %icmp1 = icmp ule i32 %a, %b24 %t1 = select i1 %icmp1, i32 %a, i32 %b25 26 %ret0 = sub i32 %t0, %t127 %ret = add i32 %ret0, %c28 29 store i32 %ret, ptr addrspace(1) %out30 ret void31}32 33define amdgpu_kernel void @v_sad_u32_constant_pat1(ptr addrspace(1) %out, i32 %a) {34; GCN-LABEL: v_sad_u32_constant_pat1:35; GCN: ; %bb.0:36; GCN-NEXT: s_load_dword s2, s[8:9], 0x237; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x038; GCN-NEXT: v_mov_b32_e32 v0, 0x5a39; GCN-NEXT: s_add_i32 s12, s12, s1740; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1341; GCN-NEXT: s_waitcnt lgkmcnt(0)42; GCN-NEXT: v_sad_u32 v2, s2, v0, 2043; GCN-NEXT: v_mov_b32_e32 v0, s044; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 845; GCN-NEXT: v_mov_b32_e32 v1, s146; GCN-NEXT: flat_store_dword v[0:1], v247; GCN-NEXT: s_endpgm48 %icmp0 = icmp ugt i32 %a, 9049 %t0 = select i1 %icmp0, i32 %a, i32 9050 51 %icmp1 = icmp ule i32 %a, 9052 %t1 = select i1 %icmp1, i32 %a, i32 9053 54 %ret0 = sub i32 %t0, %t155 %ret = add i32 %ret0, 2056 57 store i32 %ret, ptr addrspace(1) %out58 ret void59}60 61define amdgpu_kernel void @v_sad_u32_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {62; GCN-LABEL: v_sad_u32_pat2:63; GCN: ; %bb.0:64; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x265; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x066; GCN-NEXT: s_add_i32 s12, s12, s1767; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1368; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 869; GCN-NEXT: s_waitcnt lgkmcnt(0)70; GCN-NEXT: v_mov_b32_e32 v0, s071; GCN-NEXT: v_mov_b32_e32 v1, s272; GCN-NEXT: v_sad_u32 v2, s1, v0, v173; GCN-NEXT: v_mov_b32_e32 v0, s474; GCN-NEXT: v_mov_b32_e32 v1, s575; GCN-NEXT: flat_store_dword v[0:1], v276; GCN-NEXT: s_endpgm77 %icmp0 = icmp ugt i32 %a, %b78 %sub0 = sub i32 %a, %b79 %sub1 = sub i32 %b, %a80 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub181 82 %ret = add i32 %ret0, %c83 84 store i32 %ret, ptr addrspace(1) %out85 ret void86}87 88define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {89; GCN-LABEL: v_sad_u32_multi_use_sub_pat1:90; GCN: ; %bb.0:91; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]92; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]93; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x294; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x095; GCN-NEXT: s_add_i32 s12, s12, s1796; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 897; GCN-NEXT: s_add_u32 s20, s20, s1798; GCN-NEXT: s_addc_u32 s21, s21, 099; GCN-NEXT: s_waitcnt lgkmcnt(0)100; GCN-NEXT: s_min_u32 s3, s0, s1101; GCN-NEXT: s_max_u32 s0, s0, s1102; GCN-NEXT: s_sub_i32 s0, s0, s3103; GCN-NEXT: v_mov_b32_e32 v0, s4104; GCN-NEXT: v_mov_b32_e32 v2, s0105; GCN-NEXT: s_add_i32 s0, s0, s2106; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13107; GCN-NEXT: v_mov_b32_e32 v1, s5108; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen109; GCN-NEXT: s_waitcnt vmcnt(0)110; GCN-NEXT: v_mov_b32_e32 v2, s0111; GCN-NEXT: flat_store_dword v[0:1], v2112; GCN-NEXT: s_endpgm113 %icmp0 = icmp ugt i32 %a, %b114 %t0 = select i1 %icmp0, i32 %a, i32 %b115 116 %icmp1 = icmp ule i32 %a, %b117 %t1 = select i1 %icmp1, i32 %a, i32 %b118 119 %ret0 = sub i32 %t0, %t1120 store volatile i32 %ret0, ptr addrspace(5) poison121 %ret = add i32 %ret0, %c122 123 store i32 %ret, ptr addrspace(1) %out124 ret void125}126 127define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {128; GCN-LABEL: v_sad_u32_multi_use_add_pat1:129; GCN: ; %bb.0:130; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]131; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]132; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2133; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0134; GCN-NEXT: s_add_i32 s12, s12, s17135; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8136; GCN-NEXT: s_add_u32 s20, s20, s17137; GCN-NEXT: s_waitcnt lgkmcnt(0)138; GCN-NEXT: v_mov_b32_e32 v2, s1139; GCN-NEXT: v_mov_b32_e32 v3, s2140; GCN-NEXT: v_mov_b32_e32 v0, s4141; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13142; GCN-NEXT: s_addc_u32 s21, s21, 0143; GCN-NEXT: v_mov_b32_e32 v1, s5144; GCN-NEXT: v_sad_u32 v2, s0, v2, v3145; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen146; GCN-NEXT: s_waitcnt vmcnt(0)147; GCN-NEXT: flat_store_dword v[0:1], v2148; GCN-NEXT: s_endpgm149 %icmp0 = icmp ugt i32 %a, %b150 %t0 = select i1 %icmp0, i32 %a, i32 %b151 152 %icmp1 = icmp ule i32 %a, %b153 %t1 = select i1 %icmp1, i32 %a, i32 %b154 155 %ret0 = sub i32 %t0, %t1156 %ret = add i32 %ret0, %c157 store volatile i32 %ret, ptr addrspace(5) poison158 store i32 %ret, ptr addrspace(1) %out159 ret void160}161 162define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {163; GCN-LABEL: v_sad_u32_multi_use_max_pat1:164; GCN: ; %bb.0:165; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]166; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]167; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2168; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0169; GCN-NEXT: s_add_i32 s12, s12, s17170; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8171; GCN-NEXT: s_add_u32 s20, s20, s17172; GCN-NEXT: s_addc_u32 s21, s21, 0173; GCN-NEXT: s_waitcnt lgkmcnt(0)174; GCN-NEXT: s_max_u32 s3, s0, s1175; GCN-NEXT: v_mov_b32_e32 v0, s1176; GCN-NEXT: v_mov_b32_e32 v1, s2177; GCN-NEXT: v_mov_b32_e32 v2, s3178; GCN-NEXT: v_sad_u32 v3, s0, v0, v1179; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen180; GCN-NEXT: s_waitcnt vmcnt(0)181; GCN-NEXT: v_mov_b32_e32 v0, s4182; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13183; GCN-NEXT: v_mov_b32_e32 v1, s5184; GCN-NEXT: flat_store_dword v[0:1], v3185; GCN-NEXT: s_endpgm186 %icmp0 = icmp ugt i32 %a, %b187 %t0 = select i1 %icmp0, i32 %a, i32 %b188 store volatile i32 %t0, ptr addrspace(5) poison189 190 %icmp1 = icmp ule i32 %a, %b191 %t1 = select i1 %icmp1, i32 %a, i32 %b192 193 %ret0 = sub i32 %t0, %t1194 %ret = add i32 %ret0, %c195 196 store i32 %ret, ptr addrspace(1) %out197 ret void198}199 200define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {201; GCN-LABEL: v_sad_u32_multi_use_min_pat1:202; GCN: ; %bb.0:203; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]204; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]205; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2206; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0207; GCN-NEXT: s_add_i32 s12, s12, s17208; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8209; GCN-NEXT: s_add_u32 s20, s20, s17210; GCN-NEXT: s_addc_u32 s21, s21, 0211; GCN-NEXT: s_waitcnt lgkmcnt(0)212; GCN-NEXT: s_min_u32 s3, s0, s1213; GCN-NEXT: v_mov_b32_e32 v0, s1214; GCN-NEXT: v_mov_b32_e32 v1, s2215; GCN-NEXT: v_mov_b32_e32 v2, s3216; GCN-NEXT: v_sad_u32 v3, s0, v0, v1217; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen218; GCN-NEXT: s_waitcnt vmcnt(0)219; GCN-NEXT: v_mov_b32_e32 v0, s4220; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13221; GCN-NEXT: v_mov_b32_e32 v1, s5222; GCN-NEXT: flat_store_dword v[0:1], v3223; GCN-NEXT: s_endpgm224 %icmp0 = icmp ugt i32 %a, %b225 %t0 = select i1 %icmp0, i32 %a, i32 %b226 227 %icmp1 = icmp ule i32 %a, %b228 %t1 = select i1 %icmp1, i32 %a, i32 %b229 230 store volatile i32 %t1, ptr addrspace(5) poison231 232 %ret0 = sub i32 %t0, %t1233 %ret = add i32 %ret0, %c234 235 store i32 %ret, ptr addrspace(1) %out236 ret void237}238 239define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {240; GCN-LABEL: v_sad_u32_multi_use_sub_pat2:241; GCN: ; %bb.0:242; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]243; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]244; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2245; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0246; GCN-NEXT: s_add_i32 s12, s12, s17247; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8248; GCN-NEXT: s_add_u32 s20, s20, s17249; GCN-NEXT: s_addc_u32 s21, s21, 0250; GCN-NEXT: s_waitcnt lgkmcnt(0)251; GCN-NEXT: s_sub_i32 s3, s0, s1252; GCN-NEXT: v_mov_b32_e32 v0, s0253; GCN-NEXT: v_mov_b32_e32 v1, s2254; GCN-NEXT: v_mov_b32_e32 v2, s3255; GCN-NEXT: v_sad_u32 v3, s1, v0, v1256; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen257; GCN-NEXT: s_waitcnt vmcnt(0)258; GCN-NEXT: v_mov_b32_e32 v0, s4259; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13260; GCN-NEXT: v_mov_b32_e32 v1, s5261; GCN-NEXT: flat_store_dword v[0:1], v3262; GCN-NEXT: s_endpgm263 %icmp0 = icmp ugt i32 %a, %b264 %sub0 = sub i32 %a, %b265 store volatile i32 %sub0, ptr addrspace(5) poison266 %sub1 = sub i32 %b, %a267 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1268 269 %ret = add i32 %ret0, %c270 271 store i32 %ret, ptr addrspace(1) %out272 ret void273}274 275define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {276; GCN-LABEL: v_sad_u32_multi_use_select_pat2:277; GCN: ; %bb.0:278; GCN-NEXT: s_mov_b64 s[22:23], s[2:3]279; GCN-NEXT: s_mov_b64 s[20:21], s[0:1]280; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2281; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0282; GCN-NEXT: s_add_i32 s12, s12, s17283; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8284; GCN-NEXT: s_add_u32 s20, s20, s17285; GCN-NEXT: s_addc_u32 s21, s21, 0286; GCN-NEXT: s_waitcnt lgkmcnt(0)287; GCN-NEXT: s_min_u32 s3, s1, s0288; GCN-NEXT: s_max_u32 s0, s1, s0289; GCN-NEXT: s_sub_i32 s0, s0, s3290; GCN-NEXT: v_mov_b32_e32 v0, s4291; GCN-NEXT: v_mov_b32_e32 v2, s0292; GCN-NEXT: s_add_i32 s0, s0, s2293; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13294; GCN-NEXT: v_mov_b32_e32 v1, s5295; GCN-NEXT: buffer_store_dword v2, v0, s[20:23], 0 offen296; GCN-NEXT: s_waitcnt vmcnt(0)297; GCN-NEXT: v_mov_b32_e32 v2, s0298; GCN-NEXT: flat_store_dword v[0:1], v2299; GCN-NEXT: s_endpgm300 %icmp0 = icmp ugt i32 %a, %b301 %sub0 = sub i32 %a, %b302 %sub1 = sub i32 %b, %a303 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1304 store volatile i32 %ret0, ptr addrspace(5) poison305 306 %ret = add i32 %ret0, %c307 308 store i32 %ret, ptr addrspace(1) %out309 ret void310}311 312define amdgpu_kernel void @v_sad_u32_vector_pat1(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {313; GCN-LABEL: v_sad_u32_vector_pat1:314; GCN: ; %bb.0:315; GCN-NEXT: s_add_i32 s12, s12, s17316; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13317; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8318; GCN-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x4319; GCN-NEXT: s_load_dwordx4 s[12:15], s[8:9], 0xc320; GCN-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0321; GCN-NEXT: s_waitcnt lgkmcnt(0)322; GCN-NEXT: v_mov_b32_e32 v0, s7323; GCN-NEXT: v_mov_b32_e32 v1, s15324; GCN-NEXT: v_mov_b32_e32 v2, s6325; GCN-NEXT: v_sad_u32 v3, s3, v0, v1326; GCN-NEXT: v_mov_b32_e32 v0, s14327; GCN-NEXT: v_sad_u32 v2, s2, v2, v0328; GCN-NEXT: v_mov_b32_e32 v0, s5329; GCN-NEXT: v_mov_b32_e32 v1, s13330; GCN-NEXT: v_sad_u32 v1, s1, v0, v1331; GCN-NEXT: v_mov_b32_e32 v0, s4332; GCN-NEXT: v_mov_b32_e32 v4, s12333; GCN-NEXT: v_sad_u32 v0, s0, v0, v4334; GCN-NEXT: v_mov_b32_e32 v4, s8335; GCN-NEXT: v_mov_b32_e32 v5, s9336; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]337; GCN-NEXT: s_endpgm338 %icmp0 = icmp ugt <4 x i32> %a, %b339 %t0 = select <4 x i1> %icmp0, <4 x i32> %a, <4 x i32> %b340 341 %icmp1 = icmp ule <4 x i32> %a, %b342 %t1 = select <4 x i1> %icmp1, <4 x i32> %a, <4 x i32> %b343 344 %ret0 = sub <4 x i32> %t0, %t1345 %ret = add <4 x i32> %ret0, %c346 347 store <4 x i32> %ret, ptr addrspace(1) %out348 ret void349}350 351define amdgpu_kernel void @v_sad_u32_vector_pat2(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {352; GCN-LABEL: v_sad_u32_vector_pat2:353; GCN: ; %bb.0:354; GCN-NEXT: s_add_i32 s12, s12, s17355; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13356; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8357; GCN-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x4358; GCN-NEXT: s_load_dwordx4 s[12:15], s[8:9], 0xc359; GCN-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0360; GCN-NEXT: s_waitcnt lgkmcnt(0)361; GCN-NEXT: v_mov_b32_e32 v0, s7362; GCN-NEXT: v_mov_b32_e32 v1, s15363; GCN-NEXT: v_mov_b32_e32 v2, s6364; GCN-NEXT: v_sad_u32 v3, s3, v0, v1365; GCN-NEXT: v_mov_b32_e32 v0, s14366; GCN-NEXT: v_sad_u32 v2, s2, v2, v0367; GCN-NEXT: v_mov_b32_e32 v0, s5368; GCN-NEXT: v_mov_b32_e32 v1, s13369; GCN-NEXT: v_sad_u32 v1, s1, v0, v1370; GCN-NEXT: v_mov_b32_e32 v0, s4371; GCN-NEXT: v_mov_b32_e32 v4, s12372; GCN-NEXT: v_sad_u32 v0, s0, v0, v4373; GCN-NEXT: v_mov_b32_e32 v4, s8374; GCN-NEXT: v_mov_b32_e32 v5, s9375; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]376; GCN-NEXT: s_endpgm377 %icmp0 = icmp ugt <4 x i32> %a, %b378 %sub0 = sub <4 x i32> %a, %b379 %sub1 = sub <4 x i32> %b, %a380 %ret0 = select <4 x i1> %icmp0, <4 x i32> %sub0, <4 x i32> %sub1381 382 %ret = add <4 x i32> %ret0, %c383 384 store <4 x i32> %ret, ptr addrspace(1) %out385 ret void386}387 388define amdgpu_kernel void @v_sad_u32_i16_pat1(ptr addrspace(1) %out, i16 %a, i16 %b, i16 %c) {389; GCN-LABEL: v_sad_u32_i16_pat1:390; GCN: ; %bb.0:391; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0392; GCN-NEXT: s_add_i32 s12, s12, s17393; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13394; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8395; GCN-NEXT: s_waitcnt lgkmcnt(0)396; GCN-NEXT: s_and_b32 s4, s2, 0xffff397; GCN-NEXT: s_lshr_b32 s2, s2, 16398; GCN-NEXT: v_mov_b32_e32 v0, s3399; GCN-NEXT: v_mov_b32_e32 v1, s2400; GCN-NEXT: v_sad_u32 v2, s4, v1, v0401; GCN-NEXT: v_mov_b32_e32 v0, s0402; GCN-NEXT: v_mov_b32_e32 v1, s1403; GCN-NEXT: flat_store_short v[0:1], v2404; GCN-NEXT: s_endpgm405 %icmp0 = icmp ugt i16 %a, %b406 %t0 = select i1 %icmp0, i16 %a, i16 %b407 408 %icmp1 = icmp ule i16 %a, %b409 %t1 = select i1 %icmp1, i16 %a, i16 %b410 411 %ret0 = sub i16 %t0, %t1412 %ret = add i16 %ret0, %c413 414 store i16 %ret, ptr addrspace(1) %out415 ret void416}417 418define amdgpu_kernel void @v_sad_u32_i16_pat2(ptr addrspace(1) %out) {419; GCN-LABEL: v_sad_u32_i16_pat2:420; GCN: ; %bb.0:421; GCN-NEXT: s_add_i32 s12, s12, s17422; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13423; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8424; GCN-NEXT: flat_load_ushort v0, v[0:1] glc425; GCN-NEXT: s_waitcnt vmcnt(0)426; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0427; GCN-NEXT: flat_load_ushort v1, v[0:1] glc428; GCN-NEXT: s_waitcnt vmcnt(0)429; GCN-NEXT: flat_load_ushort v2, v[0:1] glc430; GCN-NEXT: s_waitcnt vmcnt(0)431; GCN-NEXT: v_sad_u32 v2, v0, v1, v2432; GCN-NEXT: s_waitcnt lgkmcnt(0)433; GCN-NEXT: v_mov_b32_e32 v0, s0434; GCN-NEXT: v_mov_b32_e32 v1, s1435; GCN-NEXT: flat_store_short v[0:1], v2436; GCN-NEXT: s_endpgm437 %a = load volatile i16, ptr addrspace(1) poison438 %b = load volatile i16, ptr addrspace(1) poison439 %c = load volatile i16, ptr addrspace(1) poison440 %icmp0 = icmp ugt i16 %a, %b441 %sub0 = sub i16 %a, %b442 %sub1 = sub i16 %b, %a443 %ret0 = select i1 %icmp0, i16 %sub0, i16 %sub1444 445 %ret = add i16 %ret0, %c446 447 store i16 %ret, ptr addrspace(1) %out448 ret void449}450 451define amdgpu_kernel void @v_sad_u32_i8_pat1(ptr addrspace(1) %out, i8 %a, i8 %b, i8 %c) {452; GCN-LABEL: v_sad_u32_i8_pat1:453; GCN: ; %bb.0:454; GCN-NEXT: s_load_dword s2, s[8:9], 0x2455; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0456; GCN-NEXT: s_add_i32 s12, s12, s17457; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13458; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8459; GCN-NEXT: s_waitcnt lgkmcnt(0)460; GCN-NEXT: s_and_b32 s3, s2, 0xff461; GCN-NEXT: s_bfe_u32 s4, s2, 0x80008462; GCN-NEXT: s_lshr_b32 s2, s2, 16463; GCN-NEXT: v_mov_b32_e32 v0, s4464; GCN-NEXT: v_mov_b32_e32 v1, s2465; GCN-NEXT: v_sad_u32 v2, s3, v0, v1466; GCN-NEXT: v_mov_b32_e32 v0, s0467; GCN-NEXT: v_mov_b32_e32 v1, s1468; GCN-NEXT: flat_store_byte v[0:1], v2469; GCN-NEXT: s_endpgm470 %icmp0 = icmp ugt i8 %a, %b471 %t0 = select i1 %icmp0, i8 %a, i8 %b472 473 %icmp1 = icmp ule i8 %a, %b474 %t1 = select i1 %icmp1, i8 %a, i8 %b475 476 %ret0 = sub i8 %t0, %t1477 %ret = add i8 %ret0, %c478 479 store i8 %ret, ptr addrspace(1) %out480 ret void481}482 483define amdgpu_kernel void @v_sad_u32_i8_pat2(ptr addrspace(1) %out) {484; GCN-LABEL: v_sad_u32_i8_pat2:485; GCN: ; %bb.0:486; GCN-NEXT: s_add_i32 s12, s12, s17487; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13488; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8489; GCN-NEXT: flat_load_ubyte v0, v[0:1] glc490; GCN-NEXT: s_waitcnt vmcnt(0)491; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0492; GCN-NEXT: flat_load_ubyte v1, v[0:1] glc493; GCN-NEXT: s_waitcnt vmcnt(0)494; GCN-NEXT: flat_load_ubyte v2, v[0:1] glc495; GCN-NEXT: s_waitcnt vmcnt(0)496; GCN-NEXT: v_sad_u32 v2, v0, v1, v2497; GCN-NEXT: s_waitcnt lgkmcnt(0)498; GCN-NEXT: v_mov_b32_e32 v0, s0499; GCN-NEXT: v_mov_b32_e32 v1, s1500; GCN-NEXT: flat_store_byte v[0:1], v2501; GCN-NEXT: s_endpgm502 %a = load volatile i8, ptr addrspace(1) poison503 %b = load volatile i8, ptr addrspace(1) poison504 %c = load volatile i8, ptr addrspace(1) poison505 %icmp0 = icmp ugt i8 %a, %b506 %sub0 = sub i8 %a, %b507 %sub1 = sub i8 %b, %a508 %ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1509 510 %ret = add i8 %ret0, %c511 512 store i8 %ret, ptr addrspace(1) %out513 ret void514}515 516define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) {517; GCN-LABEL: s_sad_u32_i8_pat2:518; GCN: ; %bb.0:519; GCN-NEXT: s_load_dword s2, s[8:9], 0x2520; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0521; GCN-NEXT: s_add_i32 s12, s12, s17522; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13523; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8524; GCN-NEXT: s_waitcnt lgkmcnt(0)525; GCN-NEXT: s_and_b32 s3, s2, 0xff526; GCN-NEXT: s_bfe_u32 s4, s2, 0x80008527; GCN-NEXT: s_lshr_b32 s2, s2, 16528; GCN-NEXT: v_mov_b32_e32 v0, s4529; GCN-NEXT: v_mov_b32_e32 v1, s2530; GCN-NEXT: v_sad_u32 v2, s3, v0, v1531; GCN-NEXT: v_mov_b32_e32 v0, s0532; GCN-NEXT: v_mov_b32_e32 v1, s1533; GCN-NEXT: flat_store_byte v[0:1], v2534; GCN-NEXT: s_endpgm535 %icmp0 = icmp ugt i8 %a, %b536 %sub0 = sub i8 %a, %b537 %sub1 = sub i8 %b, %a538 %ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1539 540 %ret = add i8 %ret0, %c541 542 store i8 %ret, ptr addrspace(1) %out543 ret void544}545 546define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {547; GCN-LABEL: v_sad_u32_mismatched_operands_pat1:548; GCN: ; %bb.0:549; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2550; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0551; GCN-NEXT: s_add_i32 s12, s12, s17552; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8553; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13554; GCN-NEXT: s_waitcnt lgkmcnt(0)555; GCN-NEXT: s_max_u32 s6, s0, s1556; GCN-NEXT: s_cmp_le_u32 s0, s1557; GCN-NEXT: s_cselect_b32 s0, s0, s3558; GCN-NEXT: s_sub_i32 s0, s6, s0559; GCN-NEXT: s_add_i32 s0, s0, s2560; GCN-NEXT: v_mov_b32_e32 v0, s4561; GCN-NEXT: v_mov_b32_e32 v1, s5562; GCN-NEXT: v_mov_b32_e32 v2, s0563; GCN-NEXT: flat_store_dword v[0:1], v2564; GCN-NEXT: s_endpgm565 %icmp0 = icmp ugt i32 %a, %b566 %t0 = select i1 %icmp0, i32 %a, i32 %b567 568 %icmp1 = icmp ule i32 %a, %b569 %t1 = select i1 %icmp1, i32 %a, i32 %d570 571 %ret0 = sub i32 %t0, %t1572 %ret = add i32 %ret0, %c573 574 store i32 %ret, ptr addrspace(1) %out575 ret void576}577 578define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {579; GCN-LABEL: v_sad_u32_mismatched_operands_pat2:580; GCN: ; %bb.0:581; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x2582; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0583; GCN-NEXT: s_add_i32 s12, s12, s17584; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13585; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8586; GCN-NEXT: s_waitcnt lgkmcnt(0)587; GCN-NEXT: v_mov_b32_e32 v0, s0588; GCN-NEXT: s_sub_i32 s0, s0, s3589; GCN-NEXT: v_mov_b32_e32 v1, s0590; GCN-NEXT: v_sub_i32_e32 v0, vcc, s1, v0591; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc592; GCN-NEXT: v_add_i32_e32 v2, vcc, s2, v0593; GCN-NEXT: v_mov_b32_e32 v0, s4594; GCN-NEXT: v_mov_b32_e32 v1, s5595; GCN-NEXT: flat_store_dword v[0:1], v2596; GCN-NEXT: s_endpgm597 %icmp0 = icmp ugt i32 %a, %b598 %sub0 = sub i32 %a, %d599 %sub1 = sub i32 %b, %a600 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1601 602 %ret = add i32 %ret0, %c603 604 store i32 %ret, ptr addrspace(1) %out605 ret void606}607 608