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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s8 9define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {10; GFX6-LABEL: v_saddsat_i8:11; GFX6: ; %bb.0:12; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 814; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 815; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v116; GFX6-NEXT: s_movk_i32 s4, 0xff8017; GFX6-NEXT: v_mov_b32_e32 v1, 0x7f18; GFX6-NEXT: v_med3_i32 v0, v0, s4, v119; GFX6-NEXT: s_setpc_b64 s[30:31]20;21; GFX8-LABEL: v_saddsat_i8:22; GFX8: ; %bb.0:23; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)24; GFX8-NEXT: v_add_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_025; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v026; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v027; GFX8-NEXT: s_setpc_b64 s[30:31]28;29; GFX9-LABEL: v_saddsat_i8:30; GFX9: ; %bb.0:31; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v133; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v034; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp35; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v036; GFX9-NEXT: s_setpc_b64 s[30:31]37;38; GFX10-LABEL: v_saddsat_i8:39; GFX10: ; %bb.0:40; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX10-NEXT: v_lshlrev_b16 v1, 8, v142; GFX10-NEXT: v_lshlrev_b16 v0, 8, v043; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp44; GFX10-NEXT: v_ashrrev_i16 v0, 8, v045; GFX10-NEXT: s_setpc_b64 s[30:31]46;47; GFX11-TRUE16-LABEL: v_saddsat_i8:48; GFX11-TRUE16: ; %bb.0:49; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l51; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l52; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, v0.h clamp53; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v0.l54; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]55;56; GFX11-FAKE16-LABEL: v_saddsat_i8:57; GFX11-FAKE16: ; %bb.0:58; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)59; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v160; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 8, v061; GFX11-FAKE16-NEXT: v_add_nc_i16 v0, v0, v1 clamp62; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, 8, v063; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]64 %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)65 ret i8 %result66}67 68define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {69; GFX6-LABEL: v_saddsat_i16:70; GFX6: ; %bb.0:71; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 1673; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1674; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v175; GFX6-NEXT: s_movk_i32 s4, 0x800076; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fff77; GFX6-NEXT: v_med3_i32 v0, v0, s4, v178; GFX6-NEXT: s_setpc_b64 s[30:31]79;80; GFX8-LABEL: v_saddsat_i16:81; GFX8: ; %bb.0:82; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v184; GFX8-NEXT: v_add_u16_e32 v1, v0, v185; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v086; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v187; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v088; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]89; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc90; GFX8-NEXT: s_setpc_b64 s[30:31]91;92; GFX9-LABEL: v_saddsat_i16:93; GFX9: ; %bb.0:94; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp96; GFX9-NEXT: s_setpc_b64 s[30:31]97;98; GFX10-LABEL: v_saddsat_i16:99; GFX10: ; %bb.0:100; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)101; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp102; GFX10-NEXT: s_setpc_b64 s[30:31]103;104; GFX11-TRUE16-LABEL: v_saddsat_i16:105; GFX11-TRUE16: ; %bb.0:106; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; GFX11-TRUE16-NEXT: v_add_nc_i16 v0.l, v0.l, v1.l clamp108; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]109;110; GFX11-FAKE16-LABEL: v_saddsat_i16:111; GFX11-FAKE16: ; %bb.0:112; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; GFX11-FAKE16-NEXT: v_add_nc_i16 v0, v0, v1 clamp114; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]115 %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)116 ret i16 %result117}118 119define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) {120; GFX6-LABEL: v_saddsat_i32:121; GFX6: ; %bb.0:122; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1124; GFX6-NEXT: v_add_i32_e64 v1, s[4:5], v0, v1125; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0126; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1127; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]128; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5]129; GFX6-NEXT: s_setpc_b64 s[30:31]130;131; GFX8-LABEL: v_saddsat_i32:132; GFX8: ; %bb.0:133; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)134; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1135; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v0, v1136; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0137; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1138; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]139; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5]140; GFX8-NEXT: s_setpc_b64 s[30:31]141;142; GFX9-LABEL: v_saddsat_i32:143; GFX9: ; %bb.0:144; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp146; GFX9-NEXT: s_setpc_b64 s[30:31]147;148; GFX10PLUS-LABEL: v_saddsat_i32:149; GFX10PLUS: ; %bb.0:150; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v1 clamp152; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]153 %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)154 ret i32 %result155}156 157define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {158; GFX6-LABEL: v_saddsat_v2i16:159; GFX6: ; %bb.0:160; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)161; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16162; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16163; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16164; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16165; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3166; GFX6-NEXT: s_movk_i32 s4, 0x8000167; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fff168; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2169; GFX6-NEXT: v_med3_i32 v1, v1, s4, v3170; GFX6-NEXT: v_med3_i32 v0, v0, s4, v3171; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v1172; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0173; GFX6-NEXT: v_or_b32_e32 v0, v0, v4174; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1175; GFX6-NEXT: s_setpc_b64 s[30:31]176;177; GFX8-LABEL: v_saddsat_v2i16:178; GFX8: ; %bb.0:179; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)180; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1181; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0182; GFX8-NEXT: v_add_u16_e32 v4, v3, v2183; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3184; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2185; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4186; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2187; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc188; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc189; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1190; GFX8-NEXT: v_add_u16_e32 v1, v0, v1191; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0192; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1193; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0194; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]195; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2196; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc197; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD198; GFX8-NEXT: s_setpc_b64 s[30:31]199;200; GFX9-LABEL: v_saddsat_v2i16:201; GFX9: ; %bb.0:202; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)203; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp204; GFX9-NEXT: s_setpc_b64 s[30:31]205;206; GFX10PLUS-LABEL: v_saddsat_v2i16:207; GFX10PLUS: ; %bb.0:208; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v1 clamp210; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]211 %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)212 ret <2 x i16> %result213}214 215define <3 x i16> @v_saddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {216; GFX6-LABEL: v_saddsat_v3i16:217; GFX6: ; %bb.0:218; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)219; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16220; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16221; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16222; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16223; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16224; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16225; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4226; GFX6-NEXT: s_movk_i32 s4, 0x8000227; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fff228; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3229; GFX6-NEXT: v_med3_i32 v1, v1, s4, v4230; GFX6-NEXT: v_med3_i32 v0, v0, s4, v4231; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5232; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1233; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0234; GFX6-NEXT: v_med3_i32 v3, v2, s4, v4235; GFX6-NEXT: v_or_b32_e32 v0, v0, v1236; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3237; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16238; GFX6-NEXT: s_setpc_b64 s[30:31]239;240; GFX8-LABEL: v_saddsat_v3i16:241; GFX8: ; %bb.0:242; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)243; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2244; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0245; GFX8-NEXT: v_add_u16_e32 v6, v5, v4246; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5247; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4248; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6249; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4250; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc251; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc252; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3253; GFX8-NEXT: v_add_u16_e32 v3, v1, v3254; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1255; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3256; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1257; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]258; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc259; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2260; GFX8-NEXT: v_add_u16_e32 v2, v0, v2261; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0262; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2263; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0264; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]265; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc266; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4267; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD268; GFX8-NEXT: s_setpc_b64 s[30:31]269;270; GFX9-LABEL: v_saddsat_v3i16:271; GFX9: ; %bb.0:272; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)273; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp274; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp275; GFX9-NEXT: s_setpc_b64 s[30:31]276;277; GFX10PLUS-LABEL: v_saddsat_v3i16:278; GFX10PLUS: ; %bb.0:279; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)280; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v2 clamp281; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v3 clamp282; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]283 %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)284 ret <3 x i16> %result285}286 287define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {288; GFX6-LABEL: v_saddsat_v4i16:289; GFX6: ; %bb.0:290; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)291; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16292; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16293; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16294; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16295; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5296; GFX6-NEXT: s_movk_i32 s4, 0x8000297; GFX6-NEXT: v_mov_b32_e32 v5, 0x7fff298; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4299; GFX6-NEXT: v_med3_i32 v1, v1, s4, v5300; GFX6-NEXT: v_med3_i32 v0, v0, s4, v5301; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16302; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16303; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16304; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16305; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1306; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0307; GFX6-NEXT: v_or_b32_e32 v0, v0, v1308; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v7309; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6310; GFX6-NEXT: v_med3_i32 v1, v1, s4, v5311; GFX6-NEXT: v_med3_i32 v2, v2, s4, v5312; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1313; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2314; GFX6-NEXT: v_or_b32_e32 v1, v2, v1315; GFX6-NEXT: s_setpc_b64 s[30:31]316;317; GFX8-LABEL: v_saddsat_v4i16:318; GFX8: ; %bb.0:319; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2321; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0322; GFX8-NEXT: v_add_u16_e32 v6, v5, v4323; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5324; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4325; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6326; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4327; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc328; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc329; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2330; GFX8-NEXT: v_add_u16_e32 v2, v0, v2331; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0332; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2333; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0334; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]335; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4336; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc337; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD338; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3339; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1340; GFX8-NEXT: v_add_u16_e32 v5, v4, v2341; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4342; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2343; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5344; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2345; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc346; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc347; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3348; GFX8-NEXT: v_add_u16_e32 v3, v1, v3349; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1350; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3351; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1352; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]353; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2354; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc355; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD356; GFX8-NEXT: s_setpc_b64 s[30:31]357;358; GFX9-LABEL: v_saddsat_v4i16:359; GFX9: ; %bb.0:360; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)361; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp362; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp363; GFX9-NEXT: s_setpc_b64 s[30:31]364;365; GFX10PLUS-LABEL: v_saddsat_v4i16:366; GFX10PLUS: ; %bb.0:367; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v2 clamp369; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v3 clamp370; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]371 %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)372 %cast = bitcast <4 x i16> %result to <2 x float>373 ret <2 x float> %cast374}375 376define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {377; GFX6-LABEL: v_saddsat_v2i32:378; GFX6: ; %bb.0:379; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)380; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2381; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v0, v2382; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0383; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2384; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]385; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5]386; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v1, v3387; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3388; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1389; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2390; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]391; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5]392; GFX6-NEXT: s_setpc_b64 s[30:31]393;394; GFX8-LABEL: v_saddsat_v2i32:395; GFX8: ; %bb.0:396; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)397; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2398; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v0, v2399; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0400; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2401; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]402; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5]403; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v1, v3404; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3405; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1406; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2407; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]408; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5]409; GFX8-NEXT: s_setpc_b64 s[30:31]410;411; GFX9-LABEL: v_saddsat_v2i32:412; GFX9: ; %bb.0:413; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)414; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp415; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp416; GFX9-NEXT: s_setpc_b64 s[30:31]417;418; GFX10PLUS-LABEL: v_saddsat_v2i32:419; GFX10PLUS: ; %bb.0:420; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)421; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v2 clamp422; GFX10PLUS-NEXT: v_add_nc_i32 v1, v1, v3 clamp423; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]424 %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)425 ret <2 x i32> %result426}427 428define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) {429; GFX6-LABEL: v_saddsat_i64:430; GFX6: ; %bb.0:431; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GFX6-NEXT: v_add_i32_e32 v4, vcc, v0, v2433; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc434; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]435; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3]436; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5437; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc438; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc439; GFX6-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc440; GFX6-NEXT: s_setpc_b64 s[30:31]441;442; GFX8-LABEL: v_saddsat_i64:443; GFX8: ; %bb.0:444; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)445; GFX8-NEXT: v_add_u32_e32 v4, vcc, v0, v2446; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc447; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]448; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3]449; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v5450; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc451; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc452; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc453; GFX8-NEXT: s_setpc_b64 s[30:31]454;455; GFX9-LABEL: v_saddsat_i64:456; GFX9: ; %bb.0:457; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)458; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2459; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc460; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]461; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3]462; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v5463; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc464; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc465; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc466; GFX9-NEXT: s_setpc_b64 s[30:31]467;468; GFX10-LABEL: v_saddsat_i64:469; GFX10: ; %bb.0:470; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)471; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2472; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo473; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[2:3]474; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]475; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v5476; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo477; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo478; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo479; GFX10-NEXT: s_setpc_b64 s[30:31]480;481; GFX11-LABEL: v_saddsat_i64:482; GFX11: ; %bb.0:483; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)484; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2485; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v3, vcc_lo486; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]487; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]488; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v5489; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo490; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo491; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo492; GFX11-NEXT: s_setpc_b64 s[30:31]493 %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)494 ret i64 %result495}496 497declare i8 @llvm.sadd.sat.i8(i8, i8) #0498declare i16 @llvm.sadd.sat.i16(i16, i16) #0499declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>) #0500declare <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16>, <3 x i16>) #0501declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>) #0502declare i32 @llvm.sadd.sat.i32(i32, i32) #0503declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>) #0504declare i64 @llvm.sadd.sat.i64(i64, i64) #0505