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1; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx802 < %s | FileCheck %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s5 6; This checks for a bug where uniform control flow can result in multiple7; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,8; using the resulting mask in s_cbranch_vccnz9; without ensuring that the resulting mask has bits clear for inactive lanes.10; The problematic case is s_xor_b64, as, unlike the other ops, it can actually11; set bits for inactive lanes.12;13; The check for an s_xor_b64 is just to check that this test tests what it is14; supposed to test. If the s_xor_b64 disappears due to some other case, it does15; not necessarily mean that the bug has reappeared.16;17; The check for "s_and_b64 vcc, exec, something" checks that the bug is fixed.18 19; CHECK: {{^}}main:20; CHECK: s_xor_b6421; CHECK: s_and_b64 vcc, exec,22 23define amdgpu_cs void @main(i32 inreg %arg) {24.entry:25 %tmp44 = load volatile <2 x float>, ptr addrspace(1) poison26 %tmp16 = load volatile float, ptr addrspace(1) poison27 %tmp22 = load volatile float, ptr addrspace(1) poison28 %tmp25 = load volatile float, ptr addrspace(1) poison29 %tmp31 = fcmp olt float %tmp16, 0x3FA99999A000000030 br i1 %tmp31, label %bb, label %.exit.thread31 32bb: ; preds = %.entry33 %tmp42 = fcmp olt float %tmp25, 0x3FA99999A000000034 br i1 %tmp42, label %bb43, label %.exit.thread35 36bb43:37 %tmp46 = fcmp olt <2 x float> %tmp44, <float 0x3FA99999A0000000, float 0x3FA99999A0000000>38 %tmp47 = extractelement <2 x i1> %tmp46, i32 039 %tmp48 = extractelement <2 x i1> %tmp46, i32 140 %tmp49 = and i1 %tmp47, %tmp4841 br i1 %tmp49, label %bb50, label %.exit.thread42 43bb50:44 %tmp53 = fcmp olt float %tmp22, 0x3FA99999A000000045 br i1 %tmp53, label %.exit3.i, label %.exit.thread46 47.exit3.i:48 store volatile i32 0, ptr addrspace(1) poison49 br label %.exit.thread50 51.exit.thread:52 ret void53}54 55