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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck %s4; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s5; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s6 7define amdgpu_vs float @sitofp_i32_to_f32(i32 inreg %val) {8; CHECK-LABEL: sitofp_i32_to_f32:9; CHECK: ; %bb.0:10; CHECK-NEXT: s_cvt_f32_i32 s0, s011; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)12; CHECK-NEXT: v_mov_b32_e32 v0, s013; CHECK-NEXT: ; return to shader part epilog14 %res = sitofp i32 %val to float15 ret float %res16}17 18define amdgpu_vs float @uitofp_u32_to_f32(i32 inreg %val) {19; CHECK-LABEL: uitofp_u32_to_f32:20; CHECK: ; %bb.0:21; CHECK-NEXT: s_cvt_f32_u32 s0, s022; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)23; CHECK-NEXT: v_mov_b32_e32 v0, s024; CHECK-NEXT: ; return to shader part epilog25 %res = uitofp i32 %val to float26 ret float %res27}28 29define amdgpu_vs i32 @fptosi_f32_to_i32(float inreg %val) {30; CHECK-LABEL: fptosi_f32_to_i32:31; CHECK: ; %bb.0:32; CHECK-NEXT: s_cvt_i32_f32 s0, s033; CHECK-NEXT: ; return to shader part epilog34 %res = fptosi float %val to i3235 ret i32 %res36}37 38define amdgpu_vs i32 @fptoui_f32_to_u32(float inreg %val) {39; CHECK-LABEL: fptoui_f32_to_u32:40; CHECK: ; %bb.0:41; CHECK-NEXT: s_cvt_u32_f32 s0, s042; CHECK-NEXT: ; return to shader part epilog43 %res = fptoui float %val to i3244 ret i32 %res45}46 47define amdgpu_vs i16 @fptosi_f32_to_i16(float inreg %val) {48; CHECK-LABEL: fptosi_f32_to_i16:49; CHECK: ; %bb.0:50; CHECK-NEXT: s_cvt_i32_f32 s0, s051; CHECK-NEXT: ; return to shader part epilog52 %res = fptosi float %val to i1653 ret i16 %res54}55 56define amdgpu_vs i16 @fptoui_f32_to_u16(float inreg %val) {57; CHECK-LABEL: fptoui_f32_to_u16:58; CHECK: ; %bb.0:59; CHECK-NEXT: s_cvt_u32_f32 s0, s060; CHECK-NEXT: ; return to shader part epilog61 %res = fptoui float %val to i1662 ret i16 %res63}64 65define amdgpu_vs float @fpext_f16_to_f32(half inreg %val) {66; CHECK-LABEL: fpext_f16_to_f32:67; CHECK: ; %bb.0:68; CHECK-NEXT: s_cvt_f32_f16 s0, s069; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)70; CHECK-NEXT: v_mov_b32_e32 v0, s071; CHECK-NEXT: ; return to shader part epilog72 %res = fpext half %val to float73 ret float %res74}75 76define amdgpu_vs float @fpext_hif16_to_32(<2 x half> inreg %val) {77; CHECK-LABEL: fpext_hif16_to_32:78; CHECK: ; %bb.0:79; CHECK-NEXT: s_cvt_hi_f32_f16 s0, s080; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)81; CHECK-NEXT: v_mov_b32_e32 v0, s082; CHECK-NEXT: ; return to shader part epilog83 %hielt = extractelement <2 x half> %val, i32 184 %res = fpext half %hielt to float85 ret float %res86}87 88define amdgpu_vs half @fptrunc_f32_to_f16(float inreg %val) {89; CHECK-LABEL: fptrunc_f32_to_f16:90; CHECK: ; %bb.0:91; CHECK-NEXT: s_cvt_f16_f32 s0, s092; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)93; CHECK-NEXT: v_mov_b32_e32 v0, s094; CHECK-NEXT: ; return to shader part epilog95 %res = fptrunc float %val to half96 ret half %res97}98 99define amdgpu_vs float @fceil_f32(float inreg %val) {100; CHECK-LABEL: fceil_f32:101; CHECK: ; %bb.0:102; CHECK-NEXT: s_ceil_f32 s0, s0103; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)104; CHECK-NEXT: v_mov_b32_e32 v0, s0105; CHECK-NEXT: ; return to shader part epilog106 %res = call float @llvm.ceil.f32(float %val)107 ret float %res108}109 110define amdgpu_vs float @ffloor_f32(float inreg %val) {111; CHECK-LABEL: ffloor_f32:112; CHECK: ; %bb.0:113; CHECK-NEXT: s_floor_f32 s0, s0114; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)115; CHECK-NEXT: v_mov_b32_e32 v0, s0116; CHECK-NEXT: ; return to shader part epilog117 %res = call float @llvm.floor.f32(float %val)118 ret float %res119}120 121define amdgpu_vs float @ftrunc_f32(float inreg %val) {122; CHECK-LABEL: ftrunc_f32:123; CHECK: ; %bb.0:124; CHECK-NEXT: s_trunc_f32 s0, s0125; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)126; CHECK-NEXT: v_mov_b32_e32 v0, s0127; CHECK-NEXT: ; return to shader part epilog128 %res = call float @llvm.trunc.f32(float %val)129 ret float %res130}131 132define amdgpu_vs float @frint_f32(float inreg %val) {133; CHECK-LABEL: frint_f32:134; CHECK: ; %bb.0:135; CHECK-NEXT: s_rndne_f32 s0, s0136; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)137; CHECK-NEXT: v_mov_b32_e32 v0, s0138; CHECK-NEXT: ; return to shader part epilog139 %res = call float @llvm.rint.f32(float %val)140 ret float %res141}142 143define amdgpu_vs half @fceil_f16(half inreg %val) {144; CHECK-LABEL: fceil_f16:145; CHECK: ; %bb.0:146; CHECK-NEXT: s_ceil_f16 s0, s0147; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)148; CHECK-NEXT: v_mov_b32_e32 v0, s0149; CHECK-NEXT: ; return to shader part epilog150 %res = call half @llvm.ceil.f16(half %val)151 ret half %res152}153 154define amdgpu_vs half @ffloor_f16(half inreg %val) {155; CHECK-LABEL: ffloor_f16:156; CHECK: ; %bb.0:157; CHECK-NEXT: s_floor_f16 s0, s0158; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)159; CHECK-NEXT: v_mov_b32_e32 v0, s0160; CHECK-NEXT: ; return to shader part epilog161 %res = call half @llvm.floor.f16(half %val)162 ret half %res163}164 165define amdgpu_vs half @ftrunc_f16(half inreg %val) {166; CHECK-LABEL: ftrunc_f16:167; CHECK: ; %bb.0:168; CHECK-NEXT: s_trunc_f16 s0, s0169; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)170; CHECK-NEXT: v_mov_b32_e32 v0, s0171; CHECK-NEXT: ; return to shader part epilog172 %res = call half @llvm.trunc.f16(half %val)173 ret half %res174}175 176define amdgpu_vs half @frint_f16(half inreg %val) {177; CHECK-LABEL: frint_f16:178; CHECK: ; %bb.0:179; CHECK-NEXT: s_rndne_f16 s0, s0180; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)181; CHECK-NEXT: v_mov_b32_e32 v0, s0182; CHECK-NEXT: ; return to shader part epilog183 %res = call half @llvm.rint.f16(half %val)184 ret half %res185}186 187declare float @llvm.ceil.f32(float)188declare float @llvm.floor.f32(float)189declare float @llvm.trunc.f32(float)190declare float @llvm.rint.f32(float)191declare half @llvm.ceil.f16(half)192declare half @llvm.floor.f16(half)193declare half @llvm.trunc.f16(half)194declare half @llvm.rint.f16(half)195