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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mattr=-flat-for-global | FileCheck %s --check-prefix=SI3; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX89,VI4; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -| FileCheck %s --check-prefixes=GFX89,GFX95 6; XXX - Why the packing?7define amdgpu_kernel void @scalar_to_vector_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {8; SI-LABEL: scalar_to_vector_v2i32:9; SI: ; %bb.0:10; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x911; SI-NEXT: s_mov_b32 s7, 0xf00012; SI-NEXT: s_mov_b32 s6, -113; SI-NEXT: s_mov_b32 s10, s614; SI-NEXT: s_mov_b32 s11, s715; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: s_mov_b32 s8, s217; SI-NEXT: s_mov_b32 s9, s318; SI-NEXT: buffer_load_dword v0, off, s[8:11], 019; SI-NEXT: s_waitcnt vmcnt(0)20; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v021; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 1622; SI-NEXT: s_mov_b32 s4, s023; SI-NEXT: s_mov_b32 s5, s124; SI-NEXT: v_mov_b32_e32 v1, v025; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 026; SI-NEXT: s_endpgm27;28; VI-LABEL: scalar_to_vector_v2i32:29; VI: ; %bb.0:30; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2431; VI-NEXT: s_mov_b32 s7, 0xf00032; VI-NEXT: s_mov_b32 s6, -133; VI-NEXT: s_mov_b32 s10, s634; VI-NEXT: s_mov_b32 s11, s735; VI-NEXT: s_waitcnt lgkmcnt(0)36; VI-NEXT: s_mov_b32 s8, s237; VI-NEXT: s_mov_b32 s9, s338; VI-NEXT: buffer_load_dword v0, off, s[8:11], 039; VI-NEXT: s_mov_b32 s4, s040; VI-NEXT: s_mov_b32 s5, s141; VI-NEXT: s_waitcnt vmcnt(0)42; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v043; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]44; VI-NEXT: v_mov_b32_e32 v1, v045; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 046; VI-NEXT: s_endpgm47;48; GFX9-LABEL: scalar_to_vector_v2i32:49; GFX9: ; %bb.0:50; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2451; GFX9-NEXT: s_mov_b32 s7, 0xf00052; GFX9-NEXT: s_mov_b32 s6, -153; GFX9-NEXT: s_mov_b32 s10, s654; GFX9-NEXT: s_mov_b32 s11, s755; GFX9-NEXT: s_waitcnt lgkmcnt(0)56; GFX9-NEXT: s_mov_b32 s8, s257; GFX9-NEXT: s_mov_b32 s9, s358; GFX9-NEXT: buffer_load_dword v0, off, s[8:11], 059; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff000060; GFX9-NEXT: s_mov_b32 s4, s061; GFX9-NEXT: s_mov_b32 s5, s162; GFX9-NEXT: s_waitcnt vmcnt(0)63; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v064; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v165; GFX9-NEXT: v_mov_b32_e32 v1, v066; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 067; GFX9-NEXT: s_endpgm68 %tmp1 = load i32, ptr addrspace(1) %in, align 469 %bc = bitcast i32 %tmp1 to <2 x i16>70 %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>71 store <4 x i16> %tmp2, ptr addrspace(1) %out, align 872 ret void73}74 75define amdgpu_kernel void @scalar_to_vector_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {76; SI-LABEL: scalar_to_vector_v2f32:77; SI: ; %bb.0:78; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x979; SI-NEXT: s_mov_b32 s7, 0xf00080; SI-NEXT: s_mov_b32 s6, -181; SI-NEXT: s_mov_b32 s10, s682; SI-NEXT: s_mov_b32 s11, s783; SI-NEXT: s_waitcnt lgkmcnt(0)84; SI-NEXT: s_mov_b32 s8, s285; SI-NEXT: s_mov_b32 s9, s386; SI-NEXT: buffer_load_dword v0, off, s[8:11], 087; SI-NEXT: s_waitcnt vmcnt(0)88; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v089; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 1690; SI-NEXT: s_mov_b32 s4, s091; SI-NEXT: s_mov_b32 s5, s192; SI-NEXT: v_mov_b32_e32 v1, v093; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 094; SI-NEXT: s_endpgm95;96; VI-LABEL: scalar_to_vector_v2f32:97; VI: ; %bb.0:98; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2499; VI-NEXT: s_mov_b32 s7, 0xf000100; VI-NEXT: s_mov_b32 s6, -1101; VI-NEXT: s_mov_b32 s10, s6102; VI-NEXT: s_mov_b32 s11, s7103; VI-NEXT: s_waitcnt lgkmcnt(0)104; VI-NEXT: s_mov_b32 s8, s2105; VI-NEXT: s_mov_b32 s9, s3106; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0107; VI-NEXT: s_mov_b32 s4, s0108; VI-NEXT: s_mov_b32 s5, s1109; VI-NEXT: s_waitcnt vmcnt(0)110; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0111; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]112; VI-NEXT: v_mov_b32_e32 v1, v0113; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0114; VI-NEXT: s_endpgm115;116; GFX9-LABEL: scalar_to_vector_v2f32:117; GFX9: ; %bb.0:118; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24119; GFX9-NEXT: s_mov_b32 s7, 0xf000120; GFX9-NEXT: s_mov_b32 s6, -1121; GFX9-NEXT: s_mov_b32 s10, s6122; GFX9-NEXT: s_mov_b32 s11, s7123; GFX9-NEXT: s_waitcnt lgkmcnt(0)124; GFX9-NEXT: s_mov_b32 s8, s2125; GFX9-NEXT: s_mov_b32 s9, s3126; GFX9-NEXT: buffer_load_dword v0, off, s[8:11], 0127; GFX9-NEXT: v_mov_b32_e32 v2, 0xffff0000128; GFX9-NEXT: s_mov_b32 s4, s0129; GFX9-NEXT: s_mov_b32 s5, s1130; GFX9-NEXT: s_waitcnt vmcnt(0)131; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0132; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v1133; GFX9-NEXT: v_mov_b32_e32 v1, v0134; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0135; GFX9-NEXT: s_endpgm136 %tmp1 = load float, ptr addrspace(1) %in, align 4137 %bc = bitcast float %tmp1 to <2 x i16>138 %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>139 store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8140 ret void141}142 143define amdgpu_kernel void @scalar_to_vector_v4i16() {144; SI-LABEL: scalar_to_vector_v4i16:145; SI: ; %bb.0: ; %bb146; SI-NEXT: s_mov_b32 s3, 0xf000147; SI-NEXT: s_mov_b32 s2, -1148; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0149; SI-NEXT: s_waitcnt vmcnt(0)150; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0151; SI-NEXT: v_or_b32_e32 v2, v1, v0152; SI-NEXT: v_and_b32_e32 v1, 0xff00, v2153; SI-NEXT: v_or_b32_e32 v0, v0, v1154; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0155; SI-NEXT: v_or_b32_e32 v1, v0, v3156; SI-NEXT: v_or_b32_e32 v0, v2, v3157; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0158; SI-NEXT: s_endpgm159;160; VI-LABEL: scalar_to_vector_v4i16:161; VI: ; %bb.0: ; %bb162; VI-NEXT: s_mov_b32 s3, 0xf000163; VI-NEXT: s_mov_b32 s2, -1164; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0165; VI-NEXT: s_waitcnt vmcnt(0)166; VI-NEXT: v_readfirstlane_b32 s0, v0167; VI-NEXT: s_lshl_b32 s1, s0, 8168; VI-NEXT: s_or_b32 s0, s0, s1169; VI-NEXT: s_lshl_b32 s1, s0, 16170; VI-NEXT: s_and_b32 s0, s0, 0xffff171; VI-NEXT: s_or_b32 s0, s0, s1172; VI-NEXT: v_mov_b32_e32 v0, s0173; VI-NEXT: v_mov_b32_e32 v1, s0174; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0175; VI-NEXT: s_endpgm176;177; GFX9-LABEL: scalar_to_vector_v4i16:178; GFX9: ; %bb.0: ; %bb179; GFX9-NEXT: s_mov_b32 s3, 0xf000180; GFX9-NEXT: s_mov_b32 s2, -1181; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], 0182; GFX9-NEXT: s_waitcnt vmcnt(0)183; GFX9-NEXT: v_readfirstlane_b32 s0, v0184; GFX9-NEXT: s_lshl_b32 s1, s0, 8185; GFX9-NEXT: s_or_b32 s0, s0, s1186; GFX9-NEXT: s_and_b32 s1, s0, 0xffff187; GFX9-NEXT: s_lshl_b32 s0, s0, 16188; GFX9-NEXT: s_or_b32 s0, s1, s0189; GFX9-NEXT: v_mov_b32_e32 v0, s0190; GFX9-NEXT: v_mov_b32_e32 v1, s0191; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0192; GFX9-NEXT: s_endpgm193bb:194 %tmp = load <2 x i8>, ptr addrspace(1) poison, align 1195 %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>196 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> poison, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>197 store <8 x i8> %tmp2, ptr addrspace(1) poison, align 8198 ret void199}200 201define amdgpu_kernel void @scalar_to_vector_v4f16() {202; SI-LABEL: scalar_to_vector_v4f16:203; SI: ; %bb.0: ; %bb204; SI-NEXT: s_mov_b32 s3, 0xf000205; SI-NEXT: s_mov_b32 s2, -1206; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0207; SI-NEXT: s_waitcnt vmcnt(0)208; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0209; SI-NEXT: v_or_b32_e32 v2, v1, v0210; SI-NEXT: v_and_b32_e32 v1, 0xff00, v2211; SI-NEXT: v_or_b32_e32 v0, v0, v1212; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v0213; SI-NEXT: v_or_b32_e32 v1, v0, v3214; SI-NEXT: v_or_b32_e32 v0, v2, v3215; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0216; SI-NEXT: s_endpgm217;218; VI-LABEL: scalar_to_vector_v4f16:219; VI: ; %bb.0: ; %bb220; VI-NEXT: s_mov_b32 s3, 0xf000221; VI-NEXT: s_mov_b32 s2, -1222; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0223; VI-NEXT: s_waitcnt vmcnt(0)224; VI-NEXT: v_readfirstlane_b32 s0, v0225; VI-NEXT: s_lshl_b32 s1, s0, 8226; VI-NEXT: s_or_b32 s0, s1, s0227; VI-NEXT: s_and_b32 s1, s0, 0xff00228; VI-NEXT: s_bfe_u32 s4, s0, 0x80008229; VI-NEXT: s_or_b32 s1, s4, s1230; VI-NEXT: s_and_b32 s0, s0, 0xffff231; VI-NEXT: s_lshl_b32 s4, s1, 16232; VI-NEXT: s_and_b32 s1, s1, 0xffff233; VI-NEXT: s_or_b32 s1, s1, s4234; VI-NEXT: s_or_b32 s0, s0, s4235; VI-NEXT: v_mov_b32_e32 v0, s0236; VI-NEXT: v_mov_b32_e32 v1, s1237; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0238; VI-NEXT: s_endpgm239;240; GFX9-LABEL: scalar_to_vector_v4f16:241; GFX9: ; %bb.0: ; %bb242; GFX9-NEXT: s_mov_b32 s3, 0xf000243; GFX9-NEXT: s_mov_b32 s2, -1244; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], 0245; GFX9-NEXT: s_waitcnt vmcnt(0)246; GFX9-NEXT: v_readfirstlane_b32 s0, v0247; GFX9-NEXT: s_lshl_b32 s1, s0, 8248; GFX9-NEXT: s_or_b32 s0, s1, s0249; GFX9-NEXT: s_and_b32 s1, s0, 0xff00250; GFX9-NEXT: s_bfe_u32 s4, s0, 0x80008251; GFX9-NEXT: s_or_b32 s1, s4, s1252; GFX9-NEXT: s_and_b32 s0, s0, 0xffff253; GFX9-NEXT: s_and_b32 s4, s1, 0xffff254; GFX9-NEXT: s_lshl_b32 s1, s1, 16255; GFX9-NEXT: s_or_b32 s4, s4, s1256; GFX9-NEXT: s_or_b32 s0, s0, s1257; GFX9-NEXT: v_mov_b32_e32 v0, s0258; GFX9-NEXT: v_mov_b32_e32 v1, s4259; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0260; GFX9-NEXT: s_endpgm261bb:262 %load = load half, ptr addrspace(1) poison, align 1263 %tmp = bitcast half %load to <2 x i8>264 %tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>265 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> poison, <8 x i32> <i32 0, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>266 store <8 x i8> %tmp2, ptr addrspace(1) poison, align 8267 ret void268}269 270; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed271; to produce one, but for some reason never made it to selection.272 273 274; define amdgpu_kernel void @scalar_to_vector_test2(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {275; %tmp1 = load i32, ptr addrspace(1) %in, align 4276; %bc = bitcast i32 %tmp1 to <4 x i8>277 278; %tmp2 = shufflevector <4 x i8> %bc, <4 x i8> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>279; store <8 x i8> %tmp2, ptr addrspace(1) %out, align 4280; ret void281; }282 283; define amdgpu_kernel void @scalar_to_vector_test3(ptr addrspace(1) %out) nounwind {284; %newvec0 = insertelement <2 x i64> poison, i64 12345, i32 0285; %newvec1 = insertelement <2 x i64> %newvec0, i64 poison, i32 1286; %bc = bitcast <2 x i64> %newvec1 to <4 x i32>287; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4>288; store <4 x i32> %add, ptr addrspace(1) %out, align 16289; ret void290; }291 292; define amdgpu_kernel void @scalar_to_vector_test4(ptr addrspace(1) %out) nounwind {293; %newvec0 = insertelement <4 x i32> poison, i32 12345, i32 0294; %bc = bitcast <4 x i32> %newvec0 to <8 x i16>295; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>296; store <8 x i16> %add, ptr addrspace(1) %out, align 16297; ret void298; }299 300; define amdgpu_kernel void @scalar_to_vector_test5(ptr addrspace(1) %out) nounwind {301; %newvec0 = insertelement <2 x i32> poison, i32 12345, i32 0302; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>303; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>304; store <4 x i16> %add, ptr addrspace(1) %out, align 16305; ret void306; }307 308define amdgpu_kernel void @scalar_to_vector_test6(ptr addrspace(1) %out, i8 zeroext %val) nounwind {309; SI-LABEL: scalar_to_vector_test6:310; SI: ; %bb.0:311; SI-NEXT: s_load_dword s6, s[4:5], 0xb312; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9313; SI-NEXT: s_mov_b32 s3, 0xf000314; SI-NEXT: s_mov_b32 s2, -1315; SI-NEXT: s_waitcnt lgkmcnt(0)316; SI-NEXT: v_mov_b32_e32 v0, s6317; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0318; SI-NEXT: s_endpgm319;320; GFX89-LABEL: scalar_to_vector_test6:321; GFX89: ; %bb.0:322; GFX89-NEXT: s_load_dword s6, s[4:5], 0x2c323; GFX89-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24324; GFX89-NEXT: s_mov_b32 s3, 0xf000325; GFX89-NEXT: s_mov_b32 s2, -1326; GFX89-NEXT: s_waitcnt lgkmcnt(0)327; GFX89-NEXT: v_mov_b32_e32 v0, s6328; GFX89-NEXT: buffer_store_dword v0, off, s[0:3], 0329; GFX89-NEXT: s_endpgm330 %newvec0 = insertelement <4 x i8> poison, i8 %val, i32 0331 %bc = bitcast <4 x i8> %newvec0 to <2 x half>332 store <2 x half> %bc, ptr addrspace(1) %out333 ret void334}335 336; bitcast (scalar_to_vector x) -> any_extend x337define i64 @bitcast_combine_scalar_to_vector_v4i16(i16 %arg) {338; SI-LABEL: bitcast_combine_scalar_to_vector_v4i16:339; SI: ; %bb.0:340; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; SI-NEXT: v_and_b32_e32 v1, 0xffff, v0342; SI-NEXT: v_and_b32_e32 v2, 0xff00, v0343; SI-NEXT: v_bfe_u32 v0, v0, 8, 8344; SI-NEXT: v_or_b32_e32 v2, v0, v2345; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v2346; SI-NEXT: v_or_b32_e32 v0, v1, v3347; SI-NEXT: v_or_b32_e32 v1, v2, v3348; SI-NEXT: s_setpc_b64 s[30:31]349;350; GFX89-LABEL: bitcast_combine_scalar_to_vector_v4i16:351; GFX89: ; %bb.0:352; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)353; GFX89-NEXT: v_and_b32_e32 v1, 0xffffff00, v0354; GFX89-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD355; GFX89-NEXT: v_lshlrev_b32_e32 v2, 16, v1356; GFX89-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD357; GFX89-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD358; GFX89-NEXT: s_setpc_b64 s[30:31]359 %arg.cast = bitcast i16 %arg to <2 x i8>360 %tmp1 = shufflevector <2 x i8> %arg.cast, <2 x i8> poison, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>361 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> poison, <8 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>362 %cast = bitcast <8 x i8> %tmp2 to i64363 ret i64 %cast364}365