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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,SDAG %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GISEL %s4 5define amdgpu_ps float @global_load_b32_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {6; GCN-LABEL: global_load_b32_idxprom:7; GCN: ; %bb.0: ; %entry8; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GCN-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset10; GCN-NEXT: s_wait_loadcnt 0x011; GCN-NEXT: ; return to shader part epilog12entry:13 %idxprom = sext i32 %idx to i6414 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxprom15 %ret = load float, ptr addrspace(1) %arrayidx, align 416 ret float %ret17}18 19define amdgpu_ps float @global_load_b32_idx32(ptr addrspace(1) align 4 inreg %p, i32 %idx) {20; GCN-LABEL: global_load_b32_idx32:21; GCN: ; %bb.0: ; %entry22; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 123; GCN-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset24; GCN-NEXT: s_wait_loadcnt 0x025; GCN-NEXT: ; return to shader part epilog26entry:27 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i32 %idx28 %ret = load float, ptr addrspace(1) %arrayidx, align 429 ret float %ret30}31 32define amdgpu_ps float @global_load_b32_idxprom_wrong_stride(ptr addrspace(1) align 4 inreg %p, i32 %idx) {33; GCN-LABEL: global_load_b32_idxprom_wrong_stride:34; GCN: ; %bb.0: ; %entry35; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 136; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v037; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)38; GCN-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 3, s[0:1]39; GCN-NEXT: global_load_b32 v0, v[0:1], off40; GCN-NEXT: s_wait_loadcnt 0x041; GCN-NEXT: ; return to shader part epilog42entry:43 %idxprom = sext i32 %idx to i6444 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %p, i64 %idxprom45 %ret = load float, ptr addrspace(1) %arrayidx, align 446 ret float %ret47}48 49define amdgpu_ps float @global_load_b16_idxprom_ioffset(ptr addrspace(1) align 4 inreg %p, i32 %idx) {50; GCN-LABEL: global_load_b16_idxprom_ioffset:51; GCN: ; %bb.0: ; %entry52; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; GCN-NEXT: global_load_u16 v0, v0, s[0:1] offset:32 scale_offset54; GCN-NEXT: s_wait_loadcnt 0x055; GCN-NEXT: ; return to shader part epilog56entry:57 %idxprom = sext i32 %idx to i6458 %idxadd = add i64 %idxprom, 1659 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxadd60 %ld = load i16, ptr addrspace(1) %arrayidx, align 261 %ret.i32 = zext i16 %ld to i3262 %ret = bitcast i32 %ret.i32 to float63 ret float %ret64}65 66define amdgpu_ps <2 x float> @global_load_b64_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {67; GCN-LABEL: global_load_b64_idxprom:68; GCN: ; %bb.0: ; %entry69; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 170; GCN-NEXT: global_load_b64 v[0:1], v0, s[0:1] scale_offset71; GCN-NEXT: s_wait_loadcnt 0x072; GCN-NEXT: ; return to shader part epilog73entry:74 %idxprom = sext i32 %idx to i6475 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %p, i64 %idxprom76 %ret = load <2 x float>, ptr addrspace(1) %arrayidx, align 477 ret <2 x float> %ret78}79 80define amdgpu_ps <3 x float> @global_load_b96_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {81; GCN-LABEL: global_load_b96_idxprom:82; GCN: ; %bb.0: ; %entry83; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 184; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] scale_offset85; GCN-NEXT: s_wait_loadcnt 0x086; GCN-NEXT: ; return to shader part epilog87entry:88 %idxprom = sext i32 %idx to i6489 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxprom90 %ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 491 ret <3 x float> %ret92}93 94define amdgpu_ps <3 x float> @global_load_b96_idxpromi_ioffset(ptr addrspace(1) align 4 inreg %p, i32 %idx) {95; GCN-LABEL: global_load_b96_idxpromi_ioffset:96; GCN: ; %bb.0: ; %entry97; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 198; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:192 scale_offset99; GCN-NEXT: s_wait_loadcnt 0x0100; GCN-NEXT: ; return to shader part epilog101entry:102 %idxprom = sext i32 %idx to i64103 %idxadd = add i64 %idxprom, 16104 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxadd105 %ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4106 ret <3 x float> %ret107}108 109define amdgpu_ps <4 x float> @global_load_b128_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {110; GCN-LABEL: global_load_b128_idxprom:111; GCN: ; %bb.0: ; %entry112; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1113; GCN-NEXT: global_load_b128 v[0:3], v0, s[0:1] scale_offset114; GCN-NEXT: s_wait_loadcnt 0x0115; GCN-NEXT: ; return to shader part epilog116entry:117 %idxprom = sext i32 %idx to i64118 %arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(1) %p, i64 %idxprom119 %ret = load <4 x float>, ptr addrspace(1) %arrayidx, align 4120 ret <4 x float> %ret121}122 123define amdgpu_ps float @global_load_b32_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {124; GCN-LABEL: global_load_b32_idxprom_range:125; GCN: ; %bb.0: ; %entry126; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1127; GCN-NEXT: global_load_b32 v0, v[0:1], off128; GCN-NEXT: s_wait_loadcnt 0x0129; GCN-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset130; GCN-NEXT: s_wait_loadcnt 0x0131; GCN-NEXT: ; return to shader part epilog132entry:133 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0134 %idxprom = sext i32 %idx to i64135 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxprom136 %ret = load float, ptr addrspace(1) %arrayidx, align 4137 ret float %ret138}139 140define amdgpu_ps float @global_load_b32_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {141; GCN-LABEL: global_load_b32_idxprom_range_ioffset:142; GCN: ; %bb.0: ; %entry143; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1144; GCN-NEXT: global_load_b32 v0, v[0:1], off145; GCN-NEXT: s_wait_loadcnt 0x0146; GCN-NEXT: global_load_b32 v0, v0, s[0:1] offset:64 scale_offset147; GCN-NEXT: s_wait_loadcnt 0x0148; GCN-NEXT: ; return to shader part epilog149entry:150 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0151 %idxprom = sext i32 %idx to i64152 %idxadd = add i64 %idxprom, 16153 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxadd154 %ret = load float, ptr addrspace(1) %arrayidx, align 4155 ret float %ret156}157 158; Note: this is a byte load, there is nothing to scale159 160define amdgpu_ps float @global_load_b8_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {161; GCN-LABEL: global_load_b8_idxprom_range_ioffset:162; GCN: ; %bb.0: ; %entry163; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1164; GCN-NEXT: global_load_b32 v0, v[0:1], off165; GCN-NEXT: s_wait_loadcnt 0x0166; GCN-NEXT: global_load_u8 v0, v0, s[0:1] offset:16167; GCN-NEXT: s_wait_loadcnt 0x0168; GCN-NEXT: ; return to shader part epilog169entry:170 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0171 %idxprom = sext i32 %idx to i64172 %idxadd = add i64 %idxprom, 16173 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %p, i64 %idxadd174 %ld = load i8, ptr addrspace(1) %arrayidx175 %ret.i32 = zext i8 %ld to i32176 %ret = bitcast i32 %ret.i32 to float177 ret float %ret178}179 180define amdgpu_ps float @global_load_b16_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {181; GCN-LABEL: global_load_b16_idxprom_range:182; GCN: ; %bb.0: ; %entry183; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1184; GCN-NEXT: global_load_b32 v0, v[0:1], off185; GCN-NEXT: s_wait_loadcnt 0x0186; GCN-NEXT: global_load_u16 v0, v0, s[0:1] scale_offset187; GCN-NEXT: s_wait_loadcnt 0x0188; GCN-NEXT: ; return to shader part epilog189entry:190 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0191 %idxprom = sext i32 %idx to i64192 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxprom193 %ld = load i16, ptr addrspace(1) %arrayidx, align 2194 %ret.i32 = zext i16 %ld to i32195 %ret = bitcast i32 %ret.i32 to float196 ret float %ret197}198 199define amdgpu_ps float @global_load_b16_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {200; GCN-LABEL: global_load_b16_idxprom_range_ioffset:201; GCN: ; %bb.0: ; %entry202; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1203; GCN-NEXT: global_load_b32 v0, v[0:1], off204; GCN-NEXT: s_wait_loadcnt 0x0205; GCN-NEXT: global_load_u16 v0, v0, s[0:1] offset:32 scale_offset206; GCN-NEXT: s_wait_loadcnt 0x0207; GCN-NEXT: ; return to shader part epilog208entry:209 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0210 %idxprom = sext i32 %idx to i64211 %idxadd = add i64 %idxprom, 16212 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxadd213 %ld = load i16, ptr addrspace(1) %arrayidx, align 2214 %ret.i32 = zext i16 %ld to i32215 %ret = bitcast i32 %ret.i32 to float216 ret float %ret217}218 219define amdgpu_ps <2 x float> @global_load_b64_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {220; GCN-LABEL: global_load_b64_idxprom_range:221; GCN: ; %bb.0: ; %entry222; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1223; GCN-NEXT: global_load_b32 v0, v[0:1], off224; GCN-NEXT: s_wait_loadcnt 0x0225; GCN-NEXT: global_load_b64 v[0:1], v0, s[0:1] scale_offset226; GCN-NEXT: s_wait_loadcnt 0x0227; GCN-NEXT: ; return to shader part epilog228entry:229 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0230 %idxprom = sext i32 %idx to i64231 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(1) %p, i64 %idxprom232 %ret = load <2 x float>, ptr addrspace(1) %arrayidx, align 4233 ret <2 x float> %ret234}235 236define amdgpu_ps <3 x float> @global_load_b96_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {237; GCN-LABEL: global_load_b96_idxprom_range:238; GCN: ; %bb.0: ; %entry239; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1240; GCN-NEXT: global_load_b32 v0, v[0:1], off241; GCN-NEXT: s_wait_loadcnt 0x0242; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] scale_offset243; GCN-NEXT: s_wait_loadcnt 0x0244; GCN-NEXT: ; return to shader part epilog245entry:246 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0247 %idxprom = sext i32 %idx to i64248 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxprom249 %ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4250 ret <3 x float> %ret251}252 253define amdgpu_ps <3 x float> @global_load_b96_idxprom_range_ioffset(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {254; GCN-LABEL: global_load_b96_idxprom_range_ioffset:255; GCN: ; %bb.0: ; %entry256; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1257; GCN-NEXT: global_load_b32 v0, v[0:1], off258; GCN-NEXT: s_wait_loadcnt 0x0259; GCN-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:192 scale_offset260; GCN-NEXT: s_wait_loadcnt 0x0261; GCN-NEXT: ; return to shader part epilog262entry:263 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0264 %idxprom = sext i32 %idx to i64265 %idxadd = add i64 %idxprom, 16266 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(1) %p, i64 %idxadd267 %ret = load <3 x float>, ptr addrspace(1) %arrayidx, align 4268 ret <3 x float> %ret269}270 271define amdgpu_ps <4 x float> @global_load_b128_idxprom_range(ptr addrspace(1) align 4 inreg %p, ptr addrspace(1) align 4 %pp) {272; GCN-LABEL: global_load_b128_idxprom_range:273; GCN: ; %bb.0: ; %entry274; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1275; GCN-NEXT: global_load_b32 v0, v[0:1], off276; GCN-NEXT: s_wait_loadcnt 0x0277; GCN-NEXT: global_load_b128 v[0:3], v0, s[0:1] scale_offset278; GCN-NEXT: s_wait_loadcnt 0x0279; GCN-NEXT: ; return to shader part epilog280entry:281 %idx = load i32, ptr addrspace(1) %pp, align 4, !range !0282 %idxprom = sext i32 %idx to i64283 %arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(1) %p, i64 %idxprom284 %ret = load <4 x float>, ptr addrspace(1) %arrayidx, align 4285 ret <4 x float> %ret286}287 288define amdgpu_ps void @global_store_b32_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {289; GCN-LABEL: global_store_b32_idxprom:290; GCN: ; %bb.0: ; %entry291; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1292; GCN-NEXT: v_mov_b32_e32 v1, 1.0293; GCN-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset294; GCN-NEXT: s_endpgm295entry:296 %idxprom = sext i32 %idx to i64297 %arrayidx = getelementptr inbounds float, ptr addrspace(1) %p, i64 %idxprom298 store float 1.0, ptr addrspace(1) %arrayidx, align 4299 ret void300}301 302define amdgpu_ps void @global_store_b16_idxprom(ptr addrspace(1) align 2 inreg %p, i32 %idx) {303; GCN-LABEL: global_store_b16_idxprom:304; GCN: ; %bb.0: ; %entry305; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1306; GCN-NEXT: v_mov_b32_e32 v1, 1307; GCN-NEXT: global_store_b16 v0, v1, s[0:1] scale_offset308; GCN-NEXT: s_endpgm309entry:310 %idxprom = sext i32 %idx to i64311 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %p, i64 %idxprom312 store i16 1, ptr addrspace(1) %arrayidx, align 2313 ret void314}315 316define amdgpu_ps void @global_store_b64_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {317; GCN-LABEL: global_store_b64_idxprom:318; GCN: ; %bb.0: ; %entry319; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1320; GCN-NEXT: v_mov_b64_e32 v[2:3], 1.0321; GCN-NEXT: global_store_b64 v0, v[2:3], s[0:1] scale_offset322; GCN-NEXT: s_endpgm323entry:324 %idxprom = sext i32 %idx to i64325 %arrayidx = getelementptr inbounds double, ptr addrspace(1) %p, i64 %idxprom326 store double 1.0, ptr addrspace(1) %arrayidx, align 4327 ret void328}329 330define amdgpu_ps void @global_atomicrmw_b32_idxprom(ptr addrspace(1) align 4 inreg %p, i32 %idx) {331; GCN-LABEL: global_atomicrmw_b32_idxprom:332; GCN: ; %bb.0: ; %entry333; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1334; GCN-NEXT: v_mov_b32_e32 v1, 1335; GCN-NEXT: global_atomic_add_u32 v0, v1, s[0:1] scale_offset scope:SCOPE_SYS336; GCN-NEXT: s_endpgm337entry:338 %idxprom = sext i32 %idx to i64339 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %p, i64 %idxprom340 atomicrmw add ptr addrspace(1) %arrayidx, i32 1 monotonic341 ret void342}343 344define amdgpu_ps <2 x float> @global_atomicrmw_b64_rtn_idxprom(ptr addrspace(1) align 8 inreg %p, i32 %idx) {345; GCN-LABEL: global_atomicrmw_b64_rtn_idxprom:346; GCN: ; %bb.0: ; %entry347; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1348; GCN-NEXT: v_mov_b64_e32 v[2:3], 1349; GCN-NEXT: global_atomic_add_u64 v[0:1], v0, v[2:3], s[0:1] scale_offset th:TH_ATOMIC_RETURN scope:SCOPE_SYS350; GCN-NEXT: s_wait_loadcnt 0x0351; GCN-NEXT: ; return to shader part epilog352entry:353 %idxprom = sext i32 %idx to i64354 %arrayidx = getelementptr inbounds i64, ptr addrspace(1) %p, i64 %idxprom355 %ret = atomicrmw add ptr addrspace(1) %arrayidx, i64 1 monotonic356 %ret.cast = bitcast i64 %ret to <2 x float>357 ret <2 x float> %ret.cast358}359 360!0 = !{i32 0, i32 1024}361;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:362; GISEL: {{.*}}363; SDAG: {{.*}}364