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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s4 5define amdgpu_ps float @scratch_load_b32_alloca_idxprom(i32 %idx) {6; GCN-LABEL: scratch_load_b32_alloca_idxprom:7; GCN: ; %bb.0: ; %entry8; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GCN-NEXT: scratch_load_b32 v0, v0, off scale_offset10; GCN-NEXT: s_wait_loadcnt 0x011; GCN-NEXT: ; return to shader part epilog12entry:13 %p = alloca [64 x i32], align 4, addrspace(5)14 %idxprom = zext i32 %idx to i6415 %arrayidx = getelementptr inbounds float, ptr addrspace(5) %p, i64 %idxprom16 %ret = load float, ptr addrspace(5) %arrayidx, align 417 ret float %ret18}19 20define amdgpu_ps float @scratch_load_b32_idxprom(ptr addrspace(5) align 4 inreg %p, i32 %idx) {21; GCN-LABEL: scratch_load_b32_idxprom:22; GCN: ; %bb.0: ; %entry23; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 124; GCN-NEXT: scratch_load_b32 v0, v0, s0 scale_offset25; GCN-NEXT: s_wait_loadcnt 0x026; GCN-NEXT: ; return to shader part epilog27entry:28 %idxprom = sext i32 %idx to i6429 %arrayidx = getelementptr inbounds float, ptr addrspace(5) %p, i64 %idxprom30 %ret = load float, ptr addrspace(5) %arrayidx, align 431 ret float %ret32}33 34define amdgpu_ps float @scratch_load_b32_idx32(ptr addrspace(5) align 4 inreg %p, i32 %idx) {35; GCN-LABEL: scratch_load_b32_idx32:36; GCN: ; %bb.0: ; %entry37; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 138; GCN-NEXT: scratch_load_b32 v0, v0, s0 scale_offset39; GCN-NEXT: s_wait_loadcnt 0x040; GCN-NEXT: ; return to shader part epilog41entry:42 %arrayidx = getelementptr inbounds float, ptr addrspace(5) %p, i32 %idx43 %ret = load float, ptr addrspace(5) %arrayidx, align 444 ret float %ret45}46 47define amdgpu_ps float @scratch_load_b32_idxprom_wrong_stride(ptr addrspace(5) align 4 inreg %p, i32 %idx) {48; GCN-LABEL: scratch_load_b32_idxprom_wrong_stride:49; GCN: ; %bb.0: ; %entry50; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 151; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v052; GCN-NEXT: scratch_load_b32 v0, v0, s053; GCN-NEXT: s_wait_loadcnt 0x054; GCN-NEXT: ; return to shader part epilog55entry:56 %idxprom = zext i32 %idx to i6457 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(5) %p, i64 %idxprom58 %ret = load float, ptr addrspace(5) %arrayidx, align 459 ret float %ret60}61 62define amdgpu_ps float @scratch_load_b16_idxprom_ioffset(ptr addrspace(5) align 4 inreg %p, i32 %idx) {63; GCN-LABEL: scratch_load_b16_idxprom_ioffset:64; GCN: ; %bb.0: ; %entry65; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 166; GCN-NEXT: scratch_load_u16 v0, v0, s0 offset:32 scale_offset67; GCN-NEXT: s_wait_loadcnt 0x068; GCN-NEXT: ; return to shader part epilog69entry:70 %idxprom = sext i32 %idx to i6471 %idxadd = add i64 %idxprom, 1672 %arrayidx = getelementptr inbounds i16, ptr addrspace(5) %p, i64 %idxadd73 %ld = load i16, ptr addrspace(5) %arrayidx, align 274 %ret.i32 = zext i16 %ld to i3275 %ret = bitcast i32 %ret.i32 to float76 ret float %ret77}78 79define amdgpu_ps <2 x float> @scratch_load_b64_idxprom(ptr addrspace(5) align 4 inreg %p, i32 %idx) {80; GCN-LABEL: scratch_load_b64_idxprom:81; GCN: ; %bb.0: ; %entry82; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 183; GCN-NEXT: scratch_load_b64 v[0:1], v0, s0 scale_offset84; GCN-NEXT: s_wait_loadcnt 0x085; GCN-NEXT: ; return to shader part epilog86entry:87 %idxprom = zext i32 %idx to i6488 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(5) %p, i64 %idxprom89 %ret = load <2 x float>, ptr addrspace(5) %arrayidx, align 490 ret <2 x float> %ret91}92 93define amdgpu_ps <3 x float> @scratch_load_b96_idxprom(ptr addrspace(5) align 4 inreg %p, i32 %idx) {94; GCN-LABEL: scratch_load_b96_idxprom:95; GCN: ; %bb.0: ; %entry96; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 197; GCN-NEXT: scratch_load_b96 v[0:2], v0, s0 scale_offset98; GCN-NEXT: s_wait_loadcnt 0x099; GCN-NEXT: ; return to shader part epilog100entry:101 %idxprom = zext i32 %idx to i64102 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(5) %p, i64 %idxprom103 %ret = load <3 x float>, ptr addrspace(5) %arrayidx, align 4104 ret <3 x float> %ret105}106 107define amdgpu_ps <3 x float> @scratch_load_b96_idxpromi_ioffset(ptr addrspace(5) align 4 inreg %p, i32 %idx) {108; GCN-LABEL: scratch_load_b96_idxpromi_ioffset:109; GCN: ; %bb.0: ; %entry110; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1111; GCN-NEXT: scratch_load_b96 v[0:2], v0, s0 offset:192 scale_offset112; GCN-NEXT: s_wait_loadcnt 0x0113; GCN-NEXT: ; return to shader part epilog114entry:115 %idxprom = zext i32 %idx to i64116 %idxadd = add i64 %idxprom, 16117 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(5) %p, i64 %idxadd118 %ret = load <3 x float>, ptr addrspace(5) %arrayidx, align 4119 ret <3 x float> %ret120}121 122define amdgpu_ps <4 x float> @scratch_load_b128_idxprom(ptr addrspace(5) align 4 inreg %p, i32 %idx) {123; GCN-LABEL: scratch_load_b128_idxprom:124; GCN: ; %bb.0: ; %entry125; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1126; GCN-NEXT: scratch_load_b128 v[0:3], v0, s0 scale_offset127; GCN-NEXT: s_wait_loadcnt 0x0128; GCN-NEXT: ; return to shader part epilog129entry:130 %idxprom = zext i32 %idx to i64131 %arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(5) %p, i64 %idxprom132 %ret = load <4 x float>, ptr addrspace(5) %arrayidx, align 4133 ret <4 x float> %ret134}135 136define amdgpu_ps float @scratch_load_b32_idxprom_range(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {137; GCN-LABEL: scratch_load_b32_idxprom_range:138; GCN: ; %bb.0: ; %entry139; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1140; GCN-NEXT: scratch_load_b32 v0, v0, off141; GCN-NEXT: s_wait_loadcnt 0x0142; GCN-NEXT: scratch_load_b32 v0, v0, s0 scale_offset143; GCN-NEXT: s_wait_loadcnt 0x0144; GCN-NEXT: ; return to shader part epilog145entry:146 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0147 %idxprom = zext i32 %idx to i64148 %arrayidx = getelementptr inbounds float, ptr addrspace(5) %p, i64 %idxprom149 %ret = load float, ptr addrspace(5) %arrayidx, align 4150 ret float %ret151}152 153define amdgpu_ps float @scratch_load_b32_idxprom_range_ioffset(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {154; GCN-LABEL: scratch_load_b32_idxprom_range_ioffset:155; GCN: ; %bb.0: ; %entry156; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1157; GCN-NEXT: scratch_load_b32 v0, v0, off158; GCN-NEXT: s_wait_loadcnt 0x0159; GCN-NEXT: scratch_load_b32 v0, v0, s0 offset:64 scale_offset160; GCN-NEXT: s_wait_loadcnt 0x0161; GCN-NEXT: ; return to shader part epilog162entry:163 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0164 %idxprom = zext i32 %idx to i64165 %idxadd = add i64 %idxprom, 16166 %arrayidx = getelementptr inbounds float, ptr addrspace(5) %p, i64 %idxadd167 %ret = load float, ptr addrspace(5) %arrayidx, align 4168 ret float %ret169}170 171define amdgpu_ps float @scratch_load_b8_idxprom_range_ioffset(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {172; GCN-LABEL: scratch_load_b8_idxprom_range_ioffset:173; GCN: ; %bb.0: ; %entry174; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1175; GCN-NEXT: scratch_load_b32 v0, v0, off176; GCN-NEXT: s_wait_loadcnt 0x0177; GCN-NEXT: scratch_load_u8 v0, v0, s0 offset:16178; GCN-NEXT: s_wait_loadcnt 0x0179; GCN-NEXT: ; return to shader part epilog180entry:181 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0182 %idxprom = zext i32 %idx to i64183 %idxadd = add i64 %idxprom, 16184 %arrayidx = getelementptr inbounds i8, ptr addrspace(5) %p, i64 %idxadd185 %ld = load i8, ptr addrspace(5) %arrayidx186 %ret.i32 = zext i8 %ld to i32187 %ret = bitcast i32 %ret.i32 to float188 ret float %ret189}190 191define amdgpu_ps float @scratch_load_b16_idxprom_range(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {192; GCN-LABEL: scratch_load_b16_idxprom_range:193; GCN: ; %bb.0: ; %entry194; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1195; GCN-NEXT: scratch_load_b32 v0, v0, off196; GCN-NEXT: s_wait_loadcnt 0x0197; GCN-NEXT: scratch_load_u16 v0, v0, s0 scale_offset198; GCN-NEXT: s_wait_loadcnt 0x0199; GCN-NEXT: ; return to shader part epilog200entry:201 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0202 %idxprom = zext i32 %idx to i64203 %arrayidx = getelementptr inbounds i16, ptr addrspace(5) %p, i64 %idxprom204 %ld = load i16, ptr addrspace(5) %arrayidx, align 2205 %ret.i32 = zext i16 %ld to i32206 %ret = bitcast i32 %ret.i32 to float207 ret float %ret208}209 210define amdgpu_ps float @scratch_load_b16_idxprom_range_ioffset(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {211; GCN-LABEL: scratch_load_b16_idxprom_range_ioffset:212; GCN: ; %bb.0: ; %entry213; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1214; GCN-NEXT: scratch_load_b32 v0, v0, off215; GCN-NEXT: s_wait_loadcnt 0x0216; GCN-NEXT: scratch_load_u16 v0, v0, s0 offset:32 scale_offset217; GCN-NEXT: s_wait_loadcnt 0x0218; GCN-NEXT: ; return to shader part epilog219entry:220 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0221 %idxprom = zext i32 %idx to i64222 %idxadd = add i64 %idxprom, 16223 %arrayidx = getelementptr inbounds i16, ptr addrspace(5) %p, i64 %idxadd224 %ld = load i16, ptr addrspace(5) %arrayidx, align 2225 %ret.i32 = zext i16 %ld to i32226 %ret = bitcast i32 %ret.i32 to float227 ret float %ret228}229 230define amdgpu_ps <2 x float> @scratch_load_b64_idxprom_range(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {231; GCN-LABEL: scratch_load_b64_idxprom_range:232; GCN: ; %bb.0: ; %entry233; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1234; GCN-NEXT: scratch_load_b32 v0, v0, off235; GCN-NEXT: s_wait_loadcnt 0x0236; GCN-NEXT: scratch_load_b64 v[0:1], v0, s0 scale_offset237; GCN-NEXT: s_wait_loadcnt 0x0238; GCN-NEXT: ; return to shader part epilog239entry:240 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0241 %idxprom = zext i32 %idx to i64242 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(5) %p, i64 %idxprom243 %ret = load <2 x float>, ptr addrspace(5) %arrayidx, align 4244 ret <2 x float> %ret245}246 247; Multiplication is unsigned here, so we cannot match it.248 249define amdgpu_ps <3 x float> @scratch_load_b96_idxprom_range(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {250; GCN-LABEL: scratch_load_b96_idxprom_range:251; GCN: ; %bb.0: ; %entry252; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1253; GCN-NEXT: scratch_load_b32 v0, v0, off254; GCN-NEXT: s_wait_loadcnt 0x0255; GCN-NEXT: scratch_load_b96 v[0:2], v0, s0 scale_offset256; GCN-NEXT: s_wait_loadcnt 0x0257; GCN-NEXT: ; return to shader part epilog258entry:259 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0260 %idxprom = sext i32 %idx to i64261 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(5) %p, i64 %idxprom262 %ret = load <3 x float>, ptr addrspace(5) %arrayidx, align 4263 ret <3 x float> %ret264}265 266define amdgpu_ps <3 x float> @scratch_load_b96_idxprom_range_ioffset(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {267; GCN-LABEL: scratch_load_b96_idxprom_range_ioffset:268; GCN: ; %bb.0: ; %entry269; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1270; GCN-NEXT: scratch_load_b32 v0, v0, off271; GCN-NEXT: s_wait_loadcnt 0x0272; GCN-NEXT: scratch_load_b96 v[0:2], v0, s0 offset:192 scale_offset273; GCN-NEXT: s_wait_loadcnt 0x0274; GCN-NEXT: ; return to shader part epilog275entry:276 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0277 %idxprom = sext i32 %idx to i64278 %idxadd = add i64 %idxprom, 16279 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(5) %p, i64 %idxadd280 %ret = load <3 x float>, ptr addrspace(5) %arrayidx, align 4281 ret <3 x float> %ret282}283 284define amdgpu_ps <4 x float> @scratch_load_b128_idxprom_range(ptr addrspace(5) align 4 inreg %p, ptr addrspace(5) align 4 %pp) {285; GCN-LABEL: scratch_load_b128_idxprom_range:286; GCN: ; %bb.0: ; %entry287; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1288; GCN-NEXT: scratch_load_b32 v0, v0, off289; GCN-NEXT: s_wait_loadcnt 0x0290; GCN-NEXT: scratch_load_b128 v[0:3], v0, s0 scale_offset291; GCN-NEXT: s_wait_loadcnt 0x0292; GCN-NEXT: ; return to shader part epilog293entry:294 %idx = load i32, ptr addrspace(5) %pp, align 4, !range !0295 %idxprom = zext i32 %idx to i64296 %arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(5) %p, i64 %idxprom297 %ret = load <4 x float>, ptr addrspace(5) %arrayidx, align 4298 ret <4 x float> %ret299}300 301define amdgpu_ps void @scratch_store_b32_idxprom(ptr addrspace(5) align 4 inreg %p, i32 %idx) {302; GCN-LABEL: scratch_store_b32_idxprom:303; GCN: ; %bb.0: ; %entry304; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1305; GCN-NEXT: v_mov_b32_e32 v1, 1.0306; GCN-NEXT: scratch_store_b32 v0, v1, s0 scale_offset307; GCN-NEXT: s_endpgm308entry:309 %idxprom = zext i32 %idx to i64310 %arrayidx = getelementptr inbounds float, ptr addrspace(5) %p, i64 %idxprom311 store float 1.0, ptr addrspace(5) %arrayidx, align 4312 ret void313}314 315define amdgpu_ps void @scratch_store_b16_idxprom(ptr addrspace(5) align 2 inreg %p, i32 %idx) {316; GCN-LABEL: scratch_store_b16_idxprom:317; GCN: ; %bb.0: ; %entry318; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1319; GCN-NEXT: v_mov_b32_e32 v1, 1320; GCN-NEXT: scratch_store_b16 v0, v1, s0 scale_offset321; GCN-NEXT: s_endpgm322entry:323 %idxprom = zext i32 %idx to i64324 %arrayidx = getelementptr inbounds i16, ptr addrspace(5) %p, i64 %idxprom325 store i16 1, ptr addrspace(5) %arrayidx, align 2326 ret void327}328 329define amdgpu_ps void @scratch_store_b64_idxprom(ptr addrspace(5) align 4 inreg %p, i32 %idx) {330; GCN-LABEL: scratch_store_b64_idxprom:331; GCN: ; %bb.0: ; %entry332; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1333; GCN-NEXT: v_mov_b64_e32 v[2:3], 1.0334; GCN-NEXT: scratch_store_b64 v0, v[2:3], s0 scale_offset335; GCN-NEXT: s_endpgm336entry:337 %idxprom = zext i32 %idx to i64338 %arrayidx = getelementptr inbounds double, ptr addrspace(5) %p, i64 %idxprom339 store double 1.0, ptr addrspace(5) %arrayidx, align 4340 ret void341}342 343!0 = !{i32 0, i32 1024}344