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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,SDAG %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GISEL %s4 5define amdgpu_ps float @s_load_b32_idxprom(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {6; GCN-LABEL: s_load_b32_idxprom:7; GCN: ; %bb.0: ; %entry8; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GCN-NEXT: s_load_b32 s0, s[0:1], s2 offset:0x0 scale_offset10; GCN-NEXT: s_wait_kmcnt 0x011; GCN-NEXT: v_mov_b32_e32 v0, s012; GCN-NEXT: ; return to shader part epilog13entry:14 %idxprom = zext i32 %idx to i6415 %arrayidx = getelementptr inbounds float, ptr addrspace(4) %p, i64 %idxprom16 %ret = load float, ptr addrspace(4) %arrayidx, align 417 ret float %ret18}19 20; 'i32 %idx' is a signed index while SMRD soffset is unsigned, thus it is not selected.21 22define amdgpu_ps float @s_load_b32_idx32(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {23; SDAG-LABEL: s_load_b32_idx32:24; SDAG: ; %bb.0: ; %entry25; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 126; SDAG-NEXT: s_ashr_i32 s3, s2, 3127; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)28; SDAG-NEXT: s_lshl_b64 s[2:3], s[2:3], 229; SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]30; SDAG-NEXT: s_load_b32 s0, s[0:1], 0x031; SDAG-NEXT: s_wait_kmcnt 0x032; SDAG-NEXT: v_mov_b32_e32 v0, s033; SDAG-NEXT: ; return to shader part epilog34;35; GISEL-LABEL: s_load_b32_idx32:36; GISEL: ; %bb.0: ; %entry37; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 138; GISEL-NEXT: s_ashr_i32 s3, s2, 3139; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)40; GISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 241; GISEL-NEXT: s_add_co_u32 s0, s0, s242; GISEL-NEXT: s_add_co_ci_u32 s1, s1, s343; GISEL-NEXT: s_load_b32 s0, s[0:1], 0x044; GISEL-NEXT: s_wait_kmcnt 0x045; GISEL-NEXT: v_mov_b32_e32 v0, s046; GISEL-NEXT: ; return to shader part epilog47entry:48 %arrayidx = getelementptr inbounds float, ptr addrspace(4) %p, i32 %idx49 %ret = load float, ptr addrspace(4) %arrayidx, align 450 ret float %ret51}52 53define amdgpu_ps float @s_load_b32_idxprom_wrong_stride(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {54; SDAG-LABEL: s_load_b32_idxprom_wrong_stride:55; SDAG: ; %bb.0: ; %entry56; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 157; SDAG-NEXT: s_mov_b32 s3, 058; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)59; SDAG-NEXT: s_lshl_b64 s[2:3], s[2:3], 360; SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]61; SDAG-NEXT: s_load_b32 s0, s[0:1], 0x062; SDAG-NEXT: s_wait_kmcnt 0x063; SDAG-NEXT: v_mov_b32_e32 v0, s064; SDAG-NEXT: ; return to shader part epilog65;66; GISEL-LABEL: s_load_b32_idxprom_wrong_stride:67; GISEL: ; %bb.0: ; %entry68; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 169; GISEL-NEXT: s_mov_b32 s3, 070; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)71; GISEL-NEXT: s_lshl_b64 s[2:3], s[2:3], 372; GISEL-NEXT: s_add_co_u32 s0, s0, s273; GISEL-NEXT: s_add_co_ci_u32 s1, s1, s374; GISEL-NEXT: s_load_b32 s0, s[0:1], 0x075; GISEL-NEXT: s_wait_kmcnt 0x076; GISEL-NEXT: v_mov_b32_e32 v0, s077; GISEL-NEXT: ; return to shader part epilog78entry:79 %idxprom = zext i32 %idx to i6480 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(4) %p, i64 %idxprom81 %ret = load float, ptr addrspace(4) %arrayidx, align 482 ret float %ret83}84 85define amdgpu_ps float @s_load_b16_idxprom_ioffset(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {86; GCN-LABEL: s_load_b16_idxprom_ioffset:87; GCN: ; %bb.0: ; %entry88; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 189; GCN-NEXT: s_load_u16 s0, s[0:1], s2 offset:0x20 scale_offset90; GCN-NEXT: s_wait_kmcnt 0x091; GCN-NEXT: v_mov_b32_e32 v0, s092; GCN-NEXT: ; return to shader part epilog93entry:94 %idxprom = zext i32 %idx to i6495 %idxadd = add i64 %idxprom, 1696 %arrayidx = getelementptr inbounds i16, ptr addrspace(4) %p, i64 %idxadd97 %ld = load i16, ptr addrspace(4) %arrayidx, align 298 %ret.i32 = zext i16 %ld to i3299 %ret = bitcast i32 %ret.i32 to float100 ret float %ret101}102 103define amdgpu_ps <2 x float> @s_load_b64_idxprom(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {104; GCN-LABEL: s_load_b64_idxprom:105; GCN: ; %bb.0: ; %entry106; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1107; GCN-NEXT: s_load_b64 s[4:5], s[0:1], s2 offset:0x0 scale_offset108; GCN-NEXT: s_wait_kmcnt 0x0109; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5110; GCN-NEXT: ; return to shader part epilog111entry:112 %idxprom = zext i32 %idx to i64113 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(4) %p, i64 %idxprom114 %ret = load <2 x float>, ptr addrspace(4) %arrayidx, align 4115 ret <2 x float> %ret116}117 118define amdgpu_ps <3 x float> @s_load_b96_idxprom(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {119; GCN-LABEL: s_load_b96_idxprom:120; GCN: ; %bb.0: ; %entry121; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1122; GCN-NEXT: s_load_b96 s[4:6], s[0:1], s2 offset:0x0 scale_offset123; GCN-NEXT: s_wait_kmcnt 0x0124; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5125; GCN-NEXT: v_mov_b32_e32 v2, s6126; GCN-NEXT: ; return to shader part epilog127entry:128 %idxprom = zext i32 %idx to i64129 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(4) %p, i64 %idxprom130 %ret = load <3 x float>, ptr addrspace(4) %arrayidx, align 4131 ret <3 x float> %ret132}133 134define amdgpu_ps <4 x float> @s_load_b128_idxprom(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {135; GCN-LABEL: s_load_b128_idxprom:136; GCN: ; %bb.0: ; %entry137; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1138; GCN-NEXT: s_load_b128 s[4:7], s[0:1], s2 offset:0x0 scale_offset139; GCN-NEXT: s_wait_kmcnt 0x0140; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5141; GCN-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7142; GCN-NEXT: ; return to shader part epilog143entry:144 %idxprom = zext i32 %idx to i64145 %arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(4) %p, i64 %idxprom146 %ret = load <4 x float>, ptr addrspace(4) %arrayidx, align 4147 ret <4 x float> %ret148}149 150define amdgpu_ps <8 x float> @s_load_b256_idxprom(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {151; GCN-LABEL: s_load_b256_idxprom:152; GCN: ; %bb.0: ; %entry153; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1154; GCN-NEXT: s_load_b256 s[4:11], s[0:1], s2 offset:0x0 scale_offset155; GCN-NEXT: s_wait_kmcnt 0x0156; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5157; GCN-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7158; GCN-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9159; GCN-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11160; GCN-NEXT: ; return to shader part epilog161entry:162 %idxprom = zext i32 %idx to i64163 %arrayidx = getelementptr inbounds <8 x float>, ptr addrspace(4) %p, i64 %idxprom164 %ret = load <8 x float>, ptr addrspace(4) %arrayidx, align 4165 ret <8 x float> %ret166}167 168define amdgpu_ps <16 x float> @s_load_b512_idxprom(ptr addrspace(4) align 4 inreg %p, i32 inreg %idx) {169; GCN-LABEL: s_load_b512_idxprom:170; GCN: ; %bb.0: ; %entry171; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1172; GCN-NEXT: s_load_b512 s[4:19], s[0:1], s2 offset:0x0 scale_offset173; GCN-NEXT: s_wait_kmcnt 0x0174; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5175; GCN-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7176; GCN-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9177; GCN-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11178; GCN-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13179; GCN-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15180; GCN-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17181; GCN-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19182; GCN-NEXT: ; return to shader part epilog183entry:184 %idxprom = zext i32 %idx to i64185 %arrayidx = getelementptr inbounds <16 x float>, ptr addrspace(4) %p, i64 %idxprom186 %ret = load <16 x float>, ptr addrspace(4) %arrayidx, align 4187 ret <16 x float> %ret188}189 190define amdgpu_ps float @s_load_b32_idxprom_range(ptr addrspace(4) align 4 inreg %p) {191; GCN-LABEL: s_load_b32_idxprom_range:192; GCN: ; %bb.0: ; %entry193; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1194; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0195; GCN-NEXT: s_wait_kmcnt 0x0196; GCN-NEXT: s_load_b32 s0, s[0:1], s2 offset:0x0 scale_offset197; GCN-NEXT: s_wait_kmcnt 0x0198; GCN-NEXT: v_mov_b32_e32 v0, s0199; GCN-NEXT: ; return to shader part epilog200entry:201 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0202 %idxprom = zext i32 %idx to i64203 %arrayidx = getelementptr inbounds float, ptr addrspace(4) %p, i64 %idxprom204 %ret = load float, ptr addrspace(4) %arrayidx, align 4205 ret float %ret206}207 208define amdgpu_ps float @s_load_b32_idxprom_range_ioffset(ptr addrspace(4) align 4 inreg %p) {209; GCN-LABEL: s_load_b32_idxprom_range_ioffset:210; GCN: ; %bb.0: ; %entry211; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1212; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0213; GCN-NEXT: s_wait_kmcnt 0x0214; GCN-NEXT: s_load_b32 s0, s[0:1], s2 offset:0x40 scale_offset215; GCN-NEXT: s_wait_kmcnt 0x0216; GCN-NEXT: v_mov_b32_e32 v0, s0217; GCN-NEXT: ; return to shader part epilog218entry:219 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0220 %idxprom = zext i32 %idx to i64221 %idxadd = add i64 %idxprom, 16222 %arrayidx = getelementptr inbounds float, ptr addrspace(4) %p, i64 %idxadd223 %ret = load float, ptr addrspace(4) %arrayidx, align 4224 ret float %ret225}226 227; Note: this is a byte load, there is nothing to scale228 229define amdgpu_ps float @s_load_b8_idxprom_range_ioffset(ptr addrspace(4) align 4 inreg %p) {230; GCN-LABEL: s_load_b8_idxprom_range_ioffset:231; GCN: ; %bb.0: ; %entry232; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1233; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0234; GCN-NEXT: s_wait_kmcnt 0x0235; GCN-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x10236; GCN-NEXT: s_wait_kmcnt 0x0237; GCN-NEXT: v_mov_b32_e32 v0, s0238; GCN-NEXT: ; return to shader part epilog239entry:240 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0241 %idxprom = zext i32 %idx to i64242 %idxadd = add i64 %idxprom, 16243 %arrayidx = getelementptr inbounds i8, ptr addrspace(4) %p, i64 %idxadd244 %ld = load i8, ptr addrspace(4) %arrayidx245 %ret.i32 = zext i8 %ld to i32246 %ret = bitcast i32 %ret.i32 to float247 ret float %ret248}249 250define amdgpu_ps float @s_load_b16_idxprom_range(ptr addrspace(4) align 4 inreg %p) {251; GCN-LABEL: s_load_b16_idxprom_range:252; GCN: ; %bb.0: ; %entry253; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1254; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0255; GCN-NEXT: s_wait_kmcnt 0x0256; GCN-NEXT: s_load_u16 s0, s[0:1], s2 offset:0x0 scale_offset257; GCN-NEXT: s_wait_kmcnt 0x0258; GCN-NEXT: v_mov_b32_e32 v0, s0259; GCN-NEXT: ; return to shader part epilog260entry:261 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0262 %idxprom = zext i32 %idx to i64263 %arrayidx = getelementptr inbounds i16, ptr addrspace(4) %p, i64 %idxprom264 %ld = load i16, ptr addrspace(4) %arrayidx, align 2265 %ret.i32 = zext i16 %ld to i32266 %ret = bitcast i32 %ret.i32 to float267 ret float %ret268}269 270define amdgpu_ps float @s_load_b16_idxprom_range_ioffset(ptr addrspace(4) align 4 inreg %p) {271; GCN-LABEL: s_load_b16_idxprom_range_ioffset:272; GCN: ; %bb.0: ; %entry273; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1274; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0275; GCN-NEXT: s_wait_kmcnt 0x0276; GCN-NEXT: s_load_u16 s0, s[0:1], s2 offset:0x20 scale_offset277; GCN-NEXT: s_wait_kmcnt 0x0278; GCN-NEXT: v_mov_b32_e32 v0, s0279; GCN-NEXT: ; return to shader part epilog280entry:281 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0282 %idxprom = zext i32 %idx to i64283 %idxadd = add i64 %idxprom, 16284 %arrayidx = getelementptr inbounds i16, ptr addrspace(4) %p, i64 %idxadd285 %ld = load i16, ptr addrspace(4) %arrayidx, align 2286 %ret.i32 = zext i16 %ld to i32287 %ret = bitcast i32 %ret.i32 to float288 ret float %ret289}290 291define amdgpu_ps <2 x float> @s_load_b64_idxprom_range(ptr addrspace(4) align 4 inreg %p) {292; GCN-LABEL: s_load_b64_idxprom_range:293; GCN: ; %bb.0: ; %entry294; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1295; GCN-NEXT: s_load_b32 s4, s[0:1], 0x0296; GCN-NEXT: s_wait_kmcnt 0x0297; GCN-NEXT: s_load_b64 s[2:3], s[0:1], s4 offset:0x0 scale_offset298; GCN-NEXT: s_wait_kmcnt 0x0299; GCN-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3300; GCN-NEXT: ; return to shader part epilog301entry:302 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0303 %idxprom = zext i32 %idx to i64304 %arrayidx = getelementptr inbounds <2 x float>, ptr addrspace(4) %p, i64 %idxprom305 %ret = load <2 x float>, ptr addrspace(4) %arrayidx, align 4306 ret <2 x float> %ret307}308 309define amdgpu_ps <3 x float> @s_load_b96_idxprom_range(ptr addrspace(4) align 4 inreg %p) {310; GCN-LABEL: s_load_b96_idxprom_range:311; GCN: ; %bb.0: ; %entry312; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1313; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0314; GCN-NEXT: s_wait_kmcnt 0x0315; GCN-NEXT: s_load_b96 s[4:6], s[0:1], s2 offset:0x0 scale_offset316; GCN-NEXT: s_wait_kmcnt 0x0317; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5318; GCN-NEXT: v_mov_b32_e32 v2, s6319; GCN-NEXT: ; return to shader part epilog320entry:321 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0322 %idxprom = zext i32 %idx to i64323 %arrayidx = getelementptr inbounds [3 x float], ptr addrspace(4) %p, i64 %idxprom324 %ret = load <3 x float>, ptr addrspace(4) %arrayidx, align 4325 ret <3 x float> %ret326}327 328define amdgpu_ps <4 x float> @s_load_b128_idxprom_range(ptr addrspace(4) align 4 inreg %p) {329; GCN-LABEL: s_load_b128_idxprom_range:330; GCN: ; %bb.0: ; %entry331; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1332; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0333; GCN-NEXT: s_wait_kmcnt 0x0334; GCN-NEXT: s_load_b128 s[4:7], s[0:1], s2 offset:0x0 scale_offset335; GCN-NEXT: s_wait_kmcnt 0x0336; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5337; GCN-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7338; GCN-NEXT: ; return to shader part epilog339entry:340 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0341 %idxprom = zext i32 %idx to i64342 %arrayidx = getelementptr inbounds <4 x float>, ptr addrspace(4) %p, i64 %idxprom343 %ret = load <4 x float>, ptr addrspace(4) %arrayidx, align 4344 ret <4 x float> %ret345}346 347define amdgpu_ps <8 x float> @s_load_b256_idxprom_range(ptr addrspace(4) align 4 inreg %p) {348; GCN-LABEL: s_load_b256_idxprom_range:349; GCN: ; %bb.0: ; %entry350; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1351; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0352; GCN-NEXT: s_wait_kmcnt 0x0353; GCN-NEXT: s_load_b256 s[4:11], s[0:1], s2 offset:0x0 scale_offset354; GCN-NEXT: s_wait_kmcnt 0x0355; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5356; GCN-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7357; GCN-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9358; GCN-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11359; GCN-NEXT: ; return to shader part epilog360entry:361 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0362 %idxprom = zext i32 %idx to i64363 %arrayidx = getelementptr inbounds <8 x float>, ptr addrspace(4) %p, i64 %idxprom364 %ret = load <8 x float>, ptr addrspace(4) %arrayidx, align 4365 ret <8 x float> %ret366}367 368define amdgpu_ps <16 x float> @s_load_b512_idxprom_range(ptr addrspace(4) align 4 inreg %p) {369; GCN-LABEL: s_load_b512_idxprom_range:370; GCN: ; %bb.0: ; %entry371; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1372; GCN-NEXT: s_load_b32 s2, s[0:1], 0x0373; GCN-NEXT: s_wait_kmcnt 0x0374; GCN-NEXT: s_load_b512 s[4:19], s[0:1], s2 offset:0x0 scale_offset375; GCN-NEXT: s_wait_kmcnt 0x0376; GCN-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5377; GCN-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7378; GCN-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9379; GCN-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11380; GCN-NEXT: v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13381; GCN-NEXT: v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15382; GCN-NEXT: v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, s17383; GCN-NEXT: v_dual_mov_b32 v14, s18 :: v_dual_mov_b32 v15, s19384; GCN-NEXT: ; return to shader part epilog385entry:386 %idx = load i32, ptr addrspace(4) %p, align 4, !range !0387 %idxprom = zext i32 %idx to i64388 %arrayidx = getelementptr inbounds <16 x float>, ptr addrspace(4) %p, i64 %idxprom389 %ret = load <16 x float>, ptr addrspace(4) %arrayidx, align 4390 ret <16 x float> %ret391}392 393!0 = !{i32 0, i32 1024}394