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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck %s3 4; This was a negative test to catch an extreme case when all options are exhausted5; while trying to spill SGPRs to memory. After we enabled SGPR spills into virtual VGPRs6; the edge case won't arise and the test would always compile.7 8define amdgpu_kernel void @kernel0(ptr addrspace(1) %out, i32 %in) #1 {9; CHECK-LABEL: kernel0:10; CHECK: ; %bb.0:11; CHECK-NEXT: ;;#ASMSTART12; CHECK-NEXT: ;;#ASMEND13; CHECK-NEXT: ;;#ASMSTART14; CHECK-NEXT: ;;#ASMEND15; CHECK-NEXT: ;;#ASMSTART16; CHECK-NEXT: ;;#ASMEND17; CHECK-NEXT: ;;#ASMSTART18; CHECK-NEXT: ;;#ASMEND19; CHECK-NEXT: ;;#ASMSTART20; CHECK-NEXT: ; def s[2:3]21; CHECK-NEXT: ;;#ASMEND22; CHECK-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane23; CHECK-NEXT: s_load_dword s0, s[8:9], 0x824; CHECK-NEXT: v_writelane_b32 v22, s2, 025; CHECK-NEXT: v_writelane_b32 v22, s3, 126; CHECK-NEXT: ;;#ASMSTART27; CHECK-NEXT: ; def s[48:51]28; CHECK-NEXT: ;;#ASMEND29; CHECK-NEXT: ;;#ASMSTART30; CHECK-NEXT: ; def s[4:11]31; CHECK-NEXT: ;;#ASMEND32; CHECK-NEXT: v_writelane_b32 v22, s4, 233; CHECK-NEXT: v_writelane_b32 v22, s5, 334; CHECK-NEXT: v_writelane_b32 v22, s6, 435; CHECK-NEXT: v_writelane_b32 v22, s7, 536; CHECK-NEXT: v_writelane_b32 v22, s8, 637; CHECK-NEXT: v_writelane_b32 v22, s9, 738; CHECK-NEXT: v_writelane_b32 v22, s10, 839; CHECK-NEXT: v_writelane_b32 v22, s11, 940; CHECK-NEXT: ;;#ASMSTART41; CHECK-NEXT: ; def s[4:19]42; CHECK-NEXT: ;;#ASMEND43; CHECK-NEXT: v_writelane_b32 v22, s4, 1044; CHECK-NEXT: v_writelane_b32 v22, s5, 1145; CHECK-NEXT: v_writelane_b32 v22, s6, 1246; CHECK-NEXT: v_writelane_b32 v22, s7, 1347; CHECK-NEXT: v_writelane_b32 v22, s8, 1448; CHECK-NEXT: v_writelane_b32 v22, s9, 1549; CHECK-NEXT: v_writelane_b32 v22, s10, 1650; CHECK-NEXT: v_writelane_b32 v22, s11, 1751; CHECK-NEXT: v_writelane_b32 v22, s12, 1852; CHECK-NEXT: v_writelane_b32 v22, s13, 1953; CHECK-NEXT: v_writelane_b32 v22, s14, 2054; CHECK-NEXT: v_writelane_b32 v22, s15, 2155; CHECK-NEXT: v_writelane_b32 v22, s16, 2256; CHECK-NEXT: v_writelane_b32 v22, s17, 2357; CHECK-NEXT: v_writelane_b32 v22, s18, 2458; CHECK-NEXT: v_writelane_b32 v22, s19, 2559; CHECK-NEXT: ;;#ASMSTART60; CHECK-NEXT: ; def s[38:39]61; CHECK-NEXT: ;;#ASMEND62; CHECK-NEXT: ;;#ASMSTART63; CHECK-NEXT: ; def s[44:47]64; CHECK-NEXT: ;;#ASMEND65; CHECK-NEXT: ;;#ASMSTART66; CHECK-NEXT: ; def s[4:11]67; CHECK-NEXT: ;;#ASMEND68; CHECK-NEXT: v_writelane_b32 v22, s4, 2669; CHECK-NEXT: v_writelane_b32 v22, s5, 2770; CHECK-NEXT: v_writelane_b32 v22, s6, 2871; CHECK-NEXT: v_writelane_b32 v22, s7, 2972; CHECK-NEXT: v_writelane_b32 v22, s8, 3073; CHECK-NEXT: v_writelane_b32 v22, s9, 3174; CHECK-NEXT: v_writelane_b32 v22, s10, 3275; CHECK-NEXT: v_writelane_b32 v22, s11, 3376; CHECK-NEXT: s_waitcnt lgkmcnt(0)77; CHECK-NEXT: s_cmp_lg_u32 s0, 078; CHECK-NEXT: ;;#ASMSTART79; CHECK-NEXT: ; def s[16:31]80; CHECK-NEXT: ;;#ASMEND81; CHECK-NEXT: ;;#ASMSTART82; CHECK-NEXT: ; def s[36:37]83; CHECK-NEXT: ;;#ASMEND84; CHECK-NEXT: ;;#ASMSTART85; CHECK-NEXT: ; def s[40:43]86; CHECK-NEXT: ;;#ASMEND87; CHECK-NEXT: ;;#ASMSTART88; CHECK-NEXT: ; def s[0:7]89; CHECK-NEXT: ;;#ASMEND90; CHECK-NEXT: v_writelane_b32 v22, s0, 3491; CHECK-NEXT: v_writelane_b32 v22, s1, 3592; CHECK-NEXT: v_writelane_b32 v22, s2, 3693; CHECK-NEXT: v_writelane_b32 v22, s3, 3794; CHECK-NEXT: v_writelane_b32 v22, s4, 3895; CHECK-NEXT: v_writelane_b32 v22, s5, 3996; CHECK-NEXT: v_writelane_b32 v22, s6, 4097; CHECK-NEXT: v_writelane_b32 v22, s7, 4198; CHECK-NEXT: ;;#ASMSTART99; CHECK-NEXT: ; def s[0:15]100; CHECK-NEXT: ;;#ASMEND101; CHECK-NEXT: v_writelane_b32 v22, s0, 42102; CHECK-NEXT: v_writelane_b32 v22, s1, 43103; CHECK-NEXT: v_writelane_b32 v22, s2, 44104; CHECK-NEXT: v_writelane_b32 v22, s3, 45105; CHECK-NEXT: v_writelane_b32 v22, s4, 46106; CHECK-NEXT: v_writelane_b32 v22, s5, 47107; CHECK-NEXT: v_writelane_b32 v22, s6, 48108; CHECK-NEXT: v_writelane_b32 v22, s7, 49109; CHECK-NEXT: v_writelane_b32 v22, s8, 50110; CHECK-NEXT: v_writelane_b32 v22, s9, 51111; CHECK-NEXT: v_writelane_b32 v22, s10, 52112; CHECK-NEXT: v_writelane_b32 v22, s11, 53113; CHECK-NEXT: v_writelane_b32 v22, s12, 54114; CHECK-NEXT: v_writelane_b32 v22, s13, 55115; CHECK-NEXT: v_writelane_b32 v22, s14, 56116; CHECK-NEXT: v_writelane_b32 v22, s15, 57117; CHECK-NEXT: ;;#ASMSTART118; CHECK-NEXT: ; def s[34:35]119; CHECK-NEXT: ;;#ASMEND120; CHECK-NEXT: ;;#ASMSTART121; CHECK-NEXT: ; def s[0:3]122; CHECK-NEXT: ;;#ASMEND123; CHECK-NEXT: v_writelane_b32 v22, s0, 58124; CHECK-NEXT: v_writelane_b32 v22, s1, 59125; CHECK-NEXT: v_writelane_b32 v22, s2, 60126; CHECK-NEXT: v_writelane_b32 v22, s3, 61127; CHECK-NEXT: ;;#ASMSTART128; CHECK-NEXT: ; def s[0:7]129; CHECK-NEXT: ;;#ASMEND130; CHECK-NEXT: ; implicit-def: $vgpr23 : SGPR spill to VGPR lane131; CHECK-NEXT: v_writelane_b32 v22, s0, 62132; CHECK-NEXT: v_writelane_b32 v23, s2, 0133; CHECK-NEXT: v_writelane_b32 v23, s3, 1134; CHECK-NEXT: v_writelane_b32 v23, s4, 2135; CHECK-NEXT: v_writelane_b32 v23, s5, 3136; CHECK-NEXT: v_writelane_b32 v23, s6, 4137; CHECK-NEXT: v_writelane_b32 v22, s1, 63138; CHECK-NEXT: v_writelane_b32 v23, s7, 5139; CHECK-NEXT: ;;#ASMSTART140; CHECK-NEXT: ; def s[0:15]141; CHECK-NEXT: ;;#ASMEND142; CHECK-NEXT: v_writelane_b32 v23, s0, 6143; CHECK-NEXT: v_writelane_b32 v23, s1, 7144; CHECK-NEXT: v_writelane_b32 v23, s2, 8145; CHECK-NEXT: v_writelane_b32 v23, s3, 9146; CHECK-NEXT: v_writelane_b32 v23, s4, 10147; CHECK-NEXT: v_writelane_b32 v23, s5, 11148; CHECK-NEXT: v_writelane_b32 v23, s6, 12149; CHECK-NEXT: v_writelane_b32 v23, s7, 13150; CHECK-NEXT: v_writelane_b32 v23, s8, 14151; CHECK-NEXT: v_writelane_b32 v23, s9, 15152; CHECK-NEXT: v_writelane_b32 v23, s10, 16153; CHECK-NEXT: v_writelane_b32 v23, s11, 17154; CHECK-NEXT: v_writelane_b32 v23, s12, 18155; CHECK-NEXT: v_writelane_b32 v23, s13, 19156; CHECK-NEXT: v_writelane_b32 v23, s14, 20157; CHECK-NEXT: v_writelane_b32 v23, s15, 21158; CHECK-NEXT: ;;#ASMSTART159; CHECK-NEXT: ; def s[0:1]160; CHECK-NEXT: ;;#ASMEND161; CHECK-NEXT: v_writelane_b32 v23, s0, 22162; CHECK-NEXT: v_writelane_b32 v23, s1, 23163; CHECK-NEXT: ;;#ASMSTART164; CHECK-NEXT: ; def s[0:3]165; CHECK-NEXT: ;;#ASMEND166; CHECK-NEXT: v_writelane_b32 v23, s0, 24167; CHECK-NEXT: v_writelane_b32 v23, s1, 25168; CHECK-NEXT: v_writelane_b32 v23, s2, 26169; CHECK-NEXT: v_writelane_b32 v23, s3, 27170; CHECK-NEXT: ;;#ASMSTART171; CHECK-NEXT: ; def s[0:7]172; CHECK-NEXT: ;;#ASMEND173; CHECK-NEXT: v_writelane_b32 v23, s0, 28174; CHECK-NEXT: v_writelane_b32 v23, s1, 29175; CHECK-NEXT: v_writelane_b32 v23, s2, 30176; CHECK-NEXT: v_writelane_b32 v23, s3, 31177; CHECK-NEXT: v_writelane_b32 v23, s4, 32178; CHECK-NEXT: v_writelane_b32 v23, s5, 33179; CHECK-NEXT: v_writelane_b32 v23, s6, 34180; CHECK-NEXT: v_writelane_b32 v23, s7, 35181; CHECK-NEXT: ;;#ASMSTART182; CHECK-NEXT: ; def s[0:15]183; CHECK-NEXT: ;;#ASMEND184; CHECK-NEXT: v_writelane_b32 v23, s0, 36185; CHECK-NEXT: v_writelane_b32 v23, s1, 37186; CHECK-NEXT: v_writelane_b32 v23, s2, 38187; CHECK-NEXT: v_writelane_b32 v23, s3, 39188; CHECK-NEXT: v_writelane_b32 v23, s4, 40189; CHECK-NEXT: v_writelane_b32 v23, s5, 41190; CHECK-NEXT: v_writelane_b32 v23, s6, 42191; CHECK-NEXT: v_writelane_b32 v23, s7, 43192; CHECK-NEXT: v_writelane_b32 v23, s8, 44193; CHECK-NEXT: v_writelane_b32 v23, s9, 45194; CHECK-NEXT: v_writelane_b32 v23, s10, 46195; CHECK-NEXT: v_writelane_b32 v23, s11, 47196; CHECK-NEXT: v_writelane_b32 v23, s12, 48197; CHECK-NEXT: v_writelane_b32 v23, s13, 49198; CHECK-NEXT: v_writelane_b32 v23, s14, 50199; CHECK-NEXT: v_writelane_b32 v23, s15, 51200; CHECK-NEXT: s_cbranch_scc0 .LBB0_2201; CHECK-NEXT: ; %bb.1: ; %ret202; CHECK-NEXT: s_endpgm203; CHECK-NEXT: .LBB0_2: ; %bb0204; CHECK-NEXT: v_readlane_b32 s0, v22, 0205; CHECK-NEXT: v_readlane_b32 s1, v22, 1206; CHECK-NEXT: ;;#ASMSTART207; CHECK-NEXT: ; use s[0:1]208; CHECK-NEXT: ;;#ASMEND209; CHECK-NEXT: v_readlane_b32 s0, v22, 2210; CHECK-NEXT: v_readlane_b32 s1, v22, 3211; CHECK-NEXT: v_readlane_b32 s2, v22, 4212; CHECK-NEXT: v_readlane_b32 s3, v22, 5213; CHECK-NEXT: v_readlane_b32 s4, v22, 6214; CHECK-NEXT: v_readlane_b32 s5, v22, 7215; CHECK-NEXT: v_readlane_b32 s6, v22, 8216; CHECK-NEXT: v_readlane_b32 s7, v22, 9217; CHECK-NEXT: ;;#ASMSTART218; CHECK-NEXT: ; use s[48:51]219; CHECK-NEXT: ;;#ASMEND220; CHECK-NEXT: ;;#ASMSTART221; CHECK-NEXT: ; use s[0:7]222; CHECK-NEXT: ;;#ASMEND223; CHECK-NEXT: v_readlane_b32 s0, v22, 10224; CHECK-NEXT: v_readlane_b32 s1, v22, 11225; CHECK-NEXT: v_readlane_b32 s2, v22, 12226; CHECK-NEXT: v_readlane_b32 s3, v22, 13227; CHECK-NEXT: v_readlane_b32 s4, v22, 14228; CHECK-NEXT: v_readlane_b32 s5, v22, 15229; CHECK-NEXT: v_readlane_b32 s6, v22, 16230; CHECK-NEXT: v_readlane_b32 s7, v22, 17231; CHECK-NEXT: v_readlane_b32 s8, v22, 18232; CHECK-NEXT: v_readlane_b32 s9, v22, 19233; CHECK-NEXT: v_readlane_b32 s10, v22, 20234; CHECK-NEXT: v_readlane_b32 s11, v22, 21235; CHECK-NEXT: v_readlane_b32 s12, v22, 22236; CHECK-NEXT: v_readlane_b32 s13, v22, 23237; CHECK-NEXT: v_readlane_b32 s14, v22, 24238; CHECK-NEXT: v_readlane_b32 s15, v22, 25239; CHECK-NEXT: ;;#ASMSTART240; CHECK-NEXT: ; use s[0:15]241; CHECK-NEXT: ;;#ASMEND242; CHECK-NEXT: v_readlane_b32 s0, v22, 26243; CHECK-NEXT: v_readlane_b32 s1, v22, 27244; CHECK-NEXT: v_readlane_b32 s2, v22, 28245; CHECK-NEXT: v_readlane_b32 s3, v22, 29246; CHECK-NEXT: v_readlane_b32 s4, v22, 30247; CHECK-NEXT: v_readlane_b32 s5, v22, 31248; CHECK-NEXT: v_readlane_b32 s6, v22, 32249; CHECK-NEXT: v_readlane_b32 s7, v22, 33250; CHECK-NEXT: ;;#ASMSTART251; CHECK-NEXT: ; use s[38:39]252; CHECK-NEXT: ;;#ASMEND253; CHECK-NEXT: ;;#ASMSTART254; CHECK-NEXT: ; use s[44:47]255; CHECK-NEXT: ;;#ASMEND256; CHECK-NEXT: ;;#ASMSTART257; CHECK-NEXT: ; use s[0:7]258; CHECK-NEXT: ;;#ASMEND259; CHECK-NEXT: v_readlane_b32 s0, v22, 34260; CHECK-NEXT: v_readlane_b32 s1, v22, 35261; CHECK-NEXT: v_readlane_b32 s2, v22, 36262; CHECK-NEXT: v_readlane_b32 s3, v22, 37263; CHECK-NEXT: v_readlane_b32 s4, v22, 38264; CHECK-NEXT: v_readlane_b32 s5, v22, 39265; CHECK-NEXT: v_readlane_b32 s6, v22, 40266; CHECK-NEXT: v_readlane_b32 s7, v22, 41267; CHECK-NEXT: ;;#ASMSTART268; CHECK-NEXT: ; use s[16:31]269; CHECK-NEXT: ;;#ASMEND270; CHECK-NEXT: ;;#ASMSTART271; CHECK-NEXT: ; use s[36:37]272; CHECK-NEXT: ;;#ASMEND273; CHECK-NEXT: ;;#ASMSTART274; CHECK-NEXT: ; use s[40:43]275; CHECK-NEXT: ;;#ASMEND276; CHECK-NEXT: ;;#ASMSTART277; CHECK-NEXT: ; use s[0:7]278; CHECK-NEXT: ;;#ASMEND279; CHECK-NEXT: v_readlane_b32 s0, v22, 42280; CHECK-NEXT: v_readlane_b32 s1, v22, 43281; CHECK-NEXT: v_readlane_b32 s2, v22, 44282; CHECK-NEXT: v_readlane_b32 s3, v22, 45283; CHECK-NEXT: v_readlane_b32 s4, v22, 46284; CHECK-NEXT: v_readlane_b32 s5, v22, 47285; CHECK-NEXT: v_readlane_b32 s6, v22, 48286; CHECK-NEXT: v_readlane_b32 s7, v22, 49287; CHECK-NEXT: v_readlane_b32 s8, v22, 50288; CHECK-NEXT: v_readlane_b32 s9, v22, 51289; CHECK-NEXT: v_readlane_b32 s10, v22, 52290; CHECK-NEXT: v_readlane_b32 s11, v22, 53291; CHECK-NEXT: v_readlane_b32 s12, v22, 54292; CHECK-NEXT: v_readlane_b32 s13, v22, 55293; CHECK-NEXT: v_readlane_b32 s14, v22, 56294; CHECK-NEXT: v_readlane_b32 s15, v22, 57295; CHECK-NEXT: ;;#ASMSTART296; CHECK-NEXT: ; use s[0:15]297; CHECK-NEXT: ;;#ASMEND298; CHECK-NEXT: v_readlane_b32 s0, v22, 58299; CHECK-NEXT: v_readlane_b32 s1, v22, 59300; CHECK-NEXT: v_readlane_b32 s2, v22, 60301; CHECK-NEXT: v_readlane_b32 s3, v22, 61302; CHECK-NEXT: ;;#ASMSTART303; CHECK-NEXT: ; use s[34:35]304; CHECK-NEXT: ;;#ASMEND305; CHECK-NEXT: ;;#ASMSTART306; CHECK-NEXT: ; use s[0:3]307; CHECK-NEXT: ;;#ASMEND308; CHECK-NEXT: v_readlane_b32 s0, v22, 62309; CHECK-NEXT: v_readlane_b32 s1, v22, 63310; CHECK-NEXT: v_readlane_b32 s2, v23, 0311; CHECK-NEXT: v_readlane_b32 s3, v23, 1312; CHECK-NEXT: v_readlane_b32 s4, v23, 2313; CHECK-NEXT: v_readlane_b32 s5, v23, 3314; CHECK-NEXT: v_readlane_b32 s6, v23, 4315; CHECK-NEXT: v_readlane_b32 s7, v23, 5316; CHECK-NEXT: ;;#ASMSTART317; CHECK-NEXT: ; use s[0:7]318; CHECK-NEXT: ;;#ASMEND319; CHECK-NEXT: v_readlane_b32 s0, v23, 6320; CHECK-NEXT: v_readlane_b32 s1, v23, 7321; CHECK-NEXT: v_readlane_b32 s2, v23, 8322; CHECK-NEXT: v_readlane_b32 s3, v23, 9323; CHECK-NEXT: v_readlane_b32 s4, v23, 10324; CHECK-NEXT: v_readlane_b32 s5, v23, 11325; CHECK-NEXT: v_readlane_b32 s6, v23, 12326; CHECK-NEXT: v_readlane_b32 s7, v23, 13327; CHECK-NEXT: v_readlane_b32 s8, v23, 14328; CHECK-NEXT: v_readlane_b32 s9, v23, 15329; CHECK-NEXT: v_readlane_b32 s10, v23, 16330; CHECK-NEXT: v_readlane_b32 s11, v23, 17331; CHECK-NEXT: v_readlane_b32 s12, v23, 18332; CHECK-NEXT: v_readlane_b32 s13, v23, 19333; CHECK-NEXT: v_readlane_b32 s14, v23, 20334; CHECK-NEXT: v_readlane_b32 s15, v23, 21335; CHECK-NEXT: ;;#ASMSTART336; CHECK-NEXT: ; use s[0:15]337; CHECK-NEXT: ;;#ASMEND338; CHECK-NEXT: v_readlane_b32 s0, v23, 22339; CHECK-NEXT: v_readlane_b32 s1, v23, 23340; CHECK-NEXT: ;;#ASMSTART341; CHECK-NEXT: ; use s[0:1]342; CHECK-NEXT: ;;#ASMEND343; CHECK-NEXT: v_readlane_b32 s0, v23, 24344; CHECK-NEXT: v_readlane_b32 s1, v23, 25345; CHECK-NEXT: v_readlane_b32 s2, v23, 26346; CHECK-NEXT: v_readlane_b32 s3, v23, 27347; CHECK-NEXT: ;;#ASMSTART348; CHECK-NEXT: ; use s[0:3]349; CHECK-NEXT: ;;#ASMEND350; CHECK-NEXT: v_readlane_b32 s0, v23, 28351; CHECK-NEXT: v_readlane_b32 s1, v23, 29352; CHECK-NEXT: v_readlane_b32 s2, v23, 30353; CHECK-NEXT: v_readlane_b32 s3, v23, 31354; CHECK-NEXT: v_readlane_b32 s4, v23, 32355; CHECK-NEXT: v_readlane_b32 s5, v23, 33356; CHECK-NEXT: v_readlane_b32 s6, v23, 34357; CHECK-NEXT: v_readlane_b32 s7, v23, 35358; CHECK-NEXT: ;;#ASMSTART359; CHECK-NEXT: ; use s[0:7]360; CHECK-NEXT: ;;#ASMEND361; CHECK-NEXT: v_readlane_b32 s0, v23, 36362; CHECK-NEXT: v_readlane_b32 s1, v23, 37363; CHECK-NEXT: v_readlane_b32 s2, v23, 38364; CHECK-NEXT: v_readlane_b32 s3, v23, 39365; CHECK-NEXT: v_readlane_b32 s4, v23, 40366; CHECK-NEXT: v_readlane_b32 s5, v23, 41367; CHECK-NEXT: v_readlane_b32 s6, v23, 42368; CHECK-NEXT: v_readlane_b32 s7, v23, 43369; CHECK-NEXT: v_readlane_b32 s8, v23, 44370; CHECK-NEXT: v_readlane_b32 s9, v23, 45371; CHECK-NEXT: v_readlane_b32 s10, v23, 46372; CHECK-NEXT: v_readlane_b32 s11, v23, 47373; CHECK-NEXT: v_readlane_b32 s12, v23, 48374; CHECK-NEXT: v_readlane_b32 s13, v23, 49375; CHECK-NEXT: v_readlane_b32 s14, v23, 50376; CHECK-NEXT: v_readlane_b32 s15, v23, 51377; CHECK-NEXT: ;;#ASMSTART378; CHECK-NEXT: ; use s[0:15]379; CHECK-NEXT: ;;#ASMEND380; CHECK-NEXT: s_endpgm381 call void asm sideeffect "", "~{v[0:7]}" () #0382 call void asm sideeffect "", "~{v[8:15]}" () #0383 call void asm sideeffect "", "~{v[16:19]}"() #0384 call void asm sideeffect "", "~{v[20:21]}"() #0385 386 %val0 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0387 %val1 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0388 %val2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0389 %val3 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0390 %val4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0391 %val5 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0392 %val6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0393 %val7 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0394 %val8 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0395 %val9 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0396 %val10 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0397 %val11 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0398 %val12 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0399 %val13 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0400 %val14 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0401 %val15 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0402 %val16 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0403 %val17 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0404 %val18 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0405 %val19 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0406 %cmp = icmp eq i32 %in, 0407 br i1 %cmp, label %bb0, label %ret408 409bb0:410 call void asm sideeffect "; use $0", "s"(<2 x i32> %val0) #0411 call void asm sideeffect "; use $0", "s"(<4 x i32> %val1) #0412 call void asm sideeffect "; use $0", "s"(<8 x i32> %val2) #0413 call void asm sideeffect "; use $0", "s"(<16 x i32> %val3) #0414 call void asm sideeffect "; use $0", "s"(<2 x i32> %val4) #0415 call void asm sideeffect "; use $0", "s"(<4 x i32> %val5) #0416 call void asm sideeffect "; use $0", "s"(<8 x i32> %val6) #0417 call void asm sideeffect "; use $0", "s"(<16 x i32> %val7) #0418 call void asm sideeffect "; use $0", "s"(<2 x i32> %val8) #0419 call void asm sideeffect "; use $0", "s"(<4 x i32> %val9) #0420 call void asm sideeffect "; use $0", "s"(<8 x i32> %val10) #0421 call void asm sideeffect "; use $0", "s"(<16 x i32> %val11) #0422 call void asm sideeffect "; use $0", "s"(<2 x i32> %val12) #0423 call void asm sideeffect "; use $0", "s"(<4 x i32> %val13) #0424 call void asm sideeffect "; use $0", "s"(<8 x i32> %val14) #0425 call void asm sideeffect "; use $0", "s"(<16 x i32> %val15) #0426 call void asm sideeffect "; use $0", "s"(<2 x i32> %val16) #0427 call void asm sideeffect "; use $0", "s"(<4 x i32> %val17) #0428 call void asm sideeffect "; use $0", "s"(<8 x i32> %val18) #0429 call void asm sideeffect "; use $0", "s"(<16 x i32> %val19) #0430 br label %ret431 432ret:433 ret void434}435 436attributes #0 = { nounwind }437attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" }438