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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -verify-misched -o - %s | FileCheck %s4 5# This would assert that a dead def should have no uses, but the dead6# def and use have different subreg indices.7 8---9name: multi_def_dead_reg_subreg_check10tracksRegLiveness: true11machineFunctionInfo:12 isEntryFunction: true13 scratchRSrcReg: '$sgpr24_sgpr25_sgpr26_sgpr27'14 frameOffsetReg: '$sgpr32'15 stackPtrOffsetReg: '$sgpr32'16 argumentInfo:17 privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }18 privateSegmentWaveByteOffset: { reg: '$sgpr33' }19body: |20 ; CHECK-LABEL: name: multi_def_dead_reg_subreg_check21 ; CHECK: bb.0:22 ; CHECK-NEXT: successors: %bb.1(0x80000000)23 ; CHECK-NEXT: liveins: $sgpr6_sgpr724 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec26 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec27 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec28 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_512 = COPY [[V_MOV_B32_e32_]]29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.1:31 ; CHECK-NEXT: successors: %bb.1(0x80000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN [[V_MOV_B32_e32_]].sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32), align 8, addrspace 5)34 ; CHECK-NEXT: dead [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec35 ; CHECK-NEXT: dead [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec36 ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 0, [[V_MOV_B32_e32_1]], implicit $exec37 ; CHECK-NEXT: dead [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec38 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub039 ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub1:vreg_512 = COPY [[COPY]].sub140 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead [[COPY1]], 1245194 /* regdef:VGPR_32 */, def dead [[COPY]].sub1, 1245193 /* reguse:VGPR_32 */, [[COPY1]], 1245193 /* reguse:VGPR_32 */, [[COPY]].sub141 ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub0:vreg_512 = COPY [[COPY]].sub042 ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub3:vreg_512 = COPY [[COPY]].sub343 ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_1]]44 ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub5:vreg_512 = COPY undef [[V_MOV_B32_e32_1]]45 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_512 = COPY [[COPY2]]46 ; CHECK-NEXT: dead [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 4, [[V_MOV_B32_e32_2]], implicit-def dead $vcc, implicit $exec47 ; CHECK-NEXT: S_BRANCH %bb.148 bb.0:49 liveins: $sgpr6_sgpr750 51 undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec52 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec53 %2:vgpr_32 = V_ADD_U32_e32 0, %1, implicit $exec54 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec55 %4:vreg_512 = COPY %056 57 bb.1:58 BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32), align 8, addrspace 5)59 %6:vgpr_32 = DS_READ_B32_gfx9 undef %7:vgpr_32, 0, 0, implicit $exec60 %8:vreg_64 = DS_READ_B64_gfx9 %1, 0, 0, implicit $exec61 %9:vreg_128 = DS_READ_B128_gfx9 %2, 0, 0, implicit $exec62 %10:vgpr_32 = V_ADD_CO_U32_e32 4, %3, implicit-def dead $vcc, implicit $exec63 undef %11.sub0:vreg_512 = COPY %4.sub064 %12:vgpr_32 = COPY %4.sub065 %11.sub1:vreg_512 = COPY %4.sub166 INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def dead %12:vgpr_32, 1245194 /* regdef:VGPR_32 */, def dead %4.sub1:vreg_512, 1245193 /* reguse:VGPR_32 */, %12:vgpr_32, 1245193 /* reguse:VGPR_32 */, %4.sub1:vreg_51267 %11.sub2:vreg_512 = COPY undef %168 %11.sub3:vreg_512 = COPY %4.sub369 %11.sub5:vreg_512 = COPY undef %170 %4:vreg_512 = COPY %1171 S_BRANCH %bb.172 73...74