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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck %s4 5# The sequence of DBG_VALUEs forms a scheduling region with 0 real6# instructions. The RegPressure tracker would end up skipping over any7# debug instructions, so it would point to the instruction8# before/outside of the region, hitting this assert:9# assert((BotRPTracker.getPos() == RegionEnd ||10# (RegionEnd->isDebugInstr() &&11# BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&12# "Can't find the region bottom");13 14---15name: only_dbg_value_sched_region16tracksRegLiveness: true17machineFunctionInfo:18 isEntryFunction: true19 waveLimiter: true20body: |21 ; CHECK-LABEL: name: only_dbg_value_sched_region22 ; CHECK: bb.0:23 ; CHECK-NEXT: successors: %bb.1(0x80000000)24 ; CHECK-NEXT: liveins: $vgpr025 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr027 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF28 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, implicit $exec29 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, implicit $exec30 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]31 ; CHECK-NEXT: undef [[V_ADD_F32_e32_:%[0-9]+]].sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $mode, implicit $exec32 ; CHECK-NEXT: dead undef [[V_ADD_F32_e32_:%[0-9]+]].sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $mode, implicit $exec33 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, implicit $exec34 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec35 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF36 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec37 ; CHECK-NEXT: undef [[V_ADD_F32_e32_1:%[0-9]+]].sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $mode, implicit $exec38 ; CHECK-NEXT: [[V_ADD_F32_e32_1:%[0-9]+]].sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $mode, implicit $exec39 ; CHECK-NEXT: GLOBAL_STORE_DWORDX2 [[V_ADD_F32_e32_1]], [[V_MOV_B32_e32_]], 32, 0, implicit $exec40 ; CHECK-NEXT: undef [[GLOBAL_LOAD_DWORD2:%[0-9]+]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, implicit $exec41 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF42 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF43 ; CHECK-NEXT: [[DEF2:%[0-9]+]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, implicit $exec44 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD2:%[0-9]+]].sub1:vreg_64 = IMPLICIT_DEF45 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF46 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF47 ; CHECK-NEXT: dead [[GLOBAL_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[GLOBAL_LOAD_DWORD2]], 0, 0, implicit $exec48 ; CHECK-NEXT: dead [[GLOBAL_LOAD_DWORD4:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, implicit $exec49 ; CHECK-NEXT: dead [[GLOBAL_LOAD_DWORD5:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, implicit $exec50 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF51 ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF52 ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF53 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec54 ; CHECK-NEXT: [[V_LSHLREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64_e64 2, [[DEF2]], implicit $exec55 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec56 ; CHECK-NEXT: S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_e64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_1]]57 ; CHECK-NEXT: GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec58 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: bb.1:60 ; CHECK-NEXT: successors: %bb.2(0x80000000)61 ; CHECK-NEXT: {{ $}}62 ; CHECK-NEXT: S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode63 ; CHECK-NEXT: DBG_VALUE64 ; CHECK-NEXT: DBG_VALUE65 ; CHECK-NEXT: DBG_VALUE66 ; CHECK-NEXT: S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode67 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: bb.2:69 ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]70 ; CHECK-NEXT: S_NOP 0, implicit [[DEF8]]71 ; CHECK-NEXT: S_ENDPGM 072 bb.0:73 liveins: $vgpr074 75 %0:vgpr_32 = COPY $vgpr076 %1:vreg_64 = IMPLICIT_DEF77 %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, implicit $exec78 %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, implicit $exec79 undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec80 %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec81 %5:vreg_64 = COPY %282 undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $mode, implicit $exec83 %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $mode, implicit $exec84 %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, implicit $exec85 %8:vreg_64 = IMPLICIT_DEF86 %9:vreg_64 = IMPLICIT_DEF87 %10:vreg_64 = IMPLICIT_DEF88 undef %11.sub1:vreg_64 = IMPLICIT_DEF89 %12:vgpr_32 = IMPLICIT_DEF90 %13:vgpr_32 = IMPLICIT_DEF91 %14:vreg_64 = IMPLICIT_DEF92 %15:vreg_64 = IMPLICIT_DEF93 %16:vgpr_32 = IMPLICIT_DEF94 %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec95 %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec96 undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $mode, implicit $exec97 %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $mode, implicit $exec98 GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, implicit $exec99 %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, implicit $exec100 %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, implicit $exec101 %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, implicit $exec102 %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, implicit $exec103 %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, implicit $exec104 %23:vreg_64 = V_LSHLREV_B64_e64 2, %8, implicit $exec105 S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17106 GLOBAL_STORE_DWORD %15, %18, 0, 0, implicit $exec107 108 bb.1:109 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode110 DBG_VALUE111 DBG_VALUE112 DBG_VALUE113 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode114 115 bb.2:116 S_NOP 0, implicit %0117 S_NOP 0, implicit %16118 S_ENDPGM 0119 120...121