341 lines · plain
1# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s2# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=machine-scheduler -o - %s | FileCheck %s3 4--- |5 %struct.widget.0 = type { float, i32, i32 }6 %struct.baz = type { <4 x float>, <4 x float>, <2 x float>, i32, i32 }7 %struct.snork = type { float, float, float, i32, float, float, float, float, %struct.spam }8 %struct.spam = type { %struct.zot, [16 x i8] }9 %struct.zot = type { float, float, float, float, <4 x float> }10 %struct.wombat = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [2 x i16], [2 x i16] }11 %struct.wombat.1 = type { [4 x i32], [4 x i32], [4 x i32], [4 x i32], i32, i32, i32, i32 }12 13 @sched_dbg_value_crash.tmp6 = internal unnamed_addr addrspace(3) global [256 x [16 x i8]] poison, align 1614 15 define amdgpu_kernel void @sched_dbg_value_crash(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture readonly %arg1, ptr addrspace(1) nocapture readonly %arg2, ptr addrspace(1) nocapture readonly %arg3, ptr addrspace(1) nocapture %arg4) local_unnamed_addr #2 {16 bb:17 %0 = getelementptr i32, ptr addrspace(1) %arg1, i64 0, !amdgpu.uniform !3, !amdgpu.noclobber !318 %tmp5 = alloca %struct.wombat, align 16, addrspace(5)19 %1 = call noalias nonnull dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()20 %2 = bitcast ptr addrspace(4) %1 to ptr addrspace(4)21 %3 = getelementptr inbounds i32, ptr addrspace(4) %2, i64 122 %4 = bitcast ptr addrspace(4) %3 to ptr addrspace(4), !amdgpu.uniform !3, !amdgpu.noclobber !323 %5 = load <2 x i32>, ptr addrspace(4) %4, align 4, !invariant.load !324 %6 = extractelement <2 x i32> %5, i32 025 %7 = extractelement <2 x i32> %5, i32 126 %8 = lshr i32 %6, 1627 %9 = call i32 @llvm.amdgcn.workitem.id.x(), !range !428 %10 = call i32 @llvm.amdgcn.workitem.id.y(), !range !429 %11 = call i32 @llvm.amdgcn.workitem.id.z(), !range !430 %12 = mul nuw nsw i32 %8, %731 %13 = mul i32 %12, %932 %14 = mul nuw nsw i32 %10, %733 %15 = add i32 %13, %1434 %16 = add i32 %15, %1135 %17 = getelementptr inbounds [256 x [16 x i8]], ptr addrspace(3) @sched_dbg_value_crash.tmp6, i32 0, i32 %1636 %tmp7 = load i64, ptr addrspace(4) null, align 53687091237 %tmp8 = tail call i32 @llvm.amdgcn.workitem.id.x() #3, !range !438 %tmp9 = zext i32 %tmp8 to i6439 %tmp10 = add i64 %tmp7, %tmp940 %tmp11 = shl i64 %tmp10, 3241 %tmp12 = ashr exact i64 %tmp11, 3242 %tmp13 = getelementptr inbounds %struct.widget.0, ptr addrspace(1) %arg2, i64 %tmp12, i32 143 %tmp14 = load i32, ptr addrspace(1) %tmp13, align 444 %tmp15 = getelementptr inbounds %struct.baz, ptr addrspace(1) %arg3, i64 %tmp12, i32 145 %tmp16 = load <4 x float>, ptr addrspace(1) %tmp15, align 1646 %tmp17 = sext i32 %tmp14 to i6447 %tmp18 = load i32, ptr addrspace(1) %0, align 448 %tmp19 = zext i32 %tmp18 to i6449 %tmp20 = shl nuw nsw i64 %tmp19, 250 %tmp21 = getelementptr inbounds i8, ptr addrspace(1) %arg, i64 %tmp2051 %tmp22 = bitcast ptr addrspace(1) %tmp21 to ptr addrspace(1)52 %tmp23 = bitcast ptr addrspace(5) %tmp5 to ptr addrspace(5)53 call void @llvm.lifetime.start.p5(i64 144, ptr addrspace(5) nonnull %tmp23) #354 %tmp24 = getelementptr inbounds %struct.wombat, ptr addrspace(5) %tmp5, i32 0, i32 655 %tmp25 = getelementptr i32, ptr addrspace(1) %arg1, i64 3, !amdgpu.uniform !3, !amdgpu.noclobber !356 %tmp26 = load i32, ptr addrspace(1) %tmp25, align 457 %tmp27 = zext i32 %tmp26 to i6458 %tmp28 = shl nuw nsw i64 %tmp27, 259 %tmp29 = getelementptr inbounds i8, ptr addrspace(1) %arg, i64 %tmp2860 %tmp30 = bitcast ptr addrspace(1) %tmp29 to ptr addrspace(1)61 %tmp31 = getelementptr inbounds %struct.wombat.1, ptr addrspace(1) %tmp22, i64 %tmp17, i32 2, i64 062 %18 = bitcast ptr addrspace(1) %tmp31 to ptr addrspace(1)63 %19 = load <3 x i32>, ptr addrspace(1) %18, align 464 %tmp325 = extractelement <3 x i32> %19, i32 065 %tmp386 = extractelement <3 x i32> %19, i32 166 %tmp447 = extractelement <3 x i32> %19, i32 267 %tmp33 = sext i32 %tmp325 to i6468 %tmp34 = getelementptr inbounds <2 x float>, ptr addrspace(1) %tmp30, i64 %tmp3369 %tmp35 = load <2 x float>, ptr addrspace(1) %tmp34, align 870 %tmp36 = extractelement <2 x float> %tmp35, i32 171 %tmp39 = sext i32 %tmp386 to i6472 %tmp40 = getelementptr inbounds <2 x float>, ptr addrspace(1) %tmp30, i64 %tmp3973 %tmp41 = load <2 x float>, ptr addrspace(1) %tmp40, align 874 %tmp42 = extractelement <2 x float> %tmp41, i32 175 %tmp45 = sext i32 %tmp447 to i6476 %tmp46 = getelementptr inbounds <2 x float>, ptr addrspace(1) %tmp30, i64 %tmp4577 %tmp47 = load <2 x float>, ptr addrspace(1) %tmp46, align 878 %tmp48 = extractelement <2 x float> %tmp47, i32 179 %tmp49 = getelementptr i32, ptr addrspace(1) %arg1, i64 1, !amdgpu.uniform !3, !amdgpu.noclobber !380 %tmp50 = load i32, ptr addrspace(1) %tmp49, align 481 %tmp51 = zext i32 %tmp50 to i6482 %tmp52 = shl nuw nsw i64 %tmp51, 283 %tmp53 = getelementptr inbounds i8, ptr addrspace(1) %arg, i64 %tmp5284 %tmp54 = bitcast ptr addrspace(1) %tmp53 to ptr addrspace(1)85 %tmp55 = getelementptr inbounds %struct.wombat.1, ptr addrspace(1) %tmp22, i64 %tmp17, i32 0, i64 086 %20 = bitcast ptr addrspace(1) %tmp55 to ptr addrspace(1)87 %21 = load <2 x i32>, ptr addrspace(1) %20, align 488 %tmp568 = extractelement <2 x i32> %21, i32 089 %tmp639 = extractelement <2 x i32> %21, i32 190 %tmp57 = sext i32 %tmp568 to i6491 %tmp58 = getelementptr inbounds <4 x float>, ptr addrspace(1) %tmp54, i64 %tmp5792 %tmp59 = load <4 x float>, ptr addrspace(1) %tmp58, align 1693 %tmp60 = extractelement <4 x float> %tmp59, i32 094 %tmp61 = extractelement <4 x float> %tmp59, i32 195 %tmp64 = sext i32 %tmp639 to i6496 %tmp65 = getelementptr inbounds <4 x float>, ptr addrspace(1) %tmp54, i64 %tmp6497 %tmp66 = load <4 x float>, ptr addrspace(1) %tmp65, align 1698 %tmp67 = extractelement <4 x float> %tmp16, i64 099 %tmp69 = fsub fast float -0.000000e+00, %tmp67100 %tmp70 = fmul float %tmp67, 0.000000e+00101 %tmp = fmul fast float %tmp67, poison102 %tmp71 = fsub fast float %tmp, %tmp70103 %tmp73 = fadd fast float %tmp, poison104 %tmp74 = insertelement <4 x float> <float poison, float poison, float poison, float 0.000000e+00>, float %tmp69, i32 0105 %tmp75 = insertelement <4 x float> %tmp74, float %tmp71, i32 1106 %tmp76 = insertelement <4 x float> %tmp75, float %tmp73, i32 2107 store <4 x float> %tmp76, ptr addrspace(5) %tmp24, align 16108 %tmp77 = fsub float poison, %tmp60109 %tmp78 = fsub float poison, %tmp61110 %tmp79 = extractelement <4 x float> %tmp66, i32 2111 %tmp80 = extractelement <4 x float> %tmp59, i32 2112 %tmp81 = fsub float %tmp79, %tmp80113 %tmp82 = fmul fast float %tmp81, poison114 %tmp83 = fmul fast float %tmp78, poison115 %tmp84 = fadd fast float %tmp83, %tmp77116 %tmp85 = fadd fast float %tmp84, poison117 %tmp86 = fmul float %tmp82, %tmp82118 %tmp87 = fdiv float 1.000000e+00, %tmp86119 tail call void @llvm.dbg.value(metadata float %tmp87, metadata !5, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #3, !dbg !8120 %tmp88 = fmul float %tmp82, 0.000000e+00121 %tmp89 = fsub fast float %tmp85, %tmp88122 %tmp90 = fdiv float %tmp89, %tmp86123 %tmp91 = fsub float 1.000000e+00, %tmp87124 %tmp92 = fsub float %tmp91, %tmp90125 %tmp93 = fmul float %tmp42, %tmp87126 %tmp94 = call float @llvm.fmuladd.f32(float %tmp92, float %tmp36, float %tmp93)127 %tmp95 = call float @llvm.fmuladd.f32(float %tmp48, float poison, float %tmp94)128 %fmul = fmul <2 x float> poison, poison129 %fadd = fadd <2 x float> %fmul, poison130 %extractelement = extractelement <2 x float> %fadd, i64 1131 %tmp96 = fsub float %extractelement, %tmp95132 %tmp97 = getelementptr inbounds %struct.wombat, ptr addrspace(5) %tmp5, i32 0, i32 8, i32 1133 call void @func(float %tmp96, i64 0, ptr addrspace(5) nonnull %tmp97) #3134 %tmp984 = bitcast ptr addrspace(3) %17 to ptr addrspace(3)135 %tmp99 = getelementptr inbounds %struct.snork, ptr addrspace(1) %arg4, i64 %tmp12, i32 8, i32 1, i64 0136 call void @llvm.memcpy.p1.p3.i64(ptr addrspace(1) %tmp99, ptr addrspace(3) %tmp984, i64 16, i32 16, i1 false)137 call void @llvm.lifetime.end.p5(i64 144, ptr addrspace(5) nonnull %tmp23) #3138 ret void139 }140 141 declare void @func(float, i64, ptr addrspace(5))142 declare void @llvm.lifetime.start.p5(i64, ptr addrspace(5) nocapture) #0143 declare float @llvm.fmuladd.f32(float, float, float) #1144 declare void @llvm.lifetime.end.p5(i64, ptr addrspace(5) nocapture) #0145 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1146 declare i32 @llvm.amdgcn.workitem.id.x() #1147 declare void @llvm.dbg.value(metadata, metadata, metadata) #1148 declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #1149 declare i32 @llvm.amdgcn.workitem.id.y() #1150 declare i32 @llvm.amdgcn.workitem.id.z() #1151 declare void @llvm.memcpy.p1.p5.i64(ptr addrspace(1) nocapture writeonly, ptr addrspace(5) nocapture readonly, i64, i32, i1) #0152 declare void @llvm.memcpy.p1.p3.i64(ptr addrspace(1) nocapture writeonly, ptr addrspace(3) nocapture readonly, i64, i32, i1) #0153 154 attributes #0 = { argmemonly nounwind }155 attributes #1 = { nounwind readnone speculatable }156 attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="gfx900" }157 attributes #3 = { nounwind }158 159 !llvm.dbg.cu = !{!0}160 !llvm.module.flags = !{!2}161 162 !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)163 !1 = !DIFile(filename: "foo.cl", directory: "/dev/null")164 !2 = !{i32 2, !"Debug Info Version", i32 3}165 !3 = !{}166 !4 = !{i32 0, i32 256}167 !5 = !DILocalVariable(name: "bar", scope: !6, file: !1, line: 102, type: !7)168 !6 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 81, isLocal: false, isDefinition: true, scopeLine: 86, flags: DIFlagPrototyped, isOptimized: true, unit: !0)169 !7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)170 !8 = !DILocation(line: 102, column: 8, scope: !6)171 172...173---174 175# CHECK: name: sched_dbg_value_crash176# CHECK: DBG_VALUE %99, $noreg, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8177 178name: sched_dbg_value_crash179alignment: 1180exposesReturnsTwice: false181legalized: false182regBankSelected: false183selected: false184tracksRegLiveness: true185frameInfo:186 adjustsStack: true187liveins:188 - { reg: '$vgpr0', virtual-reg: '%0' }189 - { reg: '$vgpr1', virtual-reg: '%1' }190 - { reg: '$vgpr2', virtual-reg: '%2' }191 - { reg: '$sgpr4_sgpr5', virtual-reg: '%3' }192 - { reg: '$sgpr6_sgpr7', virtual-reg: '%4' }193fixedStack:194stack:195 - { id: 0, name: tmp5, type: default, offset: 0, size: 128, alignment: 16,196 stack-id: default, callee-saved-register: '', callee-saved-restored: true,197 local-offset: 0, debug-info-variable: '', debug-info-expression: '',198 debug-info-location: '' }199constants:200body: |201 bb.0.bb:202 liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr32, $sgpr101203 204 %4:sgpr_64 = COPY $sgpr6_sgpr7205 %3:sgpr_64 = COPY $sgpr4_sgpr5206 %2:vgpr_32 = COPY $vgpr2207 %1:vgpr_32 = COPY $vgpr1208 %0:vgpr_32 = COPY $vgpr0209 %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)210 %6:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 8, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)211 %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 16, 0 :: (non-temporal dereferenceable invariant load (s64) from `ptr addrspace(4) poison`)212 %8:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 24, 0213 %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 32, 0214 %10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %3, 4, 0215 %11:sreg_32_xm0 = S_LSHR_B32 %10.sub0, 16, implicit-def dead $scc216 %12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1217 %13:vgpr_32 = V_MUL_LO_I32_e64 0, %0, implicit $exec218 %14:vgpr_32 = V_MUL_LO_I32_e64 %1, %10.sub1, implicit $exec219 %15:vgpr_32 = V_ADD_CO_U32_e32 0, %13, implicit-def dead $vcc, implicit $exec220 %16:vgpr_32 = V_ADD_CO_U32_e32 0, %15, implicit-def dead $vcc, implicit $exec221 %17:vgpr_32 = IMPLICIT_DEF222 %18:sreg_64 = S_MOV_B64 0223 %19:sreg_32_xm0_xexec = IMPLICIT_DEF224 %20:vgpr_32 = V_ADD_CO_U32_e32 %19, %0, implicit-def dead $vcc, implicit $exec225 %21:vreg_64, dead %22:sreg_64 = V_MAD_I64_I32_e64 %20, 12, %7, 0, implicit $exec226 %23:vgpr_32 = GLOBAL_LOAD_DWORD %21, 4, 0, implicit $exec227 %24:vreg_64, dead %25:sreg_64 = V_MAD_I64_I32_e64 %20, 48, %8, 0, implicit $exec228 %26:vreg_128 = IMPLICIT_DEF229 undef %27.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 0, 0230 %27.sub1:sreg_64_xexec = S_MOV_B32 0231 %28:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc232 undef %29.sub0:sreg_64 = S_ADD_U32 %5.sub0, %28.sub0, implicit-def $scc233 %29.sub1:sreg_64 = S_ADDC_U32 %5.sub1, %28.sub1, implicit-def dead $scc, implicit killed $scc234 undef %30.sub0:sreg_64_xexec = S_LOAD_DWORD_IMM %6, 4, 0235 %27.sub0:sreg_64_xexec = IMPLICIT_DEF236 %31:sreg_64 = S_LSHL_B64 %27, 2, implicit-def dead $scc237 %32:sreg_32_xm0 = S_ADD_U32 0, %31.sub0, implicit-def $scc238 %33:sgpr_32 = S_ADDC_U32 %5.sub1, %31.sub1, implicit-def dead $scc, implicit killed $scc239 %34:vgpr_32 = IMPLICIT_DEF240 %35:vreg_64, dead %36:sreg_64 = V_MAD_I64_I32_e64 %23, %34, 0, 0, implicit $exec241 %37:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 32, 0, implicit $exec242 undef %38.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %37.sub0, implicit $exec243 %38.sub0:vreg_64 = COPY %37.sub0244 %39:vreg_64 = V_LSHLREV_B64_e64 3, %38, implicit $exec245 undef %40.sub0:vreg_64, %41:sreg_64_xexec = V_ADD_CO_U32_e64 0, %39.sub0, 0, implicit $exec246 %42:vgpr_32 = COPY %33247 %40.sub1:vreg_64, dead %43:sreg_64_xexec = V_ADDC_U32_e64 %42, %39.sub1, %41, 0, implicit $exec248 %44:vreg_64 = GLOBAL_LOAD_DWORDX2 %40, 0, 0, implicit $exec :: (load (s64) from %ir.tmp34)249 undef %45.sub1:vreg_64 = IMPLICIT_DEF250 %45.sub0:vreg_64 = COPY %37.sub1251 %46:vreg_64 = V_LSHLREV_B64_e64 3, %45, implicit $exec252 undef %47.sub0:vreg_64, %48:sreg_64_xexec = V_ADD_CO_U32_e64 %32, %46.sub0, 0, implicit $exec253 %49:vgpr_32 = COPY %33254 %47.sub1:vreg_64, dead %50:sreg_64_xexec = V_ADDC_U32_e64 %49, %46.sub1, %48, 0, implicit $exec255 %51:vreg_64 = IMPLICIT_DEF256 undef %52.sub0:vreg_64 = GLOBAL_LOAD_DWORD %35, 40, 0, implicit $exec :: (load (s32) from %ir.18 + 8)257 %52.sub1:vreg_64 = IMPLICIT_DEF258 %53:vreg_64 = V_LSHLREV_B64_e64 3, %52, implicit $exec259 undef %54.sub0:vreg_64, %55:sreg_64_xexec = V_ADD_CO_U32_e64 0, %53.sub0, 0, implicit $exec260 %56:vgpr_32 = COPY %33261 %54.sub1:vreg_64, dead %57:sreg_64_xexec = V_ADDC_U32_e64 0, %53.sub1, %55, 0, implicit $exec262 %58:vreg_64 = IMPLICIT_DEF263 %30.sub1:sreg_64_xexec = IMPLICIT_DEF264 %59:sreg_64 = IMPLICIT_DEF265 %60:sreg_32_xm0 = S_ADD_U32 %5.sub0, %59.sub0, implicit-def $scc266 %61:sgpr_32 = S_ADDC_U32 %5.sub1, %59.sub1, implicit-def dead $scc, implicit killed $scc267 %62:vreg_64 = GLOBAL_LOAD_DWORDX2 %35, 0, 0, implicit $exec :: (load (s64) from %ir.20, align 4)268 undef %63.sub1:vreg_64 = V_ASHRREV_I32_e32 31, %62.sub0, implicit $exec269 %63.sub0:vreg_64 = COPY %62.sub0270 %64:vreg_64 = IMPLICIT_DEF271 undef %65.sub0:vreg_64, %66:sreg_64_xexec = V_ADD_CO_U32_e64 %60, %64.sub0, 0, implicit $exec272 %67:vgpr_32 = COPY %61273 %65.sub1:vreg_64, dead %68:sreg_64_xexec = V_ADDC_U32_e64 %67, %64.sub1, %66, 0, implicit $exec274 %69:vreg_128 = GLOBAL_LOAD_DWORDX4 %65, 0, 0, implicit $exec :: (load (s128) from %ir.tmp58)275 undef %70.sub1:vreg_64 = IMPLICIT_DEF276 %70.sub0:vreg_64 = IMPLICIT_DEF277 %71:vreg_64 = IMPLICIT_DEF278 undef %72.sub0:vreg_64, %73:sreg_64_xexec = V_ADD_CO_U32_e64 %60, %71.sub0, 0, implicit $exec279 %74:vgpr_32 = COPY %61280 %72.sub1:vreg_64, dead %75:sreg_64_xexec = V_ADDC_U32_e64 0, %71.sub1, %73, 0, implicit $exec281 %76:vreg_128 = GLOBAL_LOAD_DWORDX4 %72, 0, 0, implicit $exec282 %77:vgpr_32 = IMPLICIT_DEF283 %78:vgpr_32 = IMPLICIT_DEF284 %79:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %77, implicit $mode, implicit $exec285 %80:vgpr_32 = IMPLICIT_DEF286 %81:vgpr_32 = IMPLICIT_DEF287 %84:vgpr_32 = IMPLICIT_DEF288 BUFFER_STORE_DWORD_OFFEN %84, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 108, 0, 0, implicit $exec289 BUFFER_STORE_DWORD_OFFEN %81, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 104, 0, 0, implicit $exec290 BUFFER_STORE_DWORD_OFFEN %80, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 100, 0, 0, implicit $exec291 BUFFER_STORE_DWORD_OFFEN %78, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 96, 0, 0, implicit $exec292 %85:vgpr_32 = IMPLICIT_DEF293 %86:vgpr_32 = IMPLICIT_DEF294 %87:vgpr_32 = IMPLICIT_DEF295 %88:vgpr_32 = IMPLICIT_DEF296 %90:vgpr_32 = IMPLICIT_DEF297 %91:vgpr_32, dead %92:sreg_64 = nofpexcept V_DIV_SCALE_F32_e64 0, %90, 0, %90, 0, 1065353216, 0, 0, implicit $mode, implicit $exec298 %95:vgpr_32 = nofpexcept V_FMA_F32_e64 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $mode, implicit $exec299 %96:vgpr_32, %97:sreg_64 = nofpexcept V_DIV_SCALE_F32_e64 0, 1065353216, 0, %90, 0, 1065353216, 0, 0, implicit $mode, implicit $exec300 %98:vgpr_32 = IMPLICIT_DEF301 %99:vgpr_32 = IMPLICIT_DEF302 %100:vgpr_32 = IMPLICIT_DEF303 %101:vgpr_32 = IMPLICIT_DEF304 %102:vgpr_32 = IMPLICIT_DEF305 %103:vgpr_32 = IMPLICIT_DEF306 %104:vgpr_32 = IMPLICIT_DEF307 %105:vgpr_32 = IMPLICIT_DEF308 %106:vgpr_32, dead %107:sreg_64 = nofpexcept V_DIV_SCALE_F32_e64 0, %90, 0, %90, 0, %105, 0, 0, implicit $mode, implicit $exec309 %108:vgpr_32 = nofpexcept V_RCP_F32_e32 0, implicit $mode, implicit $exec310 %109:vgpr_32 = IMPLICIT_DEF311 %110:vgpr_32 = nofpexcept V_FMA_F32_e64 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec312 %111:vgpr_32, %112:sreg_64 = nofpexcept V_DIV_SCALE_F32_e64 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec313 %113:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %110, implicit $mode, implicit $exec314 %114:vgpr_32 = IMPLICIT_DEF315 %115:vgpr_32 = IMPLICIT_DEF316 %116:vgpr_32 = IMPLICIT_DEF317 $vcc = IMPLICIT_DEF318 %117:vgpr_32 = nofpexcept V_DIV_FMAS_F32_e64 0, %116, 0, %110, 0, %115, 0, 0, implicit killed $vcc, implicit $mode, implicit $exec319 %118:vgpr_32 = nofpexcept V_DIV_FIXUP_F32_e64 0, %117, 0, %90, 0, %105, 0, 0, implicit $mode, implicit $exec320 %119:vgpr_32 = IMPLICIT_DEF321 %120:vgpr_32 = IMPLICIT_DEF322 %121:vgpr_32 = IMPLICIT_DEF323 %122:vgpr_32 = IMPLICIT_DEF324 %123:vgpr_32 = IMPLICIT_DEF325 %124:vgpr_32 = IMPLICIT_DEF326 %125:vgpr_32 = IMPLICIT_DEF327 %126:vgpr_32 = IMPLICIT_DEF328 DBG_VALUE %103, _, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8329 ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32330 %127:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc331 $sgpr4 = COPY $sgpr101332 $vgpr0 = COPY %124333 $vgpr1_vgpr2 = IMPLICIT_DEF334 $vgpr3 = COPY %126335 dead $sgpr30_sgpr31 = SI_CALL %127, @func, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0, implicit $vgpr1_vgpr2, implicit killed $vgpr3336 ADJCALLSTACKDOWN 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32337 %128:vreg_64, dead %129:sreg_64 = V_MAD_I64_I32_e64 %20, %34, 0, 0, implicit $exec338 S_ENDPGM 0339 340...341