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1; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack -amdgpu-use-amdgpu-trackers=1 2>&1 < %s | FileCheck -check-prefixes=ERR-GCNTRACKERS %s2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack 2>&1 < %s | FileCheck -check-prefixes=GCN %s3 4%asm.output = type { <16 x i32>, <16 x i32>, <16 x i32>, <8 x i32>, <2 x i32>, i32, ; sgprs5 <16 x i32>, <7 x i32>, ; vgprs6 i64 ; vcc7 }8 9%asm.output2 = type { <16 x i32>, <16 x i32>, <16 x i32>, <8 x i32>, <2 x i32>, i32, ; sgprs10 <16 x i32>, <5 x i32>, ; vgprs11 i64 ; vcc12 }13 14%asm.output3 = type { <16 x i32>, <16 x i32>, <16 x i32>, <8 x i32>, <2 x i32>, ; sgprs15 <16 x i32>, <6 x i32>, ; vgprs16 i64 ; vcc17 }18 19; ERR-GCNTRACKERS: ran out of registers during register allocation20; GCN-NOT: ran out of registers during register allocation21 22; FIXME: GCN Trackers do not track pressure from PhysRegs, so scheduling is actually worse23 24define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0 {25 %alloca0 = alloca [4096 x i32], align 64, addrspace(5)26 %alloca1 = alloca i32, align 4, addrspace(5)27 call void asm sideeffect "; use alloca0 $0", "v"(ptr addrspace(5) %alloca0)28 29 %asm = call %asm.output asm sideeffect30 "; def $0, $1, $2, $3, $4, $5, $6, $7, $8",31 "={s[0:15]},={s[16:31]},={s[32:47]},={s[48:55]},={s[56:57]},={s58},={v[0:15]},={v[16:22]},={vcc}"()32 33 %s0 = extractvalue %asm.output %asm, 034 %s1 = extractvalue %asm.output %asm, 135 %s2 = extractvalue %asm.output %asm, 236 %s3 = extractvalue %asm.output %asm, 337 %s4 = extractvalue %asm.output %asm, 438 %s5 = extractvalue %asm.output %asm, 539 40 %v0 = extractvalue %asm.output %asm, 641 %v1 = extractvalue %asm.output %asm, 742 43 %vcc = extractvalue %asm.output %asm, 844 45 ; scc is unavailable since it is live in46 call void asm sideeffect "; use $0, $1, $2, $3, $4, $5, $6, $7, $8, $9, $10",47 "{s[0:15]},{s[16:31]},{s[32:47]},{s[48:55]},{s[56:57]},{s58},{v[0:15]},{v[16:22]},{vcc},{s64},{scc}"(48 <16 x i32> %s0,49 <16 x i32> %s1,50 <16 x i32> %s2,51 <8 x i32> %s3,52 <2 x i32> %s4,53 i32 %s5,54 <16 x i32> %v0,55 <7 x i32> %v1,56 i64 %vcc,57 ptr addrspace(5) %alloca1,58 i32 0) ; use of scc59 60 ret void61}62 63attributes #0 = { nounwind alignstack=64 "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="10,10" "no-realign-stack" }64attributes #1 = { nounwind alignstack=16 "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="10,10" "no-realign-stack" }65 66