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1; RUN: llc -mtriple=r600 -mcpu=cayman -stress-sched -verify-misched < %s2; REQUIRES: asserts3 4define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {5main_body:6 %tmp = extractelement <4 x float> %reg1, i32 07 %tmp5 = extractelement <4 x float> %reg1, i32 18 %tmp6 = extractelement <4 x float> %reg1, i32 29 %tmp7 = extractelement <4 x float> %reg1, i32 310 %tmp8 = fcmp ult float %tmp5, 0.000000e+0011 %tmp9 = select i1 %tmp8, float 1.000000e+00, float 0.000000e+0012 %tmp10 = fsub float -0.000000e+00, %tmp913 %tmp11 = fptosi float %tmp10 to i3214 %tmp12 = bitcast i32 %tmp11 to float15 %tmp13 = fcmp ult float %tmp, 5.700000e+0116 %tmp14 = select i1 %tmp13, float 1.000000e+00, float 0.000000e+0017 %tmp15 = fsub float -0.000000e+00, %tmp1418 %tmp16 = fptosi float %tmp15 to i3219 %tmp17 = bitcast i32 %tmp16 to float20 %tmp18 = bitcast float %tmp12 to i3221 %tmp19 = bitcast float %tmp17 to i3222 %tmp20 = and i32 %tmp18, %tmp1923 %tmp21 = bitcast i32 %tmp20 to float24 %tmp22 = bitcast float %tmp21 to i3225 %tmp23 = icmp ne i32 %tmp22, 026 %tmp24 = fcmp ult float %tmp, 0.000000e+0027 %tmp25 = select i1 %tmp24, float 1.000000e+00, float 0.000000e+0028 %tmp26 = fsub float -0.000000e+00, %tmp2529 %tmp27 = fptosi float %tmp26 to i3230 %tmp28 = bitcast i32 %tmp27 to float31 %tmp29 = bitcast float %tmp28 to i3232 %tmp30 = icmp ne i32 %tmp29, 033 br i1 %tmp23, label %IF, label %ELSE34 35IF: ; preds = %main_body36 %. = select i1 %tmp30, float 0.000000e+00, float 1.000000e+0037 %.18 = select i1 %tmp30, float 1.000000e+00, float 0.000000e+0038 br label %ENDIF39 40ELSE: ; preds = %main_body41 br i1 %tmp30, label %ENDIF, label %ELSE1742 43ENDIF: ; preds = %ELSE17, %ELSE, %IF44 %temp1.0 = phi float [ %., %IF ], [ %tmp48, %ELSE17 ], [ 0.000000e+00, %ELSE ]45 %temp2.0 = phi float [ 0.000000e+00, %IF ], [ %tmp49, %ELSE17 ], [ 1.000000e+00, %ELSE ]46 %temp.0 = phi float [ %.18, %IF ], [ %tmp47, %ELSE17 ], [ 0.000000e+00, %ELSE ]47 %max.0.i = call float @llvm.maxnum.f32(float %temp.0, float 0.000000e+00)48 %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)49 %max.0.i3 = call float @llvm.maxnum.f32(float %temp1.0, float 0.000000e+00)50 %clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)51 %max.0.i1 = call float @llvm.maxnum.f32(float %temp2.0, float 0.000000e+00)52 %clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)53 %tmp31 = insertelement <4 x float> poison, float %clamp.i, i32 054 %tmp32 = insertelement <4 x float> %tmp31, float %clamp.i4, i32 155 %tmp33 = insertelement <4 x float> %tmp32, float %clamp.i2, i32 256 %tmp34 = insertelement <4 x float> %tmp33, float 1.000000e+00, i32 357 call void @llvm.r600.store.swizzle(<4 x float> %tmp34, i32 0, i32 0)58 ret void59 60ELSE17: ; preds = %ELSE61 %tmp35 = fadd float 0.000000e+00, 0x3FC99999A000000062 %tmp36 = fadd float 0.000000e+00, 0x3FC99999A000000063 %tmp37 = fadd float 0.000000e+00, 0x3FC99999A000000064 %tmp38 = fadd float %tmp35, 0x3FC99999A000000065 %tmp39 = fadd float %tmp36, 0x3FC99999A000000066 %tmp40 = fadd float %tmp37, 0x3FC99999A000000067 %tmp41 = fadd float %tmp38, 0x3FC99999A000000068 %tmp42 = fadd float %tmp39, 0x3FC99999A000000069 %tmp43 = fadd float %tmp40, 0x3FC99999A000000070 %tmp44 = fadd float %tmp41, 0x3FC99999A000000071 %tmp45 = fadd float %tmp42, 0x3FC99999A000000072 %tmp46 = fadd float %tmp43, 0x3FC99999A000000073 %tmp47 = fadd float %tmp44, 0x3FC99999A000000074 %tmp48 = fadd float %tmp45, 0x3FC99999A000000075 %tmp49 = fadd float %tmp46, 0x3FC99999A000000076 br label %ENDIF77}78 79declare float @llvm.minnum.f32(float, float) #180declare float @llvm.maxnum.f32(float, float) #181 82declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)83 84attributes #0 = { nounwind }85attributes #1 = { nounwind readnone }86