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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s3 4--- |5 define amdgpu_kernel void @schedule_ilp(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) { ret void }6 7 !0 = distinct !{!0}8 !1 = !{!1, !0}9...10 11# Check that the load that defines %4 and its user are scheduled as far apart12# as possible. In this example, the generic machine scheduler's default latency13# heuristic will not be triggered early enough. Verify that our backend handles14# this properly.15 16---17name: schedule_ilp18tracksRegLiveness: true19machineFunctionInfo:20 stackPtrOffsetReg: $sgpr3221stack:22 - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }23 - { id: 1, type: default, offset: 0, size: 4, alignment: 4 }24body: |25 bb.0:26 liveins: $sgpr0_sgpr1_sgpr2_sgpr327 28 ; CHECK-LABEL: name: schedule_ilp29 ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr330 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF32 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF33 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF34 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF35 ; CHECK-NEXT: $exec = S_OR_B64 $exec, [[DEF]], implicit-def $scc36 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0, addrspace 1)37 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF3]], 4, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0, addrspace 1)38 ; CHECK-NEXT: [[GLOBAL_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF3]], 8, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0, addrspace 1)39 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN [[DEF1]], %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out, !noalias !0, addrspace 1)40 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN [[DEF2]], %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out, !noalias !0, addrspace 1)41 ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec42 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 -1, [[GLOBAL_LOAD_DWORD]], implicit $exec43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec44 ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc45 ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]46 ; CHECK-NEXT: S_ENDPGM 0, implicit [[GLOBAL_LOAD_DWORD1]], implicit [[GLOBAL_LOAD_DWORD2]], implicit [[V_MOV_B]]47 %0:sreg_64 = IMPLICIT_DEF48 %1:vgpr_32 = IMPLICIT_DEF49 %2:vgpr_32 = IMPLICIT_DEF50 %3:vreg_64 = IMPLICIT_DEF51 $exec = S_OR_B64 $exec, %0, implicit-def $scc52 BUFFER_STORE_DWORD_OFFEN %1:vgpr_32, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.out, !noalias !0)53 BUFFER_STORE_DWORD_OFFEN %2:vgpr_32, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out, !noalias !0)54 %4:vgpr_32 = GLOBAL_LOAD_DWORD %3, 0, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0)55 %5:vgpr_32 = GLOBAL_LOAD_DWORD %3, 4, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0)56 %6:vgpr_32 = GLOBAL_LOAD_DWORD %3, 8, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0)57 %7:sreg_64 = V_CMP_NE_U32_e64 -1, %4, implicit $exec58 %8:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec59 %9:sreg_64 = COPY $exec, implicit-def $exec60 %10:sreg_64 = S_AND_B64 %9:sreg_64, %7:sreg_64, implicit-def dead $scc61 $exec = S_MOV_B64_term %1062 S_ENDPGM 0, implicit %5, implicit %6, implicit %863...64