33 lines · plain
1# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass machine-scheduler --misched-prera-direction=topdown -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s2# REQUIRES: asserts3 4# Check that cycle counts are consistent with hazards.5 6# CHECK: Cycle: 3 TopQ.A7# CHECK: hazard: SU(6) HWXDL[0]=9c, is later than CurrCycle = 3c8# CHECK-NOT: Cycle: 9 TopQ.A9# CHECK: Cycle: 83 TopQ.A10# CHECK: Checking pending node SU(6)11# CHECK: Move SU(6) into Available Q12 13---14name: pending_queue_ready_cycle15tracksRegLiveness: true16body: |17 bb.0:18 liveins: $sgpr4_sgpr519 20 %2:sgpr_128 = IMPLICIT_DEF21 %14:vgpr_32 = IMPLICIT_DEF22 %15:vgpr_32 = IMPLICIT_DEF23 %18:areg_512 = IMPLICIT_DEF24 %18:areg_512 = V_MFMA_F32_16X16X1F32_mac_e64 %15, %14, %18, 0, 0, 0, implicit $mode, implicit $exec25 %5:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET %2, 0, 0, 0, 0, implicit $exec26 %18:areg_512 = V_MFMA_F32_16X16X1F32_mac_e64 %15, %14, %18, 0, 0, 0, implicit $mode, implicit $exec27 undef %84.sub0:vreg_128_align2 = V_ADD_U32_e32 %5.sub0, %14, implicit $exec28 %7:vreg_512 = COPY %1829 SCHED_BARRIER 030 S_NOP 0, implicit %18, implicit %7, implicit %8431 S_ENDPGM 032...33