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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s2 3; Interleave loads and stores to fit into 9 VGPR limit.4; This requires to avoid load/store clustering.5 6; Reschedule the second scheduling region without clustering while7; the first region is skipped.8 9; GCN: global_load_dwordx410; GCN: global_store_dwordx411; GCN: global_load_dwordx412; GCN: global_store_dwordx413; GCN: global_load_dwordx414; GCN: global_store_dwordx415; GCN: NumVgprs: {{[0-9]$}}16; GCN: ScratchSize: 0{{$}}17 18define amdgpu_kernel void @load_store_max_9vgprs(ptr addrspace(1) nocapture noalias readonly %arg, ptr addrspace(1) nocapture noalias %arg1, i1 %cnd) #1 {19bb:20 %id = call i32 @llvm.amdgcn.workitem.id.x()21 %base = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i32 %id22 br i1 %cnd, label %bb1, label %bb223 24bb1:25 %tmp = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 126 %tmp2 = load <4 x i32>, ptr addrspace(1) %tmp, align 427 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 328 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 429 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 530 %tmp6 = load <4 x i32>, ptr addrspace(1) %tmp5, align 431 store <4 x i32> %tmp2, ptr addrspace(1) %arg1, align 432 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 333 store <4 x i32> %tmp4, ptr addrspace(1) %tmp7, align 434 %tmp8 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 535 store <4 x i32> %tmp6, ptr addrspace(1) %tmp8, align 436 br label %bb237 38bb2:39 ret void40}41 42declare i32 @llvm.amdgcn.workitem.id.x() #043 44attributes #0 = { nounwind readnone }45attributes #1 = { "amdgpu-num-vgpr"="9" }46