57 lines · plain
1# REQUIRES: asserts2# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -start-before=machine-scheduler -stop-after=greedy,2 -stress-regalloc=4 -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s3 4--- |5 define amdgpu_kernel void @no_sched_metric_due_to_spills() #0 {6 ret void7 }8 9 attributes #0 = { "amdgpu-flat-work-group-size"="1,256" }10...11 12# This test checks for the following scenario: Unclustered high-RP-reschedule13# stage raises the occupancy target temporarily but no region gets scheduled14# because of constraints. Then, DAG and MFI min-occupancy should not be changed15# at the end of the unclustered schedule stage.16# CHECK: Retrying function scheduling without clustering. Aggressively try to reduce register pressure to achieve occupancy 5.17# CHECK: Unclustered High Register Pressure Reschedule: No regions scheduled, min occupancy stays at 4, MFI occupancy stays at 4.18 19---20name: no_sched_metric_due_to_spills21tracksRegLiveness: true22machineFunctionInfo:23 stackPtrOffsetReg: '$sgpr32'24 occupancy: 425body: |26 bb.0:27 liveins: $vgpr0, $sgpr0_sgpr1, $sgpr1528 29 %0:sgpr_32 = COPY $sgpr1530 %1:sgpr_64 = COPY $sgpr0_sgpr131 %2:vgpr_32 = COPY $vgpr032 %3:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 0, 0 :: (dereferenceable invariant load (s128), addrspace 4)33 undef %4.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 16, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)34 %5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 32, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)35 %6:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 64, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)36 %7:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 84, 0 :: (dereferenceable invariant load (s32), addrspace 4)37 %8:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 112, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)38 %9:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 128, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)39 %10:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 176, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)40 %11:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %1, 192, 0 :: (dereferenceable invariant load (s32), align 8, addrspace 4)41 %12:sreg_64_xexec = S_LOAD_DWORDX2_IMM %1, 216, 0 :: (dereferenceable invariant load (s64), addrspace 4)42 %13:sreg_32 = S_ADD_I32 %12.sub0, 127, implicit-def dead $scc43 %14:sreg_32 = S_ASHR_I32 %13, 31, implicit-def dead $scc44 %15:sreg_32 = S_LSHR_B32 %14, 25, implicit-def dead $scc45 %16:sreg_32 = S_ADD_I32 %13, %15, implicit-def dead $scc46 %17:sreg_32 = S_ASHR_I32 %16, 7, implicit-def dead $scc47 %18:sreg_32 = S_ADD_I32 %12.sub1, 255, implicit-def dead $scc48 %19:sreg_32 = S_ASHR_I32 %18, 31, implicit-def dead $scc49 %20:sreg_32 = S_LSHR_B32 %19, 24, implicit-def dead $scc50 %21:sreg_32 = S_ADD_I32 %18, %20, implicit-def dead $scc51 %22:sreg_32 = S_ASHR_I32 %21, 8, implicit-def dead $scc52 %23:sreg_32 = nsw S_MUL_I32 %22, %1753 %24:sreg_32 = S_ASHR_I32 %0, 31, implicit-def dead $scc54 S_ENDPGM 055 56...57