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1; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -debug-only=machine-scheduler < %s 2>&1 | FileCheck -enable-var-scope %s2; REQUIRES: asserts3 4declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half>, <4 x half>, <32 x float>, i32, i32, i32)5 6; CHECK: Scheduling SU({{[0-9]+}}) {{.*}} V_MFMA_F32_32X32X4F167; CHECK: HWXDL +16x1u8define amdgpu_kernel void @schedule-xdl-resource(ptr addrspace(1) %in, ptr addrspace(1) %out, ptr addrspace(3) %lds, i32 %stride) #0 {9 %in_ptr.1 = getelementptr <32 x float>, ptr addrspace(1) %in, i32 %stride10 %in_ptr.2 = getelementptr <32 x float>, ptr addrspace(1) %in_ptr.1, i32 %stride11 %in_ptr.3 = getelementptr <32 x float>, ptr addrspace(1) %in_ptr.2, i32 %stride12 %in.load.1 = load <32 x float>, ptr addrspace (1) %in_ptr.113 %in.load.2 = load <32 x float>, ptr addrspace (1) %in_ptr.214 %in.load.3 = load <32 x float>, ptr addrspace (1) %in_ptr.315 %lds_ptr.1 = getelementptr <4 x half>, ptr addrspace(3) %lds, i32 %stride16 %lds_ptr.2 = getelementptr <4 x half>, ptr addrspace(3) %lds_ptr.1, i32 %stride17 %lds_ptr.3 = getelementptr <4 x half>, ptr addrspace(3) %lds_ptr.2, i32 %stride18 %lds.load.1 = load <4 x half>, ptr addrspace(3) %lds_ptr.119 %lds.load.2 = load <4 x half>, ptr addrspace(3) %lds_ptr.220 %lds.load.3 = load <4 x half>, ptr addrspace(3) %lds_ptr.321 %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.1, <4 x half> %lds.load.1, <32 x float> %in.load.1, i32 1, i32 1, i32 1)22 %mai.2 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.2, <4 x half> %lds.load.2, <32 x float> %in.load.2, i32 1, i32 1, i32 1)23 %mai.3 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.3, <4 x half> %lds.load.3, <32 x float> %in.load.3, i32 1, i32 1, i32 1)24 %mai.4 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.1, <4 x half> %lds.load.1, <32 x float> %in.load.1, i32 2, i32 2, i32 2)25 %mai.5 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.2, <4 x half> %lds.load.2, <32 x float> %in.load.2, i32 2, i32 2, i32 2)26 %mai.6 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %lds.load.3, <4 x half> %lds.load.3, <32 x float> %in.load.3, i32 2, i32 2, i32 2)27 %out_ptr.1 = getelementptr <32 x float>, ptr addrspace(1) %out, i32 %stride28 %out_ptr.2 = getelementptr <32 x float>, ptr addrspace(1) %out_ptr.1, i32 %stride29 %out_ptr.3 = getelementptr <32 x float>, ptr addrspace(1) %out_ptr.2, i32 %stride30 %out_ptr.4 = getelementptr <32 x float>, ptr addrspace(1) %out_ptr.3, i32 %stride31 %out_ptr.5 = getelementptr <32 x float>, ptr addrspace(1) %out_ptr.4, i32 %stride32 %out_ptr.6 = getelementptr <32 x float>, ptr addrspace(1) %out_ptr.5, i32 %stride33 store <32 x float> %mai.1, ptr addrspace(1) %out_ptr.134 store <32 x float> %mai.2, ptr addrspace(1) %out_ptr.235 store <32 x float> %mai.3, ptr addrspace(1) %out_ptr.336 store <32 x float> %mai.4, ptr addrspace(1) %out_ptr.437 store <32 x float> %mai.5, ptr addrspace(1) %out_ptr.538 store <32 x float> %mai.6, ptr addrspace(1) %out_ptr.639 40 ret void41}42 43attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }44