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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s3 4declare void @llvm.amdgcn.kill(i1)5declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg)6declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float)7declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg)8 9define amdgpu_ps void @_amdgpu_ps_main(float %arg) {10; GFX900-LABEL: _amdgpu_ps_main:11; GFX900: ; %bb.0: ; %bb12; GFX900-NEXT: s_mov_b64 s[4:5], exec13; GFX900-NEXT: s_wqm_b64 exec, exec14; GFX900-NEXT: v_mov_b32_e32 v1, v015; GFX900-NEXT: s_mov_b32 s0, 016; GFX900-NEXT: v_cmp_ngt_f32_e32 vcc, 0, v117; GFX900-NEXT: ; implicit-def: $vgpr018; GFX900-NEXT: s_and_saveexec_b64 s[2:3], vcc19; GFX900-NEXT: s_xor_b64 s[6:7], exec, s[2:3]20; GFX900-NEXT: s_cbranch_execz .LBB0_221; GFX900-NEXT: ; %bb.1: ; %bb122; GFX900-NEXT: v_mov_b32_e32 v0, 023; GFX900-NEXT: s_mov_b32 s1, s024; GFX900-NEXT: s_mov_b32 s2, s025; GFX900-NEXT: s_mov_b32 s3, s026; GFX900-NEXT: s_mov_b32 s8, s027; GFX900-NEXT: s_mov_b32 s9, s028; GFX900-NEXT: s_mov_b32 s10, s029; GFX900-NEXT: s_mov_b32 s11, s030; GFX900-NEXT: s_mov_b32 s12, s031; GFX900-NEXT: s_mov_b32 s13, s032; GFX900-NEXT: s_mov_b32 s14, s033; GFX900-NEXT: s_mov_b32 s15, s034; GFX900-NEXT: image_sample v[0:1], v[0:1], s[8:15], s[0:3] dmask:0x335; GFX900-NEXT: .LBB0_2: ; %Flow36; GFX900-NEXT: s_or_saveexec_b64 s[0:1], s[6:7]37; GFX900-NEXT: s_and_b64 exec, exec, s[4:5]38; GFX900-NEXT: s_and_b64 s[0:1], exec, s[0:1]39; GFX900-NEXT: v_mov_b32_e32 v2, 1.040; GFX900-NEXT: s_xor_b64 exec, exec, s[0:1]41; GFX900-NEXT: s_cbranch_execz .LBB0_542; GFX900-NEXT: ; %bb.3: ; %bb543; GFX900-NEXT: s_andn2_b64 s[4:5], s[4:5], exec44; GFX900-NEXT: s_cbranch_scc0 .LBB0_645; GFX900-NEXT: ; %bb.4: ; %bb546; GFX900-NEXT: s_mov_b64 exec, 047; GFX900-NEXT: s_waitcnt vmcnt(0)48; GFX900-NEXT: v_mov_b32_e32 v1, 049; GFX900-NEXT: v_mov_b32_e32 v2, v150; GFX900-NEXT: .LBB0_5: ; %bb651; GFX900-NEXT: s_or_b64 exec, exec, s[0:1]52; GFX900-NEXT: s_waitcnt vmcnt(0)53; GFX900-NEXT: v_cvt_pkrtz_f16_f32 v1, 0, v154; GFX900-NEXT: v_cvt_pkrtz_f16_f32 v0, v2, v055; GFX900-NEXT: exp mrt0 off, off, off, off compr56; GFX900-NEXT: s_endpgm57; GFX900-NEXT: .LBB0_6:58; GFX900-NEXT: s_mov_b64 exec, 059; GFX900-NEXT: exp null off, off, off, off done vm60; GFX900-NEXT: s_endpgm61bb:62 %i = fcmp olt float %arg, 0.000000e+0063 br i1 %i, label %bb5, label %bb164 65bb1:66 %i2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0.000000e+00, float %arg, <8 x i32> zeroinitializer, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)67 %i3 = extractelement <4 x float> %i2, i64 168 %i4 = extractelement <4 x float> %i2, i64 069 br label %bb670 71bb5:72 call void @llvm.amdgcn.kill(i1 false)73 br label %bb674 75bb6:76 %i7 = phi float [ 0.000000e+00, %bb5 ], [ %i3, %bb1 ]77 %i8 = phi float [ 0.000000e+00, %bb5 ], [ 1.000000e+00, %bb1 ]78 %i9 = phi float [ poison, %bb5 ], [ %i4, %bb1 ]79 %i10 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 0.000000e+00, float %i7)80 %i11 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %i8, float %i9)81 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> %i10, <2 x half> %i11, i1 false, i1 false)82 ret void83}84