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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4; When a frame index offset is more than 12-bits, make sure we don't store5; it in mubuf's offset field.6 7; Also, make sure we use the same register for storing the scratch buffer addresss8; for both stores. This register is allocated by the register scavenger, so we9; should be able to reuse the same regiser for each scratch buffer access.10 11; GCN-LABEL: {{^}}legal_offset_fi:12; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:4{{$}}13; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x800414; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}15 16define amdgpu_kernel void @legal_offset_fi(ptr addrspace(1) %out, i32 %cond, i32 %if_offset, i32 %else_offset) {17entry:18 %scratch0 = alloca [8192 x i32], addrspace(5)19 %scratch1 = alloca [8192 x i32], addrspace(5)20 21 store i32 1, ptr addrspace(5) %scratch022 23 store i32 2, ptr addrspace(5) %scratch124 25 %cmp = icmp eq i32 %cond, 026 br i1 %cmp, label %if, label %else27 28if:29 %if_ptr = getelementptr [8192 x i32], ptr addrspace(5) %scratch0, i32 0, i32 %if_offset30 %if_value = load i32, ptr addrspace(5) %if_ptr31 br label %done32 33else:34 %else_ptr = getelementptr [8192 x i32], ptr addrspace(5) %scratch1, i32 0, i32 %else_offset35 %else_value = load i32, ptr addrspace(5) %else_ptr36 br label %done37 38done:39 %value = phi i32 [%if_value, %if], [%else_value, %else]40 store i32 %value, ptr addrspace(1) %out41 ret void42 43 ret void44 45}46 47; GCN-LABEL: {{^}}legal_offset_fi_offset:48; GCN-DAG: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}49; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, 4,50; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, 0x800451; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}52 53define amdgpu_kernel void @legal_offset_fi_offset(ptr addrspace(1) %out, i32 %cond, ptr addrspace(1) %offsets, i32 %if_offset, i32 %else_offset) {54entry:55 %scratch0 = alloca [8192 x i32], addrspace(5)56 %scratch1 = alloca [8192 x i32], addrspace(5)57 58 %offset0 = load i32, ptr addrspace(1) %offsets59 %scratchptr0 = getelementptr [8192 x i32], ptr addrspace(5) %scratch0, i32 0, i32 %offset060 store i32 %offset0, ptr addrspace(5) %scratchptr061 62 %offsetptr1 = getelementptr i32, ptr addrspace(1) %offsets, i32 163 %offset1 = load i32, ptr addrspace(1) %offsetptr164 %scratchptr1 = getelementptr [8192 x i32], ptr addrspace(5) %scratch1, i32 0, i32 %offset165 store i32 %offset1, ptr addrspace(5) %scratchptr166 67 %cmp = icmp eq i32 %cond, 068 br i1 %cmp, label %if, label %else69 70if:71 %if_ptr = getelementptr [8192 x i32], ptr addrspace(5) %scratch0, i32 0, i32 %if_offset72 %if_value = load i32, ptr addrspace(5) %if_ptr73 br label %done74 75else:76 %else_ptr = getelementptr [8192 x i32], ptr addrspace(5) %scratch1, i32 0, i32 %else_offset77 %else_value = load i32, ptr addrspace(5) %else_ptr78 br label %done79 80done:81 %value = phi i32 [%if_value, %if], [%else_value, %else]82 store i32 %value, ptr addrspace(1) %out83 ret void84}85 86; GCN-LABEL: {{^}}neg_vaddr_offset_inbounds:87; GCN: s_add_i32 [[ADD0:s[0-9]+]], s{{[0-9]+}}, 488; GCN: s_add_i32 [[ADD1:s[0-9]+]], [[ADD0]], 1689; GCN: v_mov_b32_e32 [[V_ADD:v[0-9]+]], [[ADD1]]90; GCN: buffer_store_dword v{{[0-9]+}}, [[V_ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}91define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) {92entry:93 %array = alloca [8192 x i32], addrspace(5)94 %ptr_offset = add i32 %offset, 495 %ptr = getelementptr inbounds [8192 x i32], ptr addrspace(5) %array, i32 0, i32 %ptr_offset96 store i32 0, ptr addrspace(5) %ptr97 ret void98}99 100; GCN-LABEL: {{^}}neg_vaddr_offset:101; GCN: s_add_i32 [[ADD0:s[0-9]+]], s{{[0-9]+}}, 4102; GCN: s_add_i32 [[ADD1:s[0-9]+]], [[ADD0]], 16103; GCN: v_mov_b32_e32 [[V_ADD:v[0-9]+]], [[ADD1]]104; GCN: buffer_store_dword v{{[0-9]+}}, [[V_ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}105define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) {106entry:107 %array = alloca [8192 x i32], addrspace(5)108 %ptr_offset = add i32 %offset, 4109 %ptr = getelementptr [8192 x i32], ptr addrspace(5) %array, i32 0, i32 %ptr_offset110 store i32 0, ptr addrspace(5) %ptr111 ret void112}113 114; GCN-LABEL: {{^}}pos_vaddr_offset:115; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:20116define amdgpu_kernel void @pos_vaddr_offset(ptr addrspace(1) %out, i32 %offset) {117entry:118 %array = alloca [8192 x i32], addrspace(5)119 %ptr = getelementptr [8192 x i32], ptr addrspace(5) %array, i32 0, i32 4120 store i32 0, ptr addrspace(5) %ptr121 %load_ptr = getelementptr [8192 x i32], ptr addrspace(5) %array, i32 0, i32 %offset122 %val = load i32, ptr addrspace(5) %load_ptr123 store i32 %val, ptr addrspace(1) %out124 ret void125}126