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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O0 < %s -debug-only=isel 2>&1 | FileCheck --check-prefixes=GCN,GCN-DEFAULT %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O0 < %s -debug-only=isel -dag-dump-verbose 2>&1 | FileCheck --check-prefixes=GCN,GCN-VERBOSE %s4 5; REQUIRES: asserts6 7; GCN-LABEL: === test_sdag_dump8; GCN: Initial selection DAG: %bb.0 'test_sdag_dump:entry'9; GCN: SelectionDAG has 11 nodes:10 11; GCN-DEFAULT: t0: ch,glue = EntryToken12; GCN-DEFAULT: t2: f32,ch = CopyFromReg t0, Register:f32 %013; GCN-DEFAULT: t7: i32 = TargetConstant<14; GCN-DEFAULT: t5: f32 = fadd t2, t215; GCN-DEFAULT: t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %116; GCN-DEFAULT: t6: f32 = fadd # D:1 t5, t417; GCN-DEFAULT: t9: ch,glue = CopyToReg # D:1 t0, Register:f32 $vgpr0, t618; GCN-DEFAULT: t10: ch = AMDGPUISD::RETURN_TO_EPILOG t9, Register:f32 $vgpr0, t9:119 20; GCN-VERBOSE: t0: ch,glue = EntryToken # D:021; GCN-VERBOSE: t2: f32,ch = CopyFromReg [ORD=1] # D:0 t0, Register:f32 %0 # D:022; GCN-VERBOSE: t7: i32 = TargetConstant<23; GCN-VERBOSE: t5: f32 = fadd [ORD=2] # D:0 t2, t224; GCN-VERBOSE: t4: f32,ch = CopyFromReg [ORD=1] # D:1 t0, Register:f32 %1 # D:025; GCN-VERBOSE: t6: f32 = fadd [ORD=3] # D:1 t5, t426; GCN-VERBOSE: t9: ch,glue = CopyToReg [ORD=4] # D:1 t0, Register:f32 $vgpr0 # D:0, t627; GCN-VERBOSE: t10: ch = AMDGPUISD::RETURN_TO_EPILOG [ORD=4] # D:0 t9, Register:f32 $vgpr0 # D:0, t9:128 29define amdgpu_ps float @test_sdag_dump(float inreg %scalar, float %vector) {30entry:31 %sadd = fadd float %scalar, %scalar32 %ret = fadd float %sadd, %vector33 ret float %ret34}35 36declare i32 @llvm.amdgcn.workitem.id.x()37