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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=FIJI,GCN %s3 4; GCN-LABEL: {{^}}test_add_co_sdwa:5; GFX9: v_add_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}7; FIJI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_08; FIJI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}9define void @test_add_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {10bb:11 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()12 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp13 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 414 %tmp5 = and i32 %tmp4, 25515 %tmp6 = zext i32 %tmp5 to i6416 %tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp17 %tmp8 = load i64, ptr addrspace(1) %tmp7, align 818 %tmp9 = add nsw i64 %tmp8, %tmp619 store i64 %tmp9, ptr addrspace(1) %tmp7, align 820 ret void21}22 23 24; GCN-LABEL: {{^}}test_sub_co_sdwa:25; GFX9: v_sub_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_026; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}27; FIJI: v_sub_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_028; FIJI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}29define void @test_sub_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {30bb:31 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()32 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp33 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 434 %tmp5 = and i32 %tmp4, 25535 %tmp6 = zext i32 %tmp5 to i6436 %tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp37 %tmp8 = load i64, ptr addrspace(1) %tmp7, align 838 %tmp9 = sub nsw i64 %tmp8, %tmp639 store i64 %tmp9, ptr addrspace(1) %tmp7, align 840 ret void41}42 43; GCN-LABEL: {{^}}test1_add_co_sdwa:44; GFX9: v_add_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_045; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}46; GFX9: v_add_co_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_047; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}48; FIJI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_049; FIJI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}50; FIJI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_051; FIJI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}52define amdgpu_kernel void @test1_add_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, ptr addrspace(1) %arg2) #0 {53bb:54 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()55 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp56 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 457 %tmp5 = and i32 %tmp4, 25558 %tmp6 = zext i32 %tmp5 to i6459 %tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp60 %tmp8 = load i64, ptr addrspace(1) %tmp7, align 861 %tmp9 = add nsw i64 %tmp8, %tmp662 store i64 %tmp9, ptr addrspace(1) %tmp7, align 863 %tmp13 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp64 %tmp14 = load i32, ptr addrspace(1) %tmp13, align 465 %tmp15 = and i32 %tmp14, 25566 %tmp16 = zext i32 %tmp15 to i6467 %tmp17 = getelementptr inbounds i64, ptr addrspace(1) %arg2, i32 %tmp68 %tmp18 = load i64, ptr addrspace(1) %tmp17, align 869 %tmp19 = add nsw i64 %tmp18, %tmp1670 store i64 %tmp19, ptr addrspace(1) %tmp17, align 871 ret void72}73 74declare i32 @llvm.amdgcn.workitem.id.x()75