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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck %s3 4; In this test, V_CNDMASK_B32_e64 gets converted to V_CNDMASK_B32_e32,5; but the expected conversion to SDWA does not occur. This led to a6; compilation error, because the use of $vcc in the resulting7; instruction must be fixed to $vcc_lo for wave32 which only happened8; after the full conversion to SDWA.9 10define void @quux(i32 %arg, i1 %arg1, i1 %arg2) {11; CHECK-LABEL: quux:12; CHECK: ; %bb.0: ; %bb13; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14; CHECK-NEXT: v_and_b32_e32 v1, 1, v115; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 1, v116; CHECK-NEXT: v_mov_b32_e32 v1, 017; CHECK-NEXT: s_and_saveexec_b32 s4, vcc_lo18; CHECK-NEXT: s_cbranch_execz .LBB0_219; CHECK-NEXT: ; %bb.1: ; %bb320; CHECK-NEXT: v_and_b32_e32 v1, 0x3ff, v3121; CHECK-NEXT: v_mov_b32_e32 v2, 022; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v023; CHECK-NEXT: v_mul_u32_u24_e32 v1, 5, v124; CHECK-NEXT: global_load_ushort v1, v[1:2], off offset:325; CHECK-NEXT: v_mov_b32_e32 v2, 0xffff26; CHECK-NEXT: s_waitcnt vmcnt(0)27; CHECK-NEXT: v_and_b32_sdwa v0, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_028; CHECK-NEXT: v_mov_b32_e32 v1, 2429; CHECK-NEXT: v_mov_b32_e32 v2, 0xff30; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo31; CHECK-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD32; CHECK-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD33; CHECK-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD34; CHECK-NEXT: .LBB0_2: ; %bb935; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s436; CHECK-NEXT: v_mov_b32_e32 v2, 037; CHECK-NEXT: v_mov_b32_e32 v3, 038; CHECK-NEXT: global_store_byte v[2:3], v1, off39; CHECK-NEXT: s_setpc_b64 s[30:31]40bb:41 br i1 %arg1, label %bb9, label %bb342 43bb3: ; preds = %bb44 %call = tail call i32 @llvm.amdgcn.workitem.id.x()45 %mul = mul i32 %call, 546 %zext = zext i32 %mul to i6447 %getelementptr = getelementptr i8, ptr addrspace(1) null, i64 %zext48 %getelementptr4 = getelementptr i8, ptr addrspace(1) %getelementptr, i64 449 %load = load i8, ptr addrspace(1) %getelementptr4, align 150 %getelementptr5 = getelementptr i8, ptr addrspace(1) %getelementptr, i64 351 %load6 = load i8, ptr addrspace(1) %getelementptr5, align 152 %insertelement = insertelement <5 x i8> poison, i8 %load, i64 453 %select = select i1 %arg2, <5 x i8> %insertelement, <5 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 0>54 %insertelement7 = insertelement <5 x i8> %select, i8 %load6, i64 055 %icmp = icmp ult i32 0, %arg56 %select8 = select i1 %icmp, <5 x i8> zeroinitializer, <5 x i8> %insertelement757 %shufflevector = shufflevector <5 x i8> zeroinitializer, <5 x i8> %select8, <5 x i32> <i32 0, i32 1, i32 7, i32 8, i32 9>58 br label %bb959 60bb9: ; preds = %bb3, %bb61 %phi = phi <5 x i8> [ %shufflevector, %bb3 ], [ zeroinitializer, %bb ]62 %extractelement = extractelement <5 x i8> %phi, i64 063 store i8 %extractelement, ptr addrspace(1) null, align 164 ret void65}66