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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -simplify-mir -run-pass=si-peephole-sdwa -o - %s | FileCheck %s3 4# Test the combination of SDWA selections in si-peephole-sdwa. In each5# example, the SDWA destination selection specified on the first instruction6# must be combined with the destination selection that the pass determines7# for the operand, i.e. the second instruction. In the cases where8# this is not possible, no conversion should occur.9 10---11name: op_select_word_1_instr_select_dword12tracksRegLiveness: true13body: |14 bb.0:15 liveins: $vgpr016 ; CHECK-LABEL: name: op_select_word_1_instr_select_dword17 ; CHECK: liveins: $vgpr018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr020 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec21 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec22 ; CHECK-NEXT: S_ENDPGM 023 %1:vgpr_32 = COPY $vgpr024 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 6, 0, 0, 0, implicit $exec25 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */26 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec27 28 S_ENDPGM 029...30 31---32name: op_select_word_1_instr_select_word_133tracksRegLiveness: true34body: |35 bb.0:36 liveins: $vgpr037 ; CHECK-LABEL: name: op_select_word_1_instr_select_word_138 ; CHECK: liveins: $vgpr039 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr041 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec42 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec43 ; CHECK-NEXT: S_ENDPGM 044 %1:vgpr_32 = COPY $vgpr045 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 5, 0, 0, 0, implicit $exec46 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */47 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec48 49 S_ENDPGM 050...51 52---53name: op_select_word_1_instr_select_word_054tracksRegLiveness: true55body: |56 bb.0:57 liveins: $vgpr058 ; CHECK-LABEL: name: op_select_word_1_instr_select_word_059 ; CHECK: liveins: $vgpr060 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr062 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec63 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec64 ; CHECK-NEXT: S_ENDPGM 065 %1:vgpr_32 = COPY $vgpr066 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 4, 0, 0, 0, implicit $exec67 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */68 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec69 70 S_ENDPGM 071...72 73---74name: op_select_word_1_instr_select_byte_375tracksRegLiveness: true76body: |77 bb.0:78 liveins: $vgpr079 ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_380 ; CHECK: liveins: $vgpr081 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr083 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec84 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 16, [[V_LSHRREV_B32_sdwa]], implicit $exec85 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec86 ; CHECK-NEXT: S_ENDPGM 087 %1:vgpr_32 = COPY $vgpr088 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 3, 0, 0, 0, implicit $exec89 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */90 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec91 92 S_ENDPGM 093...94 95---96name: op_select_word_1_instr_select_byte_297tracksRegLiveness: true98body: |99 bb.0:100 liveins: $vgpr0101 ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_2102 ; CHECK: liveins: $vgpr0103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0105 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 0, 0, implicit $exec106 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 16, [[V_LSHRREV_B32_sdwa]], implicit $exec107 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec108 ; CHECK-NEXT: S_ENDPGM 0109 %1:vgpr_32 = COPY $vgpr0110 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 0, 0, implicit $exec111 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */112 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec113 114 S_ENDPGM 0115...116 117---118name: op_select_word_1_instr_select_byte_1119tracksRegLiveness: true120body: |121 bb.0:122 liveins: $vgpr0123 ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_1124 ; CHECK: liveins: $vgpr0125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0127 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec128 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec129 ; CHECK-NEXT: S_ENDPGM 0130 %1:vgpr_32 = COPY $vgpr0131 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 1, 0, 0, 0, implicit $exec132 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */133 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec134 135 S_ENDPGM 0136...137 138---139name: op_select_word_1_instr_select_byte_0140tracksRegLiveness: true141body: |142 bb.0:143 liveins: $vgpr0144 ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_0145 ; CHECK: liveins: $vgpr0146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0148 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 0, 0, implicit $exec149 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec150 ; CHECK-NEXT: S_ENDPGM 0151 %1:vgpr_32 = COPY $vgpr0152 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 0, 0, 0, 0, implicit $exec153 %3:vgpr_32 = V_LSHLREV_B32_e32 16, %2, implicit $exec /* Select WORD_1 */154 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec155 156 S_ENDPGM 0157...158 159---160name: op_select_byte_3_instr_select_dword161tracksRegLiveness: true162body: |163 bb.0:164 liveins: $vgpr0165 ; CHECK-LABEL: name: op_select_byte_3_instr_select_dword166 ; CHECK: liveins: $vgpr0167 ; CHECK-NEXT: {{ $}}168 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0169 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec170 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec171 ; CHECK-NEXT: S_ENDPGM 0172 %1:vgpr_32 = COPY $vgpr0173 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 6, 0, 0, 0, implicit $exec174 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */175 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec176 177 S_ENDPGM 0178...179 180---181name: op_select_byte_3_instr_select_word_1182tracksRegLiveness: true183body: |184 bb.0:185 liveins: $vgpr0186 ; CHECK-LABEL: name: op_select_byte_3_instr_select_word_1187 ; CHECK: liveins: $vgpr0188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0190 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec191 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec192 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec193 ; CHECK-NEXT: S_ENDPGM 0194 %1:vgpr_32 = COPY $vgpr0195 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 5, 0, 0, 0, implicit $exec196 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */197 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec198 199 S_ENDPGM 0200...201 202---203name: op_select_byte_3_instr_select_word_0204tracksRegLiveness: true205body: |206 bb.0:207 liveins: $vgpr0208 ; CHECK-LABEL: name: op_select_byte_3_instr_select_word_0209 ; CHECK: liveins: $vgpr0210 ; CHECK-NEXT: {{ $}}211 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0212 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 4, 0, 0, 0, implicit $exec213 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec214 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec215 ; CHECK-NEXT: S_ENDPGM 0216 %1:vgpr_32 = COPY $vgpr0217 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 4, 0, 0, 0, implicit $exec218 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */219 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec220 221 S_ENDPGM 0222...223 224---225name: op_select_byte_3_instr_select_byte_3226tracksRegLiveness: true227body: |228 bb.0:229 liveins: $vgpr0230 ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_3231 ; CHECK: liveins: $vgpr0232 ; CHECK-NEXT: {{ $}}233 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0234 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec235 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec236 ; CHECK-NEXT: S_ENDPGM 0237 %1:vgpr_32 = COPY $vgpr0238 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 3, 0, 0, 0, implicit $exec239 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */240 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec241 242 S_ENDPGM 0243...244 245---246name: op_select_byte_3_instr_select_byte_2247tracksRegLiveness: true248body: |249 bb.0:250 liveins: $vgpr0251 ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_2252 ; CHECK: liveins: $vgpr0253 ; CHECK-NEXT: {{ $}}254 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0255 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 0, 0, implicit $exec256 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec257 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec258 ; CHECK-NEXT: S_ENDPGM 0259 %1:vgpr_32 = COPY $vgpr0260 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 0, 0, implicit $exec261 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */262 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec263 264 S_ENDPGM 0265...266 267---268name: op_select_byte_3_instr_select_byte_1269tracksRegLiveness: true270body: |271 bb.0:272 liveins: $vgpr0273 ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_1274 ; CHECK: liveins: $vgpr0275 ; CHECK-NEXT: {{ $}}276 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0277 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 1, 0, 0, 0, implicit $exec278 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec279 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec280 ; CHECK-NEXT: S_ENDPGM 0281 %1:vgpr_32 = COPY $vgpr0282 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 1, 0, 0, 0, implicit $exec283 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */284 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec285 286 S_ENDPGM 0287...288 289---290name: op_select_byte_3_instr_select_byte_0291tracksRegLiveness: true292body: |293 bb.0:294 liveins: $vgpr0295 ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_0296 ; CHECK: liveins: $vgpr0297 ; CHECK-NEXT: {{ $}}298 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0299 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 0, 0, 0, 0, implicit $exec300 ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec301 ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec302 ; CHECK-NEXT: S_ENDPGM 0303 %1:vgpr_32 = COPY $vgpr0304 %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 0, 0, 0, 0, implicit $exec305 %3:vgpr_32 = V_LSHLREV_B32_e32 24, %2, implicit $exec /* Select BYTE_3 */306 %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec307 308 S_ENDPGM 0309...310