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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -o - < %s | FileCheck -check-prefix=CHECK %s3 4; The si-peephole-sdwa pass has mishandled the selections of preexisting sdwa instructions5; which led to an instruction of this shape:6; v_lshlrev_b32_sdwa v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_17; instead of8; v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_09 10define amdgpu_kernel void @widget(ptr addrspace(1) %arg, i1 %arg1, ptr addrspace(3) %arg2, ptr addrspace(3) %arg3) {11; CHECK-LABEL: widget:12; CHECK: ; %bb.0: ; %bb13; CHECK-NEXT: s_clause 0x114; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x015; CHECK-NEXT: s_load_dword s2, s[8:9], 0x816; CHECK-NEXT: s_waitcnt lgkmcnt(0)17; CHECK-NEXT: global_load_sbyte v0, v0, s[0:1] offset:218; CHECK-NEXT: s_bitcmp1_b32 s2, 019; CHECK-NEXT: s_cselect_b32 s0, -1, 020; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s021; CHECK-NEXT: s_cbranch_vccz .LBB0_222; CHECK-NEXT: ; %bb.1: ; %bb1923; CHECK-NEXT: v_mov_b32_e32 v1, 024; CHECK-NEXT: ds_write_b32 v1, v125; CHECK-NEXT: .LBB0_2: ; %bb2026; CHECK-NEXT: s_mov_b32 s0, exec_lo27; CHECK-NEXT: s_waitcnt vmcnt(0)28; CHECK-NEXT: v_cmpx_ne_u16_e32 0, v029; CHECK-NEXT: s_xor_b32 s0, exec_lo, s030; CHECK-NEXT: s_cbranch_execz .LBB0_431; CHECK-NEXT: ; %bb.3: ; %bb1132; CHECK-NEXT: v_mov_b32_e32 v1, 233; CHECK-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_034; CHECK-NEXT: v_mov_b32_e32 v1, 035; CHECK-NEXT: ds_write_b32 v0, v1 offset:8436; CHECK-NEXT: .LBB0_4: ; %bb1437; CHECK-NEXT: s_endpgm38bb:39 %call = tail call i32 @llvm.amdgcn.workitem.id.x()40 %zext = zext i32 %call to i6441 %getelementptr = getelementptr i8, ptr addrspace(1) %arg, i64 %zext42 %load = load i8, ptr addrspace(1) %getelementptr, align 143 %or = or disjoint i32 %call, 144 %zext4 = zext i32 %or to i6445 %getelementptr5 = getelementptr i8, ptr addrspace(1) %arg, i64 %zext446 %load6 = load i8, ptr addrspace(1) %getelementptr5, align 147 %or7 = or disjoint i32 %call, 248 %zext8 = zext i32 %or7 to i6449 %getelementptr9 = getelementptr i8, ptr addrspace(1) %arg, i64 %zext850 %load10 = load i8, ptr addrspace(1) %getelementptr9, align 151 br i1 %arg1, label %bb19, label %bb2052 53bb11: ; preds = %bb2054 %zext12 = zext i8 %load10 to i6455 %getelementptr13 = getelementptr nusw [14 x i32], ptr addrspace(3) inttoptr (i32 84 to ptr addrspace(3)), i64 0, i64 %zext1256 store i32 0, ptr addrspace(3) %getelementptr13, align 457 br label %bb1458 59bb14: ; preds = %bb20, %bb1160 %zext15 = zext i8 %load6 to i6461 %getelementptr16 = getelementptr [14 x i32], ptr addrspace(3) %arg2, i64 0, i64 %zext1562 %zext17 = zext i8 %load to i6463 %getelementptr18 = getelementptr [14 x i32], ptr addrspace(3) %arg3, i64 0, i64 %zext1764 ret void65 66bb19: ; preds = %bb67 store i32 0, ptr addrspace(3) null, align 468 br label %bb2069 70bb20: ; preds = %bb19, %bb71 %icmp = icmp eq i8 %load10, 072 br i1 %icmp, label %bb14, label %bb1173}74 75; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)76declare noundef i32 @llvm.amdgcn.workitem.id.x() #077 78attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }79